Changeset 81 for anr/section-1.tex

Timestamp:

Feb 3, 2010, 2:24:04 PM (15 years ago)

Author:

coach

Message:

Paul: minor modifications in Sect. 1

File:

• anr/section-1.tex (modified) (5 diffs)

anr/section-1.tex

@@ -12 +12 @@
 Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
 implement a complete MPSoC with multiple processors and several
-coprocessors for few keuros per device.
+coprocessors for a few keuros per device.
 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
 Co-design, High-Level Synthesis...) are now mature and allow the automation of
@@ -24 +24 @@
 SoCLib infrastructure~\cite{soclib}, and optimized for the design of
 multi-processors digital systems targetting FPGA devices.
-Such digital system are generally integrated
-into one or several chips, and there is two types of applications:
+Such digital systems are generally integrated
+into one or several chips, and there are two types of applications:
 It can be embedded (autonomous) applications
 such as personal digital assistants (PDA), ambiant computing components
@@ -79 +79 @@
     Coach will define and implement an homogeneous HW/SW communication infrastructure and
     communication APIs (Application Programming Interface).
-    These laters are on chip communications between processors and coprocessors,
+    These laters are on-chip communications between processors and coprocessors,
     and external communications between the FPGA and the host PC. 
 \end{description}
@@ -122 +122 @@
 extension of the SoCLib platform.
 \par
-The main development of the COACH project steps are: 
+The main development steps of the COACH project are: 
 \begin{enumerate}
    \item Definition of the end user inputs:
@@ -142 +142 @@
 \end{enumerate}
 \par
-The two major FPGA companies \altera and \xilinx are participating to this
+The two major FPGA companies \altera and \xilinx are participating in this
 project to support the partners providing the software technologies, and to
 help to generate efficient bitsream for both FPGA families.