Changeset 97 for anr/section-1.tex
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anr/section-1.tex
r89 r97 2 2 The market of digital systems is about 4,600 M\$ today and is estimated to 3 3 5,600 M\$ in 2012. However the ever growing applications complexity involves 4 higherintegration of heterogeneous technologies and requires the design of4 integration of heterogeneous technologies and requires the design of 5 5 complex Multi-Processors System on Chip (MPSoC). 6 During the last decade, the design of complex digital ASICs (Application Specific 6 \par 7 During the last decade, the design of ASICs (Application Specific 7 8 Integrated Circuits) appeared to be more and more reserved to high volume markets, because 8 9 the design and fabrication costs of such components exploded, due to increasing NRE (Non 9 10 Recurring-Engineering) costs. 10 \\ 11 FPGA (Field Programmable Gate Array) components, such as the 11 Fortunately, FPGA (Field Programmable Gate Array) components, such as the 12 12 Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays 13 implement a complete MPSoC with multiple processors and several 13 implement a complete MPSoC with multiple processors and several dedicated 14 14 coprocessors for a few keuros per device. 15 15 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, … … 20 20 major companies to design innovative devices and to enter new, low and 21 21 medium volume markets. 22 \ \22 \par 23 23 The objective of COACH is to provide an integrated design flow, based on the 24 24 SoCLib infrastructure~\cite{soclib}, and optimized for the design of 25 multi-processors digital systems target ting FPGA devices.25 multi-processors digital systems targeting FPGA devices. 26 26 Such digital systems are generally integrated 27 27 into one or several chips, and there are two types of applications: 28 Itcan be embedded (autonomous) applications29 such as personal digital assistants (PDA), ambiant computing components 28 They can be embedded (autonomous) applications 29 such as personal digital assistants (PDA), ambiant computing components, 30 30 or wireless sensor networks (WSN) 31 31 They can also be extension boards connected to a PC to accelerate a specific computation, 32 32 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). 33 \\ 34 The COACH project fundamental issues are related to design methodologies 35 for digital systems, providing estimation, exploration and design tools 36 targeting both performance and power optimization at all the abstraction 37 levels of the flow (system, architecture, algorithm and logic). 38 33 \par 39 34 %verrous scientifiques et techniques 40 35 \vspace*{.9ex}\par 41 The COACH environment mixes and integrates several hardware and software technologies. 42 The more important technologies are: 36 The COACH environment will integrate several hardware and software technologies: 43 37 \begin{description} 44 38 \item[Design Space Exploration] … … 60 54 The HLS tools of COACH will support a common language and coding style to avoid 61 55 re-engineering by the designer. 62 \item[ Targeted hardware architecture and technology]56 \item[Platform based design] 63 57 COACH will handle both \altera and \xilinx FPGA devices. 64 58 COACH will define architectural templates that can be customized by adding 65 59 dedicated coprocessors and ASIPs and by fixing template parameters such as 66 the number of CPU and the operating system. 60 the number of embedded processors or the number of sizes of embedde memory banks, 61 or the embedded the operating system. 67 62 Basically, the 3 following architectural templates will be provided: 68 63 \begin{enumerate} … … 76 71 Moreover, the specification of the application will be independant of both the 77 72 architectural template and the target FPGA device. 78 \item[ Communication interfaces]79 Coach will define andimplement an homogeneous HW/SW communication infrastructure and80 communication APIs (Application Programming Interface) .81 These laters are on-chip communications between processors and coprocessors,82 and external communications between the FPGA and the host PC.73 \item[Hardware/Software communication middleware] 74 Coach will implement an homogeneous HW/SW communication infrastructure and 75 communication APIs (Application Programming Interface), that will be used for 76 communications between software tasks running on embedded processors and 77 dedicated hardware coprocessors, 83 78 \end{description} 84 79 The COACH design flow will be dedicated to system designers, and will as … … 99 94 MPSoC architectures (\tima, \ubs, \upmc), 100 95 ASIP architectures (\irisa), 101 High Level Synthesis (\tima, \ubs, \upmc) and compilation (\lip).96 High Level Synthesis (\tima, \ubs, \upmc), and compilation (\lip). 102 97 \\ 103 %The CoACH proposal can be described as an extension of the SoCLib virtual104 %prototyping platform to the FPGA technologies.105 98 The COACH project does not start from scratch. 106 99 It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping, … … 115 108 \par 116 109 The COACH proposal has been prepared during one year by a technical working group 117 involving all the academic partners (one monthly meeting from january 2009 to february 118 2010). The objective of these meetings was to analyse the issues of integrating 119 and enhancing the formers tools and tecnnologies into a unique framework allowing to both 120 virtual prototyping and hardware generation. 110 involving the 5 academic partners (one monthly meeting from january 2009 to february 111 2010). The objective was to analyse the issues of integrating 112 and enhancing the existing tools and tecnnologies into a unique framework. 113 Most of the general software architecture of the proposed design flow (including the 114 exchange format specification) has been define by this working group. 121 115 Because the SocLib platform is the base of this project, it may be described as an 122 116 extension of the SoCLib platform. 117 118 %The main development steps of the COACH project are: 119 %\begin{enumerate} 120 % \item Definition of the end user inputs: 121 % The coarse grain parallelism of the application will be described as a communicating 122 % task graph, each task being described in C language. 123 % Similarly the architectural templates with their parameters and the design constraints 124 % will be specified. 125 % \item Definition of an internal format for representing task. 126 % \item Development of the GCC pluggin for generating the internal format of a 127 % C task. 128 % \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write 129 % the internal format. This will allow to swap from one tool to another one, and to 130 % chain them if necessary. 131 % \item Modification of the DSX tool (Design Space eXplorer) of the SocLib 132 % platform to generate the bitstream for the various FPGA families and architectural 133 % templates. 134 % \item Development of new tools such as ASIP compiler, HPC design environment and 135 % dynamic reconfiguration of FPGA devices. 136 %\end{enumerate} 137 123 138 \par 124 The main development steps of the COACH project are: 125 \begin{enumerate} 126 \item Definition of the end user inputs: 127 The coarse grain parallelism of the application will be described as a communicating 128 task graph, each task being described in C language. 129 Similarly the architectural templates with their parameters and the design constraints 130 will be specified. 131 \item Definition of an internal format for representing task. 132 \item Development of the GCC pluggin for generating the internal format of a 133 C task. 134 \item Adaptation of the existing HAS tools (BEE, SYNTOL, UGH, GAUT) to read and write 135 the internal format. This will allow to swap from one tool to another one, and to 136 chain them if necessary. 137 \item Modification of the DSX tool (Design Space eXplorer) of the SocLib 138 platform to generate the bitstream for the various FPGA families and architectural 139 templates. 140 \item Development of new tools such as ASIP compiler, HPC design environment and 141 dynamic reconfiguration of FPGA devices. 142 \end{enumerate} 143 \par 144 The two major FPGA companies \altera and \xilinx are participating in this 145 project to support the partners providing the software technologies, and to 146 help to generate efficient bitsream for both FPGA families. 139 Two major FPGA companies are involved in the project : \xilinx will contribute 140 as a contractual partner providing documentation and manpower; \altera will contribute as a supporter, 141 providing documentation and development boards (\altera). These two companies are strongly motivated 142 to help the COACH project to generate efficient bitsream for both FPGA families. 147 143 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide 148 144 real use cases to benchmark the COACH design environment. … … 152 148 The architectural templates, and the COACH software tools will be distributed under the 153 149 GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib 154 IP core library) will be freely available for non commercial use. Commercial licences 155 will be negociated for industrial exploitation. 150 IP core library) will be freely available for non commercial use. For industrial exploitation 151 the technology providers are ready to propose commercial licenses, directly to the end user, 152 or through a third party. 156 153
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