Changeset 99 for anr/section-1.tex

Timestamp:

Feb 8, 2010, 12:11:05 AM (15 years ago)

Author:

coach

Message:

IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

File:

• anr/section-1.tex (modified) (8 diffs)

anr/section-1.tex

@@ -4 +4 @@
 integration of heterogeneous technologies and requires the design of
 complex Multi-Processors System on Chip (MPSoC).
-\par
+\\
 During the last decade, the design of ASICs (Application Specific
 Integrated Circuits) appeared to be more and more reserved to high volume markets, because
@@ -20 +20 @@
 major companies to design innovative devices and to enter new, low and
 medium volume markets.
-\par
+\parlf
 The objective of COACH is to provide an integrated design flow, based on the
 SoCLib infrastructure~\cite{soclib}, and optimized for the design of
@@ -31 +31 @@
 They can also be extension boards connected to a PC to accelerate a specific computation,
 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
-\par
+\parlf
 %verrous scientifiques et techniques
-\vspace*{.9ex}\par
 The COACH environment will integrate several hardware and software technologies:
 \begin{description}
@@ -66 +65 @@
     \item An \altera architectural template based on the \altera IP core library and the
       AVALON system bus.
-    \item A \xilinx architectural template based on the Xlinx IP core library and the OPB
+    \item A \xilinx architectural template based on the Xlinx IP core library and the PLB
       system bus.
     \end{enumerate}
@@ -82 +81 @@
 %independant from both the architectural template and from the selected FPGA
 %family.
-
+\parlf
 % le programme de travail
-\vspace*{.9ex}\par
 %The COACH project targets fundamental issues related to design methodologies for 
 %digital systems by providing estimation, exploration and design tools targeting both 
@@ -106 +104 @@
 Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
 bitstreams.
-\par
+\parlf
 The COACH proposal has been prepared during one year by a technical working group
 involving the 5 academic partners (one monthly meeting from january 2009 to february
@@ -115 +113 @@
 Because the SocLib platform is the base of this project, it may be described as an
 extension of the SoCLib platform.
-
 %The main development steps of the COACH project are: 
 %\begin{enumerate}
@@ -135 +132 @@
 %    dynamic reconfiguration of FPGA devices.
 %\end{enumerate}
-
-\par
+\parlf
 Two major FPGA companies are involved in the project : \xilinx will contribute
 as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
-providing documentation and development boards (\altera). These two companies are strongly motivated
+providing documentation and development boards. These two companies are strongly motivated
 to help the COACH project to generate efficient bitsream for both FPGA families.
 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
 real use cases to benchmark the COACH design environment.
-\par
+\parlf
 Following the general policy of the SoCLib platform, the COACH project will be an open
 infrastructure, available in the framework of the SoCLib server.