Changeset 99 for anr/section-2.2.tex


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Timestamp:
Feb 8, 2010, 12:11:05 AM (14 years ago)
Author:
coach
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IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

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  • anr/section-2.2.tex

    r97 r99  
    99This project proposes an open-source framework for mapping multi-tasks software applications
    1010on Field Programmable Gate Array circuits (FPGA).
    11 
    12 \par
     11%%%
     12\parlf
    1313COACH will contribute to build an open development and run-time
    1414environment, including communication middleware and tools to support
    1515developers in the production of embedded software, through all phases of the software lifecycle,
    1616from requirements analysis until deployment and maintenance.
    17 
    1817More specifically, COACH focuses on:
    1918\begin{itemize}
    … …  
    2625environment, suitable for co-operative and distributed development.
    2726\end{itemize}
    28 
     27%%%
     28\parlf
    2929COACH outcome will contribute to strengthen Europe's competitive position by developing
    3030technologies and methodologies for product development, focusing (in compliance with the
    … …  
    3333in COACH will enable new and emerging information technologies for the development,
    3434manufacturing and integration of devices and related software into end-products.
    35 
    36 \par
     35%%%
     36\parlf
    3737The COACH project will benefit from a number of previous projects:
    38 \begin{itemize}
    39 \item SOCLIB :
    40 The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
    41 and 6 industrial companies.
    42 It supports system level virtual prototyping of shared memory, multi-processors
    43 architectures, and provides tools to map multi-tasks software application on these
    44 architectures, for reliable performance evaluation.
    45 The core  of this platform is a library of SystemC simulation models for
    46 general purpose IP cores such as processors, buses, networks, memories, IO controller.
    47 The platform provides also embedded operating systems and software/hardware
    48 communication middleware.
    49 The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    50 this project enhances SoCLib by providing the synthesisable VHDL models required
    51 for FPGA synthesis.
    52 \item ROMA :
    53 The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
    54 reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
    55 computing structure to computation patterns that can be speed-up and/or power efficient.
    56 The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
    57 operators to avoid traditional overhead, in reconfigurable devices, related to
    58 the interconnection network.
    59 The project will  borrow from the ROMA ANR xxproject (2007-2009) and the ongoing
    60 joint INRIA-STMicro Nano2012 project to adapt existing pattern
    61 extraction algorithms and datapath merging techniques to the synthesis of customized
    62 ASIP processors.
    63 \item TSAR :
    64 The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the LIP6 targets the design of a
    65 scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
    66 plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
    67 models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
    68 \item BioWic
    69 On the HPC application side, we also hope to benefit from the experience in
    70 hardware acceleration of bioinformatic algorithms/workfows gathered by the
    71 CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
    72 be able to validate the framework on real-life HPC applications.
    73 \end{itemize}
    74 
    75 
    76 \par
     38\begin{description}
     39  \item[SOCLIB]
     40    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories
     41    and 6 industrial companies.
     42    It supports system level virtual prototyping of shared memory, multi-processors
     43    architectures, and provides tools to map multi-tasks software application on these
     44    architectures, for reliable performance evaluation.
     45    The core of this platform is a library of SystemC simulation models for
     46    general purpose IP cores such as processors, buses, networks, memories, IO controller.
     47    The platform provides also embedded operating systems and software/hardware
     48    communication middleware.
     49    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
     50    this project enhances SoCLib by providing the synthesisable VHDL models required
     51    for FPGA synthesis.
     52  \item[ROMA]
     53    The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
     54    reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
     55    computing structure to computation patterns that can be speed-up and/or power efficient.
     56    The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
     57    operators to avoid traditional overhead, in reconfigurable devices, related to
     58    the interconnection network.
     59    The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing
     60    joint INRIA-STMicro Nano2012 project to adapt existing pattern
     61    extraction algorithms and datapath merging techniques to the synthesis of customized
     62    ASIP processors.
     63  \item[TSAR]
     64    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a
     65    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
     66    plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL
     67    models developped in the framework of TSAR (MIPS32 processor core, and RING interconnect).
     68  \item[BioWic]
     69    On the HPC application side, we also hope to benefit from the experience in
     70    hardware acceleration of bioinformatic algorithms/workfows gathered by the
     71    CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
     72    be able to validate the framework on real-life HPC applications.
     73\end{description}
     74%%%
     75\parlf
    7776The laboratories involved in the COACH project have a well estabished expertise
    7877in the following domains:
    7978\begin{itemize}
    80 \item
    81 In the field of High Level Synthesis (HLS), the project
    82 leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
    83 developped by the Lab-STIC laboratory, and with the UGH~\cite{ugh08} project developped
    84 by the LIP6 and TIMA laboratories.
     79  \item
     80    In the field of High Level Synthesis (HLS), the project
     81    leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project
     82    developped by the \ubs laboratory, and with the UGH~\cite{ugh08} project developped
     83    by the \upmc and \tima laboratories.
     84  \item
     85    Regarding system level architecture, the project is based on the know-how
     86    acquired by the \upmc and \tima laboratories in the framework of various projects 
     87    (COSY~\cite{disydent}, or MEDEA-MESA~\cite{dspin}), in the field of communication
     88    architectures for shared memory multi-processors systems.
     89    As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
     90  \item
     91    Regarding Application Specific Instruction Processor (ASIP) design, the
     92    CAIRN group at INRIA Bretagne Atlantique benefits from several years of
     93    expertise in the domain of retargetable compiler
     94    (Armor/Calife~\cite{CODES99} since 1996, and the Gecos
     95    compilers~\cite{ASAP05} since 2002).
    8596\item
    86 Regarding system level architecture, the project is based on the know-how
    87 acquired by the LIP6 and TIMA laboratories in the framework of various projects 
    88 (COSY \cite{disydent}, or MEDEA MESA \cite{dspin}), in the field of communication
    89 architectures for shared memory multi-processors systems.
    90 As an example, the DSPIN network on chip, is now used by BULL in the TSAR project.
    91 \item
    92 Regarding Application Specific Instruction Processor (ASIP) design, the
    93 CAIRN group at INRIA Bretagne Atlantique benefits from several years of
    94 expertise in the domain of retargetable compiler
    95 (Armor/Calife\cite{CODES99} since 1996, and the Gecos
    96 compilers\cite{ASAP05} since 2002).
    97 \item
    98 In the field of compilers, the Compsys group was founded in 2002
    99 by several senior researchers with experience in
    100 high performance computing and automatic parallelization. They have been
    101 among the initiators of the polyhedral model, a theory which serve to
    102 unify many parallelism detection and exploitation techniques for regular
    103 programs. It is expected that the techniques developped by Compsys for
    104 parallelism detection, scheduling, process construction and memory management
    105 will be very useful as a Rfront end for the a high-level synthesis tools.
     97    In the field of compilers, the Compsys group was founded in 2002
     98    by several senior researchers with experience in
     99    high performance computing and automatic parallelization. They have been
     100    among the initiators of the polyhedral model, a theory which serve to
     101    unify many parallelism detection and exploitation techniques for regular
     102    programs. It is expected that the techniques developped by Compsys for
     103    parallelism detection, scheduling, process construction and memory management
     104    will be very useful as a front-end for the a high-level synthesis tools.
    106105\end{itemize}
    107 
    108 
    109 \par
    110 % FIXME A VERIFIER L'appel d'offre
     106%%%
     107\parlf
    111108Finally, it is worth to note that this project cover priorities defined by the commission
    112109experts in the field of Information Technolgies Society (IST) for Embedded
    … …  
    115112considering resources constraints (delais, power, memory, etc.), security and quality
    116113services$>>$.
    117 
    118 
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