Changes between Version 18 and Version 19 of SoclibComponents

Timestamp:

Mar 4, 2008, 7:49:31 PM (17 years ago)

Author:

Nicolas Pouillon

Comment:

API update

SoclibComponents

@@ -6 +6 @@
 
  * functionality : a generic VCI compliant micro-network
- * Mandatory arguments:
+ * Arguments:
    * `instance name`
- * Optional arguments:
    * `min_latency` (one-way)
+   * `fifo_size`
  * Example:
 {{{
-my_vgmn = Vgmn("my_vgmn", 10)
+my_vgmn = arch.create('caba:vci_vgmn', "my_vgmn", min_latency = 10, fifo_size = 8)
 }}}
  * Defined ports:
-   * `getBoth()`, `getInit()` and `getTarget()`: local ports, allocated on demand
+   * `to_initiator.new()` and `to_target.new()`: local ports, allocated on demand
 
 == A.2) !LocalCrossbar ==
 
  * functionality : a VCI compliant crossbar interconnect
- * Mandatory arguments:
+ * Arguments:
    * `instance name`
  * Example:
 {{{
-my_lc = LocalCrossbar("lc0")
+my_lc = arch.create('caba:vci_local_crossbar', "lc0")
 }}}
  * Defined ports:
-   * `getBoth()`, `getInit()` and `getTarget()`: local ports, allocated on demand
-   * `upstream`, bidirectional port to upper-level interconnect
+   * `to_initiator.new()` and `to_target.new()`: local ports, allocated on demand
 
 = B) VCI Initiators =
@@ -35 +34 @@
 
  * functionality: a direct mapping cache controler (separated instruction & data cache)
- * Mandatory arguments:
+ * Arguments:
    * `instance name`
- * Optional arguments:
    * `dcache_lines` : number of lines in data cache
    * `dcache_words` : number of words per line in data cache
@@ -44 +42 @@
  * Example:
 {{{
-my_cache = Xcache( "my_cache",
+my_cache = arch.create('caba:vci_vgmn', "my_cache",
                    dcache_lines = 32,
                    dcache_words = 8,
@@ -51 +49 @@
 }}}
  * Defined ports:
-   * `cache`: to the CPU 
+   * `dcache`: to the CPU 
+   * `icache`: to the CPU 
    * `vci`: to the VCI micro-network
 
@@ -58 +57 @@
 == C.1) Mips ==
 
+This component is special as it is in fact a wrapped ISS.
+
  * Functionality : a MIPS R3000 micro-processor
- * Mandatory arguments:
+ * Arguments:
     * `name`
+    * `ident`: cpu id
  * Example:
 {{{
-my_proc = Mips("my_proc")
+my_proc = arch.create('caba:iss_wrapper', "my_proc", iss_t = 'common:mipsel', ident = 0 )
 }}}
  * Defined ports:
-   * `cache`: to the cache's cache port
+   * `dcache`: to the cache's dcache port
+   * `icache`: to the cache's icache port
    * `irq[n]`: interrupt line (0 <= n < 6)
 
@@ -75 +78 @@
  * !Mandatory arguments:
    * `name`
- * Optional arguments:
-   * a list of segments, allocated with Segment()
  * Example:
 {{{
-my_ram = MultiRam("my_ram", seg1, seg2, seg3)
+my_ram = arch.create('caba:vci_ram', "my_ram")
 }}}
  * Defined ports:
    * `vci`: to the micro-network
+ * Adding a segment:
+   * Arguments: name, base address, size, cacheability
+{{{
+my_ram.addSegment( 'boot', 0xbfc00000, 0x100, true )
+}}}
 
 == D.2) !MultiTty ==
 
- * functionality: a TTY controler (up to  256 TTYs)
+ * functionality: a TTY controler
  * Mandatory arguments:
    * `instance name`
-   * an ordered  list ot names (one name per emulated terminal) 
+   * a list of names 
  * Example:
 {{{
-my_tty = MultiTty("my_tty_controler", "TTY0", "TTY1", "TT2")
+my_tty = arch.create('caba:vci_multi_tty', "my_tty_controler", ["TTY0", "TTY1", "TT2"])
 }}}
  * Defined ports:
    * `vci`: to the micro-network
    * `irq[n]`: interrupt line (0 <= n < nb of ttys)
-
-== D.3) Locks ==
-
- * functionality : a locks controler
- * Mandatory arguments:
-   * `instance name`
- * Example:
-{{{
-my_locks = Locks("my_locks_controler")
-}}}
- * Defined ports:
-   * `vci`: to the micro-network