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source: soft/giet_vm/giet_python/mapping.py @ 404

Last change on this file since 404 was 404, checked in by cfuguet, 10 years ago

mapping.py: when ramdisk is used, other ioc controller are disabled

All USE_IOC_* = 0 but the USE_IOC_RDK when ramdisk is used

Property svn:executable set to *

File size: 102.4 KB

Rev	Line
[305]	1	#!/usr/bin/env python
	2
[319]	3	import sys
	4
	5	##########################################################################################
[305]	6	# file : giet_mapping.py
	7	# date : april 2014
	8	# author : Alain Greiner
[319]	9	##########################################################################################
	10	# This file contains the classes required to define a mapping for the GIET_VM.
	11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
	12	# a set of 'Vseg' (kernel virtual segments mapping)
	13	# a set of 'Vspace' (several user applications).
	14	# - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster)
	15	# a set of 'Proc' (processors in cluster)
	16	# a set of 'Periph' (peripherals in cluster)
	17	# a set of 'Coproc' (coprocessors in cluster)
	18	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping)
	19	# a set of 'Task' (user tasks mapping)
	20	# - A 'Vseg' contains a set of 'Vobj'
	21	# - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types )
	22	# - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel)
	23	##########################################################################################
	24	# Implementation Note
	25	# As described above, the various objects are distributed in the PYTHON structure:
	26	# For example the psegs set is split in several subsets (one subset per cluster),
	27	# or the tasks set is split in several subsets (one subset per vspace), etc...
	28	# In the C binary data structure used by the giet_vm, all objects of same type
	29	# are stored in a linear array (one single array for all psegs for example).
	30	# For all objects, we compute and store in the PYTHON object itsel a "global index"
	31	# corresponding to the index in this global array, and this index can be used as
	32	# a pseudo-pointer to identify a specific object of a given type.
	33	##########################################################################################
[305]	34
[319]	35	######################################################################################
	36	# These global lists must be consistent with enums in mapping_info.h or irq_handler.h
	37	######################################################################################
	38	PERIPHTYPES = [
	39	'CMA',
	40	'DMA',
	41	'FBF',
	42	'ICU',
	43	'IOB',
	44	'IOC',
	45	'MMC',
	46	'MWR',
	47	'NIC',
	48	'ROM',
	49	'SIM',
	50	'TIM',
	51	'TTY',
	52	'XCU',
	53	'PIC',
	54	]
	55
	56	PERIPHSUBTYPES = [
	57	'BDV',
	58	'HBA',
	59	'SPI',
	60	'NONE',
	61	]
	62
	63	IRQTYPES = [
	64	'HWI',
	65	'WTI',
	66	'PTI',
	67	]
	68
	69	ISRTYPES = [
	70	'ISR_DEFAULT',
	71	'ISR_TICK',
	72	'ISR_TTY_RX',
	73	'ISR_TTY_TX',
	74	'ISR_BDV',
	75	'ISR_TIMER',
	76	'ISR_WAKUP',
	77	'ISR_NIC_RX',
	78	'ISR_NIC_TX',
	79	'ISR_CMA',
	80	'ISR_MMC',
	81	'ISR_DMA',
	82	'ISR_SPI',
	83	]
	84
	85	VOBJTYPES = [
	86	'ELF',
	87	'BLOB',
	88	'PTAB',
	89	'PERI',
	90	'MWMR',
	91	'LOCK',
	92	'BUFFER',
	93	'BARRIER',
	94	'CONST',
	95	'MEMSPACE',
	96	'SCHED',
	97	]
	98
	99	VSEGMODES = [
	100	'____',
	101	'___U',
	102	'__W_',
	103	'__WU',
	104	'_X__',
	105	'_X_U',
	106	'_XW_',
	107	'_XWU',
	108	'C___',
	109	'C__U',
	110	'C_W_',
	111	'C_WU',
	112	'CX__',
	113	'CX_U',
	114	'CXW_',
	115	'CXWU',
	116	]
	117
	118	PSEGTYPES = [
	119	'RAM',
	120	'ROM', # deprecated => use PERI
	121	'PERI',
	122	]
	123
	124	CP_PORT_DIRS = [
	125	'TO_COPROC',
	126	'FROM_COPROC',
	127	]
	128
	129	##########################################################################################
[305]	130	class Mapping( object ):
[319]	131	##########################################################################################
[305]	132	def __init__( self,
[319]	133	name, # mapping name
	134	x_size, # number of clusters in a row
	135	y_size, # number of clusters in a column
	136	procs_max, # max number of processors per cluster
	137	x_width = 4, # number of bits encoding x coordinate
	138	y_width = 4, # number of bits encoding y coordinate
	139	paddr_width = 40, # number of bits for physical address
	140	coherence = 1, # hardware cache coherence when non-zero
	141	irq_per_proc = 1, # number or IRQs from XCU to processor
	142	use_ramdisk = False, # use ramdisk when true
	143	x_io = 0, # cluster_io x coordinate
	144	y_io = 0, # cluster_io y coordinate
[328]	145	peri_increment = 0x10000, # address increment for globals
[356]	146	reset_address = 0xBFC00000, # Processor wired boot_address
	147	ram_base = 0, # RAM physical base address in cluster[0,0]
	148	ram_size = 0 ): # RAM size in each cluster (bytes)
[305]	149
[319]	150	self.signature = 0xDACE2014
	151	self.name = name
	152	self.paddr_width = paddr_width
	153	self.coherence = coherence
	154	self.x_size = x_size
	155	self.y_size = y_size
	156	self.x_width = x_width
	157	self.y_width = y_width
	158	self.irq_per_proc = irq_per_proc
	159	self.procs_max = procs_max
	160	self.use_ramdisk = use_ramdisk
	161	self.x_io = x_io
	162	self.y_io = y_io
[328]	163	self.peri_increment = peri_increment
[319]	164	self.reset_address = reset_address
[356]	165	self.ram_base = ram_base
	166	self.ram_size = ram_size
[305]	167
[356]	168
[319]	169	self.total_vspaces = 0
	170	self.total_globals = 0
	171	self.total_psegs = 0
	172	self.total_vsegs = 0
	173	self.total_vobjs = 0
	174	self.total_tasks = 0
	175	self.total_procs = 0
	176	self.total_irqs = 0
	177	self.total_coprocs = 0
	178	self.total_cpports = 0
	179	self.total_periphs = 0
[305]	180
[319]	181	self.clusters = []
	182	self.globs = []
	183	self.vspaces = []
[305]	184
[319]	185	for x in xrange( self.x_size ):
	186	for y in xrange( self.y_size ):
	187	cluster = Cluster( x , y )
	188	cluster.index = (x * self.y_size) + y
	189	self.clusters.append( cluster )
[305]	190
	191	return
	192
[319]	193	########################## add a ram pseg in a cluster
	194	def addRam( self,
	195	name, # pseg name
	196	base, # pseg base address
	197	size ): # pseg length (bytes)
	198
	199	# check coordinates (obtained from the base address)
[356]	200	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
	201	cluster_xy = base >> paddr_lsb_width
[305]	202	x = cluster_xy >> (self.y_width);
	203	y = cluster_xy & ((1 << self.y_width) - 1)
	204
[319]	205	assert (base & 0xFFF) == 0
	206
	207	assert (x < self.x_size) and (y < self.y_size)
	208
[356]	209	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
	210
	211	assert ( size == self.ram_size )
	212
[319]	213	cluster_id = (x * self.y_size) + y
	214
	215	# add one pseg in the mapping
	216	pseg = Pseg( name, base, size, x, y, 'RAM' )
	217	self.clusters[cluster_id].psegs.append( pseg )
	218	pseg.index = self.total_psegs
	219	self.total_psegs += 1
	220
	221	return pseg
	222
	223	############################## add a peripheral and the associated pseg in a cluster
	224	def addPeriph( self,
	225	name, # associated pseg name
	226	base, # associated pseg base address
	227	size, # associated pseg length (bytes)
	228	ptype, # peripheral type
	229	subtype = 'NONE', # peripheral subtype
	230	channels = 1, # number of channels
	231	arg = 0 ): # optional argument (semantic depends on ptype)
	232
	233	# check cluster coordinates (obtained from the base address)
	234	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
[305]	235	x = cluster_xy >> (self.y_width);
	236	y = cluster_xy & ((1 << self.y_width) - 1)
	237
[319]	238	assert (x < self.x_size) and (y < self.y_size)
	239
	240	assert (base & 0xFFF) == 0
	241
	242	assert ptype in PERIPHTYPES
	243
	244	assert subtype in PERIPHSUBTYPES
	245
	246	cluster_id = (x * self.y_size) + y
	247
	248	# add one pseg into mapping
	249	pseg = Pseg( name, base, size, x, y, 'PERI' )
	250	self.clusters[cluster_id].psegs.append( pseg )
	251	pseg.index = self.total_psegs
	252	self.total_psegs += 1
	253
	254	# add one periph into mapping
	255	periph = Periph( pseg, ptype, subtype, channels, arg )
	256	self.clusters[cluster_id].periphs.append( periph )
	257	periph.index = self.total_periphs
	258	self.total_periphs += 1
	259
	260	return periph
	261
	262	################################ add an IRQ in a peripheral
	263	def addIrq( self,
	264	periph, # peripheral containing IRQ (PIC or XCU)
	265	index, # peripheral input port index
	266	isrtype, # ISR type
	267	channel = 0 ): # channel for multi-channels ISR
	268
	269	assert isrtype in ISRTYPES
	270
	271	assert index < 32
	272
	273	# add one irq into mapping
	274	irq = Irq( 'HWI', index , isrtype, channel )
	275	periph.irqs.append( irq )
	276	irq.index = self.total_irqs
	277	self.total_irqs += 1
	278
	279	return irq
	280
	281	########################## add a processor in a cluster
	282	def addProc( self,
	283	x, # cluster x coordinate
	284	y, # cluster y coordinate
	285	p ): # processor local index
	286
	287	assert (x < self.x_size) and (y < self.y_size)
	288
	289	cluster_id = (x * self.y_size) + y
	290
	291	# add one proc into mapping
	292	proc = Processor( x, y, p )
	293	self.clusters[cluster_id].procs.append( proc )
	294	proc.index = self.total_procs
[305]	295	self.total_procs += 1
	296
[319]	297	return proc
	298
	299	############################## add a coprocessor in a cluster
	300	def addCoproc( self,
	301	name, # associated pseg name
	302	base, # associated pseg base address
	303	size ): # associated pseg length
	304
	305	# check cluster coordinates (obtained from the base address)
	306	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
	307	x = cluster_xy >> (self.y_width);
	308	y = cluster_xy & ((1 << self.y_width) - 1)
	309
	310	assert (x < self.x_size) and (y < self.y_size)
	311
	312	cluster_id = (x * self.y_size) + y
	313
	314	# add one pseg into mapping
	315	pseg = Pseg( name, base, size, x, y, 'PERI' )
	316	self.clusters[cluster_id].psegs.append( pseg )
	317	pseg.index = self.total_psegs
	318	self.total_psegs += 1
	319
	320	# add one coproc into mapping
	321	periph = Coproc( pseg )
	322	self.clusters[cluster_id].coprocs.append( coproc )
	323	periph.index = self.total_coprocs
	324	self.total_coprocs += 1
	325
	326	return coproc
	327
	328	################################## add a port in a coprocessor
	329	def addPort( self,
	330	coproc, # coprocessor containing the port
	331	direction, # direction (TO_COPROC / FROM_COPROC)
	332	vspacename, # name of vspace using the coproc
	333	mwmrname ): # name of the vobj defining the MWMR channel
	334
	335	assert direction in CP_PORT_DIRS
	336
	337	# add one cpport into mapping
	338	port = Cpport( direction, vspacename, mwmrname )
	339	coproc.ports.append( port )
	340	port.index = self.total_cpports
	341	self.total_cpports += 1
	342
	343	return port
	344
	345	############################ add one (or several) global vseg into mapping
	346	def addGlobal( self,
[348]	347	name, # vseg name
	348	vbase, # virtual base address
	349	size, # vobj length (bytes)
	350	mode, # CXWU flags
	351	vtype, # vobj type
	352	x, # destination x coordinate
	353	y, # destination y coordinate
	354	pseg, # destination pseg name
	355	identity = False, # identity mapping required if true
	356	binpath = '', # pathname for binary code
	357	local = False ): # non shared vseg when true
[319]	358
	359	assert mode in VSEGMODES
	360
	361	assert vtype in VOBJTYPES
	362
	363	assert (vbase & 0xFFF) == 0
	364
	365	assert (x < self.x_size) and (y < self.y_size)
	366
[328]	367	# add one vseg into mapping
[348]	368	vseg = Vseg( name, vbase, mode, x, y, pseg,
	369	identity = identity, local = local )
	370
[328]	371	self.globs.append( vseg )
	372	self.total_globals += 1
	373	vseg.index = self.total_vsegs
	374	self.total_vsegs += 1
[319]	375
[328]	376	# add one vobj into mapping
	377	vobj = Vobj( name, size, vtype, binpath, 0, 0 )
	378	vseg.vobjs.append( vobj )
	379	vobj.index = self.total_vobjs
	380	self.total_vobjs += 1
[319]	381
[305]	382	return
	383
[319]	384	################################ add a vspace into mapping
	385	def addVspace( self,
	386	name, # vspace name
	387	startname ): # name of vobj containing start_vector
	388
	389	# add one vspace into mapping
	390	vspace = Vspace( name, startname )
[305]	391	self.vspaces.append( vspace )
[319]	392	vspace.index = self.total_vspaces
	393	self.total_vspaces += 1
	394
	395	return vspace
[305]	396
[319]	397	################################# add a private vseg and a vobj in a vspace
	398	def addVseg( self,
	399	vspace, # vspace containing the vseg
	400	name, # vseg name
	401	vbase, # virtual base address
	402	size, # vobj length (bytes)
	403	mode, # CXWU flags
	404	vtype, # vobj type
	405	x, # destination x coordinate
	406	y, # destination y coordinate
	407	pseg, # destination pseg name
[348]	408	binpath = '', # pathname for binary code
	409	align = 0, # alignment required
	410	init = 0, # initial value
	411	local = False ): # non shared when true
[319]	412
	413	assert mode in VSEGMODES
	414
	415	assert vtype in VOBJTYPES
	416
	417	assert (x < self.x_size) and (y < self.y_size)
	418
	419	# add one vseg into mapping
[348]	420	vseg = Vseg( name, vbase, mode, x, y, pseg, local = local )
[319]	421	vspace.vsegs.append( vseg )
	422	vseg.index = self.total_vsegs
	423	self.total_vsegs += 1
	424
	425	# add one vobj into mapping
	426	vobj = Vobj( name, size, vtype, binpath, align, init )
	427	vseg.vobjs.append( vobj )
	428	vobj.index = self.total_vobjs
	429	self.total_vobjs += 1
	430
	431	return vseg
	432
	433	################################ add a vobj in a private vseg
	434	def addVobj( self,
	435	vseg, # vseg containing vobj
	436	name, # vobj name
	437	size, # vobj length (bytes)
	438	vtype, # vobj type
	439	binpath = '', # pathname to binary
	440	align = 0, # alignment constraint
	441	init = 0 ): # initial value
	442
	443	assert vtype in VOBJTYPES
	444
	445	# add one vobj into mapping
	446	vobj = Vobj( name, size, vtype, binpath, align, init )
	447	vseg.vobjs.append( vobj )
	448	vobj.index = self.total_vobjs
	449	self.total_vobjs += 1
	450
	451	return vobj
	452
	453	################################ add a task in a vspace
	454	def addTask( self,
	455	vspace, # vspace containing task
	456	name, # task name
	457	trdid, # task index in vspace
	458	x, # destination x coordinate
	459	y, # destination y coordinate
	460	lpid, # destination processor local index
	461	stackname, # name of vobj containing stack
	462	heapname, # name of vobj containing heap
	463	startid, # index in start_vector
	464	usetty = False, # request a private TTY channel
	465	usenic = False, # request a private NIC channel
	466	usecma = False, # request a private CMA channel
	467	usehba = False, # request a private HBA channel
	468	usetim = False ): # request a private TIM channel
	469
	470	assert (x < self.x_size) and (y < self.y_size)
	471
	472	assert lpid < self.procs_max
	473
	474	# add one task into mapping
	475	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid,
	476	usetty, usenic, usecma, usehba, usetim )
	477	vspace.tasks.append( task )
	478	task.index = self.total_tasks
	479	self.total_tasks += 1
	480
	481	return task
	482
	483	#################################
	484	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
	485
	486	byte_stream = bytearray()
	487	length = len( s )
	488	if length < (nbytes - 1):
	489	for b in s:
	490	byte_stream.append( b )
	491	for x in xrange(nbytes-length):
	492	byte_stream.append( '\0' )
	493	else:
[348]	494	print '[genmap error] in str2bytes() : string %s too long' % s
[319]	495	sys.exit(1)
	496
	497	return byte_stream
	498
	499	###################################
	500	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
	501
	502	byte_stream = bytearray()
	503	for n in xrange( nbytes ):
	504	byte_stream.append( (val >> (n<<3)) & 0xFF )
	505
	506	return byte_stream
	507
	508	################
	509	def xml( self ): # xml file generation for mapping
	510
[305]	511	s = '<?xml version="1.0"?>\n\n'
[319]	512	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
[305]	513	s += ' name = "%s"\n' % (self.name)
	514	s += ' x_size = "%d"\n' % (self.x_size)
	515	s += ' y_size = "%d"\n' % (self.y_size)
	516	s += ' x_width = "%d"\n' % (self.x_width)
	517	s += ' y_width = "%d"\n' % (self.y_width)
	518	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
[319]	519	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
[305]	520	s += ' x_io = "%d"\n' % (self.x_io)
	521	s += ' y_io = "%d" >\n' % (self.y_io)
[319]	522	s += '\n'
	523
[305]	524	s += ' <clusterset>\n'
	525	for x in xrange ( self.x_size ):
	526	for y in xrange ( self.y_size ):
[319]	527	cluster_id = (x * self.y_size) + y
	528	s += self.clusters[cluster_id].xml()
[305]	529	s += ' </clusterset>\n'
[319]	530	s += '\n'
	531
[305]	532	s += ' <globalset>\n'
[319]	533	for vseg in self.globs: s += vseg.xml()
[305]	534	s += ' </globalset>\n'
[319]	535	s += '\n'
	536
[305]	537	s += ' <vspaceset>\n'
[319]	538	for vspace in self.vspaces: s += vspace.xml()
[305]	539	s += ' </vspaceset>\n'
[319]	540
[305]	541	s += '</mapping_info>\n'
	542	return s
[319]	543
	544	#########################
	545	def cbin( self, verbose ): # C binary structure generation for mapping
	546
	547	byte_stream = bytearray()
	548
	549	# header
	550	byte_stream += self.int2bytes(4, self.signature)
	551	byte_stream += self.int2bytes(4, self.x_size)
	552	byte_stream += self.int2bytes(4, self.y_size)
	553	byte_stream += self.int2bytes(4, self.x_width)
	554	byte_stream += self.int2bytes(4, self.y_width)
	555	byte_stream += self.int2bytes(4, self.x_io)
	556	byte_stream += self.int2bytes(4, self.y_io)
	557	byte_stream += self.int2bytes(4, self.irq_per_proc)
	558	byte_stream += self.int2bytes(4, self.use_ramdisk)
	559	byte_stream += self.int2bytes(4, self.total_globals)
	560	byte_stream += self.int2bytes(4, self.total_vspaces)
	561	byte_stream += self.int2bytes(4, self.total_psegs)
	562	byte_stream += self.int2bytes(4, self.total_vsegs)
	563	byte_stream += self.int2bytes(4, self.total_vobjs)
	564	byte_stream += self.int2bytes(4, self.total_tasks)
	565	byte_stream += self.int2bytes(4, self.total_procs)
	566	byte_stream += self.int2bytes(4, self.total_irqs)
	567	byte_stream += self.int2bytes(4, self.total_coprocs)
	568	byte_stream += self.int2bytes(4, self.total_cpports)
	569	byte_stream += self.int2bytes(4, self.total_periphs)
	570	byte_stream += self.str2bytes(32, self.name)
	571
	572	if ( verbose ):
	573	print '\n'
	574	print 'name = %s' % self.name
	575	print 'signature = %x' % self.signature
	576	print 'x_size = %d' % self.x_size
	577	print 'y_size = %d' % self.y_size
	578	print 'x_width = %d' % self.x_width
	579	print 'y_width = %d' % self.y_width
	580	print 'x_io = %d' % self.x_io
	581	print 'y_io = %d' % self.y_io
	582	print 'irq_per_proc = %d' % self.irq_per_proc
	583	print 'use_ramdisk = %d' % self.use_ramdisk
	584	print 'total_globals = %d' % self.total_globals
	585	print 'total_psegs = %d' % self.total_psegs
	586	print 'total_vsegs = %d' % self.total_vsegs
	587	print 'total_vobjs = %d' % self.total_vobjs
	588	print 'total_tasks = %d' % self.total_tasks
	589	print 'total_procs = %d' % self.total_procs
	590	print 'total_irqs = %d' % self.total_irqs
	591	print 'total_coprocs = %d' % self.total_coprocs
	592	print 'total_cpports = %d' % self.total_cpports
	593	print 'total_periphs = %d' % self.total_periphs
	594	print '\n'
	595
	596	# clusters array
	597	index = 0
	598	for cluster in self.clusters:
	599	byte_stream += cluster.cbin( self, verbose, index )
	600	index += 1
	601
	602	if ( verbose ): print '\n'
	603
	604	# psegs array
	605	index = 0
	606	for cluster in self.clusters:
	607	for pseg in cluster.psegs:
	608	byte_stream += pseg.cbin( self, verbose, index, cluster )
	609	index += 1
	610
	611	if ( verbose ): print '\n'
	612
	613	# vspaces array
	614	index = 0
	615	for vspace in self.vspaces:
	616	byte_stream += vspace.cbin( self, verbose, index )
	617	index += 1
	618
	619	if ( verbose ): print '\n'
	620
	621	# vsegs array
	622	index = 0
	623	for vseg in self.globs:
	624	byte_stream += vseg.cbin( self, verbose, index )
	625	index += 1
	626	for vspace in self.vspaces:
	627	for vseg in vspace.vsegs:
	628	byte_stream += vseg.cbin( self, verbose, index )
	629	index += 1
	630
	631	if ( verbose ): print '\n'
	632
	633	# vobjs array
	634	index = 0
	635	for vseg in self.globs:
	636	for vobj in vseg.vobjs:
	637	byte_stream += vobj.cbin( self, verbose, index )
	638	index += 1
	639	for vspace in self.vspaces:
	640	for vseg in vspace.vsegs:
	641	for vobj in vseg.vobjs:
	642	byte_stream += vobj.cbin( self, verbose, index )
	643	index += 1
	644
	645	if ( verbose ): print '\n'
	646
	647	# tasks array
	648	index = 0
	649	for vspace in self.vspaces:
	650	for task in vspace.tasks:
	651	byte_stream += task.cbin( self, verbose, index, vspace )
	652	index += 1
	653
	654	if ( verbose ): print '\n'
	655
	656	# procs array
	657	index = 0
	658	for cluster in self.clusters:
	659	for proc in cluster.procs:
	660	byte_stream += proc.cbin( self, verbose, index )
	661	index += 1
	662
	663	if ( verbose ): print '\n'
	664
	665	# irqs array
	666	index = 0
	667	for cluster in self.clusters:
	668	for periph in cluster.periphs:
	669	for irq in periph.irqs:
	670	byte_stream += irq.cbin( self, verbose, index )
	671	index += 1
	672
	673	if ( verbose ): print '\n'
	674
	675	# coprocs array
	676	index = 0
	677	for cluster in self.clusters:
	678	for coproc in cluster.coprocs:
	679	byte_stream += coproc.cbin( self, verbose, index )
	680	index += 1
	681
	682	if ( verbose ): print '\n'
	683
	684	# cpports array
	685	index = 0
	686	for cluster in self.clusters:
	687	for coproc in cluster.coprocs:
	688	for port in coproc.ports:
	689	byte_stream += port.cbin( self, verbose, index )
	690	index += 1
	691
	692	if ( verbose ): print '\n'
	693
	694	# periphs array
	695	index = 0
	696	for cluster in self.clusters:
	697	for periph in cluster.periphs:
	698	byte_stream += periph.cbin( self, verbose, index )
	699	index += 1
	700
	701	return byte_stream
	702	# end of cbin()
	703
	704	#######################
	705	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
	706	# required by giet_vm compilation
	707
	708	# search the vsegs required for the giet_vsegs.ld
	709	boot_code_found = False
	710	boot_data_found = False
	711	kernel_uncdata_found = False
	712	kernel_data_found = False
	713	kernel_code_found = False
	714	kernel_init_found = False
	715	for vseg in self.globs:
[348]	716
[319]	717	if ( vseg.name == 'seg_boot_code' ):
	718	boot_code_vbase = vseg.vbase
	719	boot_code_size = vseg.vobjs[0].length
	720	boot_code_found = True
	721
	722	if ( vseg.name == 'seg_boot_data' ):
	723	boot_data_vbase = vseg.vbase
	724	boot_data_size = vseg.vobjs[0].length
	725	boot_data_found = True
	726
	727	if ( vseg.name == 'seg_kernel_uncdata' ):
	728	kernel_uncdata_vbase = vseg.vbase
	729	kernel_uncdata_size = vseg.vobjs[0].length
	730	kernel_uncdata_found = True
	731
	732	if ( vseg.name == 'seg_kernel_data' ):
	733	kernel_data_vbase = vseg.vbase
	734	kernel_data_size = vseg.vobjs[0].length
	735	kernel_data_found = True
	736
	737	if ( vseg.name == 'seg_kernel_code' ):
	738	kernel_code_vbase = vseg.vbase
	739	kernel_code_size = vseg.vobjs[0].length
	740	kernel_code_found = True
	741
	742	if ( vseg.name == 'seg_kernel_init' ):
	743	kernel_init_vbase = vseg.vbase
	744	kernel_init_size = vseg.vobjs[0].length
	745	kernel_init_found = True
	746
	747	# check if all required vsegs have been found
	748	if ( boot_code_found == False ):
[348]	749	print '[genmap error] in giet_vsegs() : seg_boot_code vseg missing'
[319]	750	sys.exit()
	751
	752	if ( boot_data_found == False ):
[348]	753	print '[genmap error] in giet_vsegs() : seg_boot_data vseg missing'
[319]	754	sys.exit()
	755
	756	if ( kernel_data_found == False ):
[348]	757	print '[genmap error] in giet_vsegs() : seg_kernel_data vseg missing'
[319]	758	sys.exit()
	759
	760	if ( kernel_uncdata_found == False ):
[348]	761	print '[genmap error] in giet_vsegs() : seg_kernel_uncdata vseg missing'
[319]	762	sys.exit()
	763
	764	if ( kernel_code_found == False ):
[348]	765	print '[genmap error] in giet_vsegs() : seg_kernel_code vseg missing'
[319]	766	sys.exit()
	767
	768	if ( kernel_init_found == False ):
[348]	769	print '[genmap error] in giet_vsegs() : seg_kernel_init vseg missing'
[319]	770	sys.exit()
	771
	772	# build string
[327]	773	s = '/* Generated by genmap for %s */\n' % self.name
[319]	774	s += '\n'
	775
	776	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
	777	s += 'boot_code_size = 0x%x;\n' % boot_code_size
	778	s += '\n'
	779	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
	780	s += 'boot_data_size = 0x%x;\n' % boot_data_size
	781	s += '\n'
	782	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
	783	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
	784	s += '\n'
	785	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
	786	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
	787	s += '\n'
	788	s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase
	789	s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size
	790	s += '\n'
	791	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
	792	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
	793	s += '\n'
	794
	795	return s
	796
	797	########################
	798	def hard_config( self ): # compute string for hard_config.h file required by
	799	# - top.cpp compilation
	800	# - giet_vm compilation
	801	# - tsar_preloader compilation
	802
	803	nb_total_procs = 0
	804
	805	# for each peripheral type, define default values
	806	# for pbase address, size, number of components, and channels
	807	nb_cma = 0
	808	cma_channels = 0
	809	seg_cma_base = 0xFFFFFFFF
	810	seg_cma_size = 0
	811
	812	nb_dma = 0
	813	dma_channels = 0
	814	seg_dma_base = 0xFFFFFFFF
	815	seg_dma_size = 0
	816
	817	nb_fbf = 0
	818	fbf_channels = 0
[328]	819	fbf_arg = 0
[319]	820	seg_fbf_base = 0xFFFFFFFF
	821	seg_fbf_size = 0
	822
	823	nb_icu = 0
	824	icu_channels = 0
	825	seg_icu_base = 0xFFFFFFFF
	826	seg_icu_size = 0
	827
	828	nb_iob = 0
	829	iob_channels = 0
	830	seg_iob_base = 0xFFFFFFFF
	831	seg_iob_size = 0
	832
	833	nb_ioc = 0
	834	ioc_channels = 0
	835	seg_ioc_base = 0xFFFFFFFF
	836	seg_ioc_size = 0
	837
	838	nb_mmc = 0
	839	mmc_channels = 0
	840	seg_mmc_base = 0xFFFFFFFF
	841	seg_mmc_size = 0
	842
	843	nb_mwr = 0
	844	mwr_channels = 0
	845	seg_mwr_base = 0xFFFFFFFF
	846	seg_mwr_size = 0
	847
	848	nb_nic = 0
	849	nic_channels = 0
	850	seg_nic_base = 0xFFFFFFFF
	851	seg_nic_size = 0
	852
	853	nb_pic = 0
	854	pic_channels = 0
	855	seg_pic_base = 0xFFFFFFFF
	856	seg_pic_size = 0
	857
	858	nb_rom = 0
	859	rom_channels = 0
	860	seg_rom_base = 0xFFFFFFFF
	861	seg_rom_size = 0
	862
	863	nb_sim = 0
	864	sim_channels = 0
	865	seg_sim_base = 0xFFFFFFFF
	866	seg_sim_size = 0
	867
	868	nb_tim = 0
	869	tim_channels = 0
	870	seg_tim_base = 0xFFFFFFFF
	871	seg_tim_size = 0
	872
	873	nb_tty = 0
	874	tty_channels = 0
	875	seg_tty_base = 0xFFFFFFFF
	876	seg_tty_size = 0
	877
	878	nb_xcu = 0
	879	xcu_channels = 0
[328]	880	xcu_arg = 0
[319]	881	seg_xcu_base = 0xFFFFFFFF
	882	seg_xcu_size = 0
	883
	884	use_bdv = False
	885	use_spi = False
	886	use_hba = False
	887
	888	# get peripherals attributes
	889	for cluster in self.clusters:
	890	for periph in cluster.periphs:
	891	if ( periph.ptype == 'CMA' ):
	892	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
	893	seg_cma_size = periph.pseg.size
	894	cma_channels = periph.channels
	895	nb_cma +=1
	896
	897	elif ( periph.ptype == 'DMA' ):
	898	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
	899	seg_dma_size = periph.pseg.size
	900	dma_channels = periph.channels
	901	nb_dma +=1
	902
	903	elif ( periph.ptype == 'FBF' ):
	904	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
	905	seg_fbf_size = periph.pseg.size
	906	fbf_channels = periph.channels
[328]	907	fbf_arg = periph.arg
[319]	908	nb_fbf +=1
	909
	910	elif ( periph.ptype == 'ICU' ):
	911	seg_icu_base = periph.pseg.base & 0xFFFFFFFF
	912	seg_icu_size = periph.pseg.size
	913	icu_channels = periph.channels
	914	nb_icu +=1
	915
	916	elif ( periph.ptype == 'IOB' ):
	917	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
	918	seg_iob_size = periph.pseg.size
	919	iob_channels = periph.channels
	920	nb_iob +=1
	921
	922	elif ( periph.ptype == 'IOC' ):
	923	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
	924	seg_ioc_size = periph.pseg.size
	925	ioc_channels = periph.channels
	926	nb_ioc += 1
[404]	927
	928	if self.use_ramdisk: continue
	929
[319]	930	if ( periph.subtype == 'BDV' ): use_bdv = True
	931	elif ( periph.subtype == 'HBA' ): use_hba = True
	932	elif ( periph.subtype == 'SPI' ): use_spi = True
	933
	934	elif ( periph.ptype == 'MMC' ):
	935	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
	936	seg_mmc_size = periph.pseg.size
	937	mmc_channels = periph.channels
	938	nb_mmc +=1
	939
	940	elif ( periph.ptype == 'MWR' ):
	941	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
	942	seg_wmr_size = periph.pseg.size
	943	mwr_channels = periph.channels
	944	nb_mwr +=1
	945
	946	elif ( periph.ptype == 'ROM' ):
	947	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
	948	seg_rom_size = periph.pseg.size
	949	rom_channels = periph.channels
	950	nb_rom +=1
	951
	952	elif ( periph.ptype == 'SIM' ):
	953	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
	954	seg_sim_size = periph.pseg.size
	955	sim_channels = periph.channels
	956	nb_sim +=1
	957
	958	elif ( periph.ptype == 'NIC' ):
	959	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
	960	seg_nic_size = periph.pseg.size
	961	nic_channels = periph.channels
	962	nb_nic +=1
	963
	964	elif ( periph.ptype == 'PIC' ):
	965	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
	966	seg_pic_size = periph.pseg.size
	967	pic_channels = periph.channels
	968	nb_pic +=1
	969
	970	elif ( periph.ptype == 'TIM' ):
	971	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
	972	seg_tim_size = periph.pseg.size
	973	tim_channels = periph.channels
	974	nb_tim +=1
	975
	976	elif ( periph.ptype == 'TTY' ):
	977	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
	978	seg_tty_size = periph.pseg.size
	979	tty_channels = periph.channels
	980	nb_tty +=1
	981
	982	elif ( periph.ptype == 'XCU' ):
	983	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
	984	seg_xcu_size = periph.pseg.size
	985	xcu_channels = periph.channels
[328]	986	xcu_arg = periph.arg
[319]	987	nb_xcu +=1
	988
	989	# don't mix ICU and XCU
	990	assert ( nb_icu*nb_xcu == 0 )
	991
	992	# no more than two access to external peripherals
	993	assert ( nb_fbf <= 2 )
	994	assert ( nb_cma <= 2 )
	995	assert ( nb_ioc <= 2 )
	996	assert ( nb_nic <= 2 )
	997	assert ( nb_tim <= 2 )
	998	assert ( nb_tty <= 2 )
	999	assert ( nb_pic <= 2 )
	1000
	1001	# one and only one type of IOC controller
[403]	1002	nb_iocs = 0
	1003	if use_hba : nb_iocs += 1
	1004	if use_bdv : nb_iocs += 1
	1005	if use_spi : nb_iocs += 1
	1006	if self.use_ramdisk: nb_iocs += 1
	1007	assert ( nb_iocs == 1 )
[404]	1008
[319]	1009	# Compute total number of processors
	1010	for cluster in self.clusters:
	1011	nb_total_procs += len( cluster.procs )
	1012
	1013	# Compute physical addresses for BOOT vsegs
	1014	boot_mapping_found = False
	1015	boot_code_found = False
	1016	boot_data_found = False
	1017	boot_stack_found = False
	1018
	1019	for vseg in self.globs:
	1020	if ( vseg.name == 'seg_boot_mapping' ):
	1021	boot_mapping_base = vseg.vbase
	1022	boot_mapping_size = vseg.vobjs[0].length
[348]	1023	boot_mapping_identity = vseg.identity
[319]	1024	boot_mapping_found = True
	1025
	1026	if ( vseg.name == 'seg_boot_code' ):
	1027	boot_code_base = vseg.vbase
	1028	boot_code_size = vseg.vobjs[0].length
[348]	1029	boot_code_identity = vseg.identity
[319]	1030	boot_code_found = True
	1031
	1032	if ( vseg.name == 'seg_boot_data' ):
	1033	boot_data_base = vseg.vbase
	1034	boot_data_size = vseg.vobjs[0].length
[348]	1035	boot_data_identity = vseg.identity
[319]	1036	boot_data_found = True
	1037
	1038	if ( vseg.name == 'seg_boot_stack' ):
	1039	boot_stack_base = vseg.vbase
	1040	boot_stack_size = vseg.vobjs[0].length
[348]	1041	boot_stack_identity = vseg.identity
[319]	1042	boot_stack_found = True
	1043
[328]	1044	# check that BOOT vsegs are found and identity mapping
[348]	1045	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
	1046	print '[genmap error] in hard_config() : seg_boot_mapping missing or not ident'
[319]	1047	sys.exit()
	1048
[348]	1049	if ( (boot_code_found == False) or (boot_code_identity == False) ):
	1050	print '[genmap error] in hard_config() : seg_boot_code missing or not ident'
[319]	1051	sys.exit()
	1052
[348]	1053	if ( (boot_data_found == False) or (boot_data_identity == False) ):
	1054	print '[genmap error] in hard_config() : seg_boot_data missing or not ident'
[319]	1055	sys.exit()
	1056
[348]	1057	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
	1058	print '[genmap error] in giet_vsegs() : seg_boot_stack missing or not ident'
[319]	1059	sys.exit()
	1060
	1061	# Search RAMDISK global vseg if required
	1062	seg_rdk_base = 0xFFFFFFFF
	1063	seg_rdk_size = 0
	1064	seg_rdk_found = False
	1065
	1066	if self.use_ramdisk:
	1067	for vseg in self.globs:
[404]	1068	if ( vseg.name == 'seg_rdk' ):
[319]	1069	seg_rdk_base = vseg.vbase
	1070	seg_rdk_size = vseg.vobjs[0].length
	1071	seg_rdk_found = True
	1072
	1073	if ( seg_rdk_found == False ):
	1074	print 'Error in hard_config() "seg_ramdisk" not found'
	1075	sys.exit(1)
	1076
	1077	# build string
[327]	1078	s = '/* Generated by genmap for %s */\n' % self.name
[319]	1079	s += '\n'
	1080	s += '#ifndef HARD_CONFIG_H\n'
	1081	s += '#define HARD_CONFIG_H\n'
	1082	s += '\n'
	1083
	1084	s += '/* General platform parameters */\n'
	1085	s += '\n'
	1086	s += '#define X_SIZE %d\n' % self.x_size
	1087	s += '#define Y_SIZE %d\n' % self.y_size
	1088	s += '#define X_WIDTH %d\n' % self.x_width
	1089	s += '#define Y_WIDTH %d\n' % self.y_width
	1090	s += '#define X_IO %d\n' % self.x_io
	1091	s += '#define Y_IO %d\n' % self.y_io
	1092	s += '#define NB_PROCS_MAX %d\n' % self.procs_max
	1093	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
	1094	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
	1095	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
	1096	s += '\n'
	1097
	1098	s += '/* Peripherals */\n'
	1099	s += '\n'
	1100	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
	1101	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
	1102	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
	1103	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
	1104	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
	1105	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
	1106	s += '\n'
	1107	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
	1108	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
	1109	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
	1110	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
	1111	s += '\n'
	1112	s += '#define USE_IOC_BDV %d\n' % use_bdv
	1113	s += '#define USE_IOC_SPI %d\n' % use_spi
	1114	s += '#define USE_IOC_HBA %d\n' % use_hba
[403]	1115	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
[319]	1116	s += '\n'
[328]	1117	s += '#define FBUF_X_SIZE %d\n' % fbf_arg
	1118	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg
	1119	s += '\n'
	1120	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg
	1121	s += '\n'
[319]	1122
[356]	1123	s += '/* base addresses and sizes for physical segments */\n'
[319]	1124	s += '\n'
[356]	1125	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
	1126	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
	1127	s += '\n'
[319]	1128	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
	1129	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
	1130	s += '\n'
	1131	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
[341]	1132	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
[319]	1133	s += '\n'
	1134	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
[341]	1135	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
[319]	1136	s += '\n'
	1137	s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base
[341]	1138	s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size
[319]	1139	s += '\n'
	1140	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
[341]	1141	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
[319]	1142	s += '\n'
	1143	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
	1144	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
	1145	s += '\n'
	1146	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
	1147	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
	1148	s += '\n'
	1149	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
	1150	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
	1151	s += '\n'
	1152	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
	1153	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
	1154	s += '\n'
	1155	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
	1156	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
	1157	s += '\n'
	1158	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
	1159	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
	1160	s += '\n'
	1161	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
	1162	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
	1163	s += '\n'
	1164	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
	1165	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
	1166	s += '\n'
	1167	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
	1168	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
	1169	s += '\n'
	1170	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
	1171	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
	1172	s += '\n'
	1173	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
	1174	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
	1175	s += '\n'
[328]	1176	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
[319]	1177	s += '\n'
	1178
[326]	1179	s += '/* physical base addresses for identity mapped vsegs */\n'
	1180	s += '/* used by the GietVM OS */\n'
[319]	1181	s += '\n'
	1182	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
	1183	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
	1184	s += '\n'
	1185	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
	1186	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
	1187	s += '\n'
	1188	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
	1189	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
	1190	s += '\n'
	1191	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
	1192	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
	1193	s += '#endif\n'
	1194
	1195	return s
	1196
	1197	# end of hard_config()
	1198
	1199	#######################
	1200	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
	1201	# used for netbsd configuration
	1202	# header
	1203	s = '/dts-v1/;\n'
	1204	s += '\n'
	1205	s += '/{\n'
	1206	s += ' #address-cells = <2>;\n'
	1207	s += ' #size-cells = <1>;\n'
	1208
	1209	# cpus (for each cluster)
	1210	s += ' cpus {\n'
	1211	s += ' #address-cells = <1>;\n'
	1212	s += ' #size-cells = <0>;\n'
	1213
	1214	for cluster in self.clusters:
	1215	for proc in cluster.procs:
	1216	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid
	1217
	1218	s += ' Mips,32@0x%x {\n' % proc_id
	1219	s += ' device_type = "cpu";\n'
	1220	s += ' icudev_type = "cpu:mips";\n'
	1221	s += ' name = "Mips,32";\n'
	1222	s += ' reg = <0x%x>;\n' % proc_id
	1223	s += ' };\n'
	1224	s += '\n'
	1225
	1226	s += ' };\n'
	1227
	1228	# rams (for each cluster)
	1229	for cluster in self.clusters:
	1230	for pseg in cluster.psegs:
	1231
	1232	if ( pseg.segtype == 'RAM' ):
	1233	msb = pseg.base >> 32
	1234	lsb = pseg.base & 0xFFFFFFFF
	1235	size = pseg.size
	1236
	1237	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
	1238	s += ' cached = <1>;\n'
	1239	s += ' device_type = "memory";\n'
	1240	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1241	s += ' };\n'
	1242
	1243	# peripherals (for each cluster)
	1244	for cluster in self.clusters:
	1245
	1246	# research XCU component
	1247	found_xcu = False
	1248	for periph in cluster.periphs:
	1249	if ( (periph.ptype == 'XCU') ):
	1250	found_xcu = True
	1251	xcu = periph
	1252	msb = periph.pseg.base >> 32
	1253	lsb = periph.pseg.base & 0xFFFFFFFF
	1254	size = periph.pseg.size
	1255
	1256	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1257	s += ' device_type = "soclib:xicu:root";\n'
	1258	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
[400]	1259	s += ' input_lines = <%d>;\n' % periph.arg
	1260	s += ' ipis = <%d>;\n' % periph.arg
	1261	s += ' timers = <%d>;\n' % periph.arg
[319]	1262
	1263	output_id = 0 # output index from XCU
	1264	for lpid in xrange ( len(cluster.procs) ): # destination processor index
	1265	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
	1266	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid
	1267	s += ' out@%d {\n' % output_id
	1268	s += ' device_type = "soclib:xicu:filter";\n'
	1269	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
	1270	s += ' output_line = <%d>;\n' % output_id
	1271	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1272	s += ' };\n'
	1273
	1274	output_id += 1
	1275
	1276	s += ' };\n'
	1277
	1278	# research PIC component
	1279	found_pic = False
	1280	for periph in cluster.periphs:
	1281	if ( periph.ptype == 'PIC' ):
	1282	found_pic = True
	1283	pic = periph
	1284	msb = periph.pseg.base >> 32
	1285	lsb = periph.pseg.base & 0xFFFFFFFF
	1286	size = periph.pseg.size
	1287
	1288	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1289	s += ' device_type = "soclib:pic:root";\n'
	1290	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1291	s += ' input_lines = <%d>;\n' % periph.channels
	1292	s += ' };\n'
	1293
	1294	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
[348]	1295	print '[genmap error] in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y)
[319]	1296	sys.exit(1)
	1297
	1298	if ( found_pic == True ): irq_tgt = pic
	1299	else: irq_tgt = xcu
	1300
	1301	# get all others peripherals in cluster
	1302	for periph in cluster.periphs:
	1303	msb = periph.pseg.base >> 32
	1304	lsb = periph.pseg.base & 0xFFFFFFFF
	1305	size = periph.pseg.size
	1306
	1307	# research DMA component
	1308	if ( periph.ptype == 'DMA' ):
	1309
	1310	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1311	s += ' device_type = "soclib:dma";\n'
	1312	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1313	s += ' channel_count = <%d>;\n' % periph.channels
	1314
	1315	# multi-channels : get HWI index (to XCU) for each channel
	1316	for channel in xrange( periph.channels ):
	1317	hwi_id = 0xFFFFFFFF
	1318	for irq in xcu.irqs:
	1319	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
	1320	hwi_id = irq.srcid
	1321	if ( hwi_id == 0xFFFFFFFF ):
[348]	1322	print '[genmap error] in netbsd.dts() ISR_DMA channel %d not found' % channel
[319]	1323	sys.exit(1)
	1324
	1325	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
	1326	s += ' irq@%d{\n' % channel
	1327	s += ' device_type = "soclib:periph:irq";\n'
	1328	s += ' output_line = <%d>;\n' % channel
	1329	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1330	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1331	s += ' };\n'
	1332
	1333	s += ' };\n'
	1334
	1335	# research MMC component
	1336	elif ( periph.ptype == 'MMC' ):
	1337
	1338	# get irq line index associated to MMC in XCU
	1339	irq_in = 0xFFFFFFFF
	1340	for irq in xcu.irqs:
	1341	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
	1342	if ( irq_in == 0xFFFFFFFF ):
[348]	1343	print '[genmap error] in netbsd.dts() ISR_MMC not found'
[319]	1344	sys.exit(1)
	1345
	1346	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1347	s += ' device_type = "soclib:mmc";\n'
	1348	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1349	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1350	s += ' };\n'
	1351
	1352	# research FBF component
	1353	elif ( periph.ptype == 'FBF' ):
	1354
	1355	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1356	s += ' device_type = "soclib:framebuffer";\n'
	1357	s += ' mode = <32>;\n' # bits par pixel
[400]	1358	s += ' width = <%d>;\n' % periph.arg
	1359	s += ' height = <%d>;\n' % periph.arg
[319]	1360	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1361	s += ' };\n'
	1362
	1363	# research IOC component
	1364	elif ( periph.ptype == 'IOC' ):
	1365
	1366	if ( periph.subtype == 'BDV' ):
	1367
	1368	# get irq line index associated to bdv
	1369	irq_in = 0xFFFFFFFF
	1370	for irq in irq_tgt.irqs:
	1371	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
	1372	if ( irq_in == 0xFFFFFFFF ):
[348]	1373	print '[genmap error] in netbsd.dts() ISR_BDV not found'
[319]	1374	sys.exit(1)
	1375
	1376	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1377	s += ' device_type = "soclib:blockdevice";\n'
	1378	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1379	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1380	s += ' };\n'
	1381
	1382	elif ( periph.subtype == 'HBA' ):
[348]	1383	print '[genmap error] in netbsd_dts() : HBA peripheral not supported by NetBSD'
[319]	1384	sys.exit(1)
	1385
	1386	elif ( periph.subtype == 'SPI' ):
	1387
	1388	# get irq line index associated to spi
	1389	irq_in = 0xFFFFFFFF
	1390	for irq in irq_tgt.irqs:
	1391	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
	1392	if ( irq_in == 0xFFFFFFFF ):
[348]	1393	print '[genmap error] in netbsd.dts() ISR_SPI not found'
[319]	1394	sys.exit(1)
	1395
	1396	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1397	s += ' device_type = "soclib:spi";\n'
	1398	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
	1399	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1400	s += ' };\n'
	1401
	1402	# research ROM component
	1403	elif ( periph.ptype == 'ROM' ):
	1404
	1405	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1406	s += ' device_type = "rom";\n'
	1407	s += ' cached = <1>;\n'
	1408	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1409	s += ' };\n'
	1410
	1411	# research SIM component
	1412	elif ( periph.ptype == 'SIM' ):
	1413
	1414	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1415	s += ' device_type = "soclib:simhelper";\n'
	1416	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1417	s += ' };\n'
	1418
	1419	# research TTY component
	1420	elif ( periph.ptype == 'TTY' ):
	1421
	1422	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1423	s += ' device_type = "soclib:tty";\n'
	1424	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1425	s += ' channel_count = < %d >;\n' % periph.channels
	1426
	1427	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1428	for channel in xrange( periph.channels ):
	1429	hwi_id = 0xFFFFFFFF
	1430	for irq in irq_tgt.irqs:
	1431	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
	1432	hwi_id = irq.srcid
	1433	if ( hwi_id == 0xFFFFFFFF ):
[348]	1434	print '[genmap error] in netbsd.dts() ISR_TTY_RX channel %d not found' % channel
[319]	1435	sys.exit(1)
	1436
	1437	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1438	s += ' irq@%d{\n' % channel
	1439	s += ' device_type = "soclib:periph:irq";\n'
	1440	s += ' output_line = <%d>;\n' % channel
	1441	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1442	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1443	s += ' };\n'
	1444
	1445	s += ' };\n'
	1446
	1447	# research IOB component
	1448	elif ( periph.ptype == 'IOB' ):
	1449
	1450	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1451	s += ' device_type = "soclib:iob";\n'
	1452	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1453	s += ' };\n'
	1454
	1455	# research NIC component
	1456	elif ( periph.ptype == 'NIC' ):
	1457
	1458	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1459	s += ' device_type = "soclib:nic";\n'
	1460	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1461	s += ' channel_count = < %d >;\n' % periph.channels
	1462
	1463	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
	1464	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
	1465	for channel in xrange( periph.channels ):
	1466	hwi_id = 0xFFFFFFFF
	1467	for irq in irq_tgt.irqs:
	1468	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
	1469	hwi_id = irq.srcid
	1470	if ( hwi_id == 0xFFFFFFFF ):
[348]	1471	print '[genmap error] in netbsd.dts() ISR_NIC_RX channel %d not found' % channel
[319]	1472	sys.exit(1)
	1473
	1474	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1475	s += ' irq_rx@%d{\n' % channel
	1476	s += ' device_type = "soclib:periph:irq";\n'
	1477	s += ' output_line = <%d>;\n' % (2*channel)
	1478	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1479	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1480	s += ' };\n'
	1481
	1482	hwi_id = 0xFFFFFFFF
	1483	for irq in irq_tgt.irqs:
	1484	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
	1485	hwi_id = irq.srcid
	1486	if ( hwi_id == 0xFFFFFFFF ):
[348]	1487	print '[genmap error] in netbsd.dts() ISR_NIC_TX channel %d not found' % channel
[319]	1488	sys.exit(1)
	1489
	1490	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1491	s += ' irq_tx@%d{\n' % channel
	1492	s += ' device_type = "soclib:periph:irq";\n'
	1493	s += ' output_line = <%d>;\n' % (2*channel + 1)
	1494	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1495	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1496	s += ' };\n'
	1497
	1498	s += ' };\n'
	1499
	1500	# research CMA component
	1501	elif ( periph.ptype == 'CMA' ):
	1502
	1503	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
	1504	s += ' device_type = "soclib:cma";\n'
	1505	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
	1506	s += ' channel_count = < %d >;\n' % periph.channels
	1507
	1508	# multi-channels : get HWI index (to XCU or PIC) for each channel
	1509	for channel in xrange( periph.channels ):
	1510	hwi_id = 0xFFFFFFFF
	1511	for irq in irq_tgt.irqs:
	1512	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
	1513	hwi_id = irq.srcid
	1514	if ( hwi_id == 0xFFFFFFFF ):
[348]	1515	print '[genmap error] in netbsd.dts() ISR_CMA channel %d not found' % channel
[319]	1516	sys.exit(1)
	1517
	1518	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
	1519	s += ' irq@%d{\n' % channel
	1520	s += ' device_type = "soclib:periph:irq";\n'
	1521	s += ' output_line = <%d>;\n' % channel
	1522	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
	1523	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
	1524	s += ' };\n'
	1525
	1526	s += ' };\n'
	1527
	1528	# research TIM component
	1529	elif ( periph.ptype == 'TIM' ):
	1530
[348]	1531	print '[genmap error] in netbsd_dts() : TIM peripheral not supported by NetBSD'
[319]	1532	sys.exit(1)
	1533
	1534	# research MWR component
	1535	elif ( periph.ptype == 'MWR' ):
	1536
[348]	1537	print '[genmap error] in netbsd_dts() : MWR peripheral not supported by NetBSD'
[319]	1538	sys.exit(1)
	1539
	1540	# research ICU component
	1541	elif ( periph.ptype == 'ICU' ):
[348]	1542	print '[genmap error] in netbsd_dts() : ICU peripheral not supported by NetBSD'
[319]	1543	sys.exit(1)
	1544
	1545	# topology
	1546	s += '\n'
	1547	s += ' topology {\n'
	1548	s += ' #address-cells = <2>;\n'
	1549	s += ' #size-cells = <0>;\n'
	1550	for cluster in self.clusters:
	1551	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
	1552	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
	1553	s += ' devices = <\n'
	1554
	1555	offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max
	1556	for proc in cluster.procs:
	1557	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
	1558	for periph in cluster.periphs:
	1559	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
	1560
	1561	s += ' >;\n'
	1562	s += ' };\n'
	1563	s += ' };\n'
	1564	s += '};\n'
	1565
	1566	return s
	1567	# end netbsd_dts( )
	1568
	1569	###########################
	1570	def almos_archinfo( self ): # compute string for arch.info file generation,
	1571	# used for almos configuration
	1572	# header
[327]	1573	s = '# arch.info file generated by genmap for %s\n' % self.name
[319]	1574	s += '\n'
	1575	s += '[HEADER]\n'
	1576	s += ' REVISION=1\n'
	1577	s += ' ARCH=%s\n' % self.name
	1578	s += ' XMAX=%d\n' % self.x_size
	1579	s += ' YMAX=%d\n' % self.y_size
	1580	s += ' CPU_NR=%d\n' % self.procs_max
	1581	s += '\n'
	1582
	1583	# clusters
	1584	cluster_id = 0
	1585	for cluster in self.clusters:
	1586
	1587	ram = None
	1588	nb_cpus = len( cluster.procs )
	1589	nb_devs = len( cluster.periphs )
	1590	if ( len( cluster.coprocs ) != 0 ):
	1591	print 'Error in almos_archinfo() coprocessors not supported yet'
	1592	sys.exit(1)
	1593
	1594	# search a RAM
	1595	for pseg in cluster.psegs:
	1596	if ( pseg.segtype == 'RAM' ):
	1597	ram = pseg
	1598	nb_devs += 1
	1599
	1600	# search XCU to get IRQs indexes if cluster contains peripherals
	1601	if ( len( cluster.periphs ) != 0 ):
	1602	tty_irq_id = None
	1603	bdv_irq_id = None
	1604	dma_irq_id = None
	1605
	1606	for periph in cluster.periphs:
	1607	if ( periph.ptype == 'XCU' ):
	1608	# scan irqs
	1609	for irq in periph.irqs:
	1610	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
	1611	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
	1612	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
	1613
	1614	# Build the cluster description
	1615	s += '[CLUSTER]\n'
	1616	s += ' CID=%d\n' % cluster_id
	1617	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
	1618	s += ' CPU_NR=%d\n' % nb_cpus
	1619	s += ' DEV_NR=%d\n' % nb_devs
	1620
	1621
	1622	# Handling RAM when cluster contain a RAM
	1623	if (ram != None ):
	1624	base = ram.base
	1625	size = ram.size
	1626	irqid = -1
	1627	s += ' DEVID=RAM'
	1628	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1629
	1630	# Handling peripherals
	1631	for periph in cluster.periphs:
	1632	base = periph.pseg.base
	1633	size = periph.pseg.size
	1634
	1635	if ( periph.ptype == 'XCU' ):
	1636
	1637	s += ' DEVID=XICU'
	1638	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1639
	1640	elif ( (periph.ptype == 'TTY')
	1641	and (tty_irq_id != None) ):
	1642
	1643	s += ' DEVID=TTY'
	1644	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
	1645
	1646	elif ( (periph.ptype == 'DMA')
	1647	and (dma_irq_id != None) ):
	1648
	1649	s += ' DEVID=DMA'
	1650	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
	1651
	1652	elif ( periph.ptype == 'FBF' ):
	1653
	1654	s += ' DEVID=FB'
	1655	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1656
	1657	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
	1658	and (bdv_irq_id != None) ):
	1659
	1660	s += ' DEVID=BLKDEV'
	1661	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
	1662
	1663	elif ( periph.ptype == 'PIC' ):
	1664
	1665	s += ' DEVID=IOPIC'
	1666	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
	1667
	1668	else:
	1669	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
	1670	% (cluster.x, cluster.y)
	1671	print '# peripheral type %s/%s not supported yet\n' \
	1672	% ( periph.ptype, periph.subtype )
	1673
	1674	cluster_id += 1
	1675
	1676	return s
	1677
	1678	# end of almos_archinfo()
	1679
	1680
	1681
	1682
	1683
	1684
	1685
	1686
	1687	###########################################################################################
	1688	class Cluster ( object ):
	1689	###########################################################################################
	1690	def __init__( self,
	1691	x,
	1692	y ):
	1693
	1694	self.index = 0 # global index (set by Mapping constructor)
	1695	self.x = x # x coordinate
	1696	self.y = y # y coordinate
	1697	self.psegs = [] # filled by addRam() or addPeriph()
	1698	self.procs = [] # filled by addProc()
	1699	self.coprocs = [] # filled by addCoproc()
	1700	self.periphs = [] # filled by addPeriph()
	1701
	1702	return
	1703
	1704	################
	1705	def xml( self ): # xml for a cluster
	1706
	1707	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
	1708	for pseg in self.psegs: s += pseg.xml()
	1709	for proc in self.procs: s += proc.xml()
	1710	for copr in self.coprocs: s += copr.xml()
	1711	for peri in self.periphs: s += peri.xml()
	1712	s += ' </cluster>\n'
	1713
	1714	return s
	1715
	1716	#############################################
	1717	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
	1718
	1719	if ( verbose ):
	1720	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
	1721
	1722	# check index
	1723	if (self.index != expected):
[348]	1724	print '[genmap error] in Cluster.cbin() : cluster global index = %d / expected = %d' \
[319]	1725	% (self.index, expected )
	1726	sys.exit(1)
	1727
	1728	# compute global index for first pseg
	1729	if ( len(self.psegs) > 0 ):
	1730	pseg_id = self.psegs[0].index
	1731	else:
	1732	pseg_id = 0
	1733
	1734	# compute global index for first proc
	1735	if ( len(self.procs) > 0 ):
	1736	proc_id = self.procs[0].index
	1737	else:
	1738	proc_id = 0
	1739
	1740	# compute global index for first coproc
	1741	if ( len(self.coprocs) > 0 ):
	1742	coproc_id = self.coprocs[0].index
	1743	else:
	1744	coproc_id = 0
	1745
	1746	# compute global index for first periph
	1747	if ( len(self.periphs) > 0 ):
	1748	periph_id = self.periphs[0].index
	1749	else:
	1750	periph_id = 0
	1751
	1752	byte_stream = bytearray()
	1753	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
	1754	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
	1755	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster
	1756	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
	1757	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster
	1758	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
	1759	byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster
	1760	byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index
	1761	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster
	1762	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
	1763
	1764	if ( verbose ):
	1765	print 'nb_psegs = %d' % len( self.psegs )
	1766	print 'pseg_id = %d' % pseg_id
	1767	print 'nb_procs = %d' % len( self.procs )
	1768	print 'proc_id = %d' % proc_id
	1769	print 'nb_coprocs = %d' % len( self.coprocs )
	1770	print 'coproc_id = %d' % coproc_id
	1771	print 'nb_periphs = %d' % len( self.periphs )
	1772	print 'periph_id = %d' % periph_id
	1773
	1774	return byte_stream
	1775
	1776	###########################################################################################
[305]	1777	class Vspace( object ):
[319]	1778	###########################################################################################
	1779	def __init__( self,
	1780	name,
	1781	startname ):
	1782
	1783	self.index = 0 # global index ( set by addVspace() )
	1784	self.name = name # vspace name
[305]	1785	self.startname = startname # name of vobj containing the start_vector
[319]	1786	self.vsegs = []
[305]	1787	self.tasks = []
	1788
	1789	return
	1790
[319]	1791	################
	1792	def xml( self ): # xml for one vspace
	1793
[305]	1794	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
[319]	1795	for vseg in self.vsegs: s += vseg.xml()
	1796	for task in self.tasks: s += task.xml()
[305]	1797	s += ' </vspace>\n'
[319]	1798
[305]	1799	return s
	1800
[319]	1801	#############################################
	1802	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
	1803
	1804	if ( verbose ):
	1805	print '*** cbin for vspace %s' % (self.name)
	1806
	1807	# check index
	1808	if (self.index != expected):
[348]	1809	print '[genmap error] in Vspace.cbin() : vspace global index = %d / expected = %d' \
[319]	1810	% (self.index, expected )
	1811	sys.exit(1)
	1812
	1813	# compute global index for vobj containing start_vector
	1814	vobj_start_id = 0xFFFFFFFF
	1815	for vseg in self.vsegs:
	1816	if ( vseg.vobjs[0].name == self.startname ):
	1817	vobj_start_id = vseg.vobjs[0].index
	1818	if ( vobj_start_id == 0xFFFFFFFF ):
[348]	1819	print '[genmap error] in Vspace.cbin() : startname %s not found for vspace %s' \
[319]	1820	% ( self.startname, self.name )
	1821	sys.exit(1)
	1822
	1823	# compute first vseg, vobj, task global index
	1824	first_vseg_id = self.vsegs[0].index
	1825	first_vobj_id = self.vsegs[0].vobjs[0].index
	1826	first_task_id = self.tasks[0].index
	1827
	1828	# compute number of vobjs, tasks, vsegs
	1829	nb_vsegs = len( self.vsegs )
	1830	nb_tasks = len( self.tasks )
	1831	nb_vobjs = 0
	1832	for vseg in self.vsegs:
	1833	nb_vobjs += len( vseg.vobjs )
	1834
	1835	byte_stream = bytearray()
	1836	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
	1837	byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector
	1838	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
	1839	byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs
	1840	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
	1841	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
	1842	byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index
	1843	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
	1844
	1845	if ( verbose ):
	1846	print 'start_id = %d' % vobj_start_id
	1847	print 'nb_vsegs = %d' % nb_vsegs
	1848	print 'nb_vobjs = %d' % nb_vobjs
	1849	print 'nb_tasks = %d' % nb_tasks
	1850	print 'vseg_id = %d' % first_vseg_id
	1851	print 'vobj_id = %d' % first_vobj_id
	1852	print 'task_id = %d' % first_task_id
	1853
	1854	return byte_stream
	1855
	1856	###########################################################################################
[305]	1857	class Task( object ):
[319]	1858	###########################################################################################
	1859	def __init__( self,
	1860	name,
	1861	trdid,
	1862	x,
	1863	y,
	1864	p,
	1865	stackname,
	1866	heapname,
	1867	startid,
	1868	usetty = False,
	1869	usenic = False,
	1870	usecma = False,
	1871	usehba = False,
	1872	usetim = False ):
	1873
	1874	self.index = 0 # global index value set by addTask()
	1875	self.name = name # tsk name
	1876	self.trdid = trdid # task index (unique in vspace)
	1877	self.x = x # cluster x coordinate
	1878	self.y = y # cluster y coordinate
	1879	self.p = p # processor local index
	1880	self.stackname = stackname # name of vobj containing the stack
	1881	self.heapname = heapname # name of vobj containing the heap
	1882	self.startid = startid # index in start_vector
	1883	self.usetty = usetty # request a private TTY channel
	1884	self.usenic = usenic # request a private NIC channel
	1885	self.usecma = usecma # request a private CMA channel
	1886	self.usehba = usehba # request a private HBA channel
	1887	self.usetim = usetim # request a private TIM channel
[305]	1888	return
	1889
[319]	1890	################
	1891	def xml( self ): # xml for one task
	1892
	1893	s = ' <task name="%s"' % self.name
	1894	s += ' trdid="%d"' % self.trdid
	1895	s += ' x="%d"' % self.x
	1896	s += ' y="%d"' % self.y
	1897	s += ' p="%d"' % self.p
	1898	s += ' stackname="%s"' % self.stackname
	1899	s += ' heapname="%s"' % self.heapname
	1900	s += ' startid="%d"' % self.startid
	1901	if self.usetty != 0: s += ' usetty="1"'
	1902	if self.usenic != 0: s += ' usenic="1"'
	1903	if self.usecma != 0: s += ' usehba="1"'
	1904	if self.usehba != 0: s += ' usehba="1"'
	1905	if self.usetim != 0: s += ' usehba="1"'
[305]	1906	s += ' />\n'
[319]	1907
[305]	1908	return s
	1909
[319]	1910	#####################################################
	1911	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
	1912
	1913	if ( verbose ):
	1914	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
	1915
	1916	# check index
	1917	if (self.index != expected):
[348]	1918	print '[genmap error] in Task.cbin() : task global index = %d / expected = %d' \
[319]	1919	% (self.index, expected )
	1920	sys.exit(1)
	1921
	1922	# compute cluster global index
	1923	cluster_id = (self.x * mapping.y_size) + self.y
	1924
	1925	# compute vobj local index for stack
	1926	vobj_stack_id = 0xFFFFFFFF
	1927	for vseg in vspace.vsegs:
	1928	if ( vseg.vobjs[0].name == self.stackname ):
	1929	vobj_stack_id = vseg.vobjs[0].index
	1930	if ( vobj_stack_id == 0xFFFFFFFF ):
[348]	1931	print '[genmap error] in Task.cbin() : stackname %s not found for task %s in vspace %s' \
[319]	1932	% ( self.stackname, self.name, vspace.name )
	1933	sys.exit(1)
	1934
	1935	# compute vobj local index for heap
	1936	vobj_heap_id = 0xFFFFFFFF
	1937	for vseg in vspace.vsegs:
	1938	if ( vseg.vobjs[0].name == self.heapname ):
	1939	vobj_heap_id = vseg.vobjs[0].index
	1940	if ( vobj_heap_id == 0xFFFFFFFF ):
[348]	1941	print '[genmap error] in Task.cbin() : heapname %s not found for task %s in vspace %s' \
[319]	1942	% ( self.heapname, self.name, vspace.name )
	1943	sys.exit(1)
	1944
	1945	byte_stream = bytearray()
	1946	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
	1947	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
	1948	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster
	1949	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
	1950	byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index
	1951	byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index
	1952	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
	1953	byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required
	1954	byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required
	1955	byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required
	1956	byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required
	1957	byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required
	1958
	1959	if ( verbose ):
	1960	print 'clusterid = %d' % cluster_id
	1961	print 'lpid = %d' % self.p
	1962	print 'trdid = %d' % self.trdid
	1963	print 'stackid = %d' % vobj_stack_id
	1964	print 'heapid = %d' % vobj_heap_id
	1965	print 'startid = %d' % self.startid
	1966
	1967	return byte_stream
	1968
	1969	###########################################################################################
[305]	1970	class Vseg( object ):
[319]	1971	###########################################################################################
	1972	def __init__( self,
	1973	name,
	1974	vbase,
	1975	mode,
	1976	x,
	1977	y,
	1978	psegname,
[348]	1979	identity = False,
	1980	local = False ):
[305]	1981
[319]	1982	assert mode in VSEGMODES
	1983
[348]	1984	self.index = 0 # global index ( set by addVseg() )
	1985	self.name = name # vseg name
	1986	self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace
	1987	self.mode = mode # CXWU access rights
	1988	self.x = x # x coordinate of destination cluster
	1989	self.y = y # y coordinate of destination cluster
	1990	self.psegname = psegname # name of pseg in destination cluster
	1991	self.identity = identity # identity mapping required
	1992	self.local = local # one copy per cluster
	1993	self.vobjs = []
[305]	1994	return
	1995
[319]	1996	################
	1997	def xml( self ): # xml for one vseg
	1998
	1999	s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \
	2000	% ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname )
[348]	2001	if ( self.identity ): s += ' ident="1"'
	2002	if ( self.local ): s += ' local="1"'
	2003	s += ' >\n'
	2004	for vobj in self.vobjs: s += vobj.xml()
[319]	2005	s += ' </vseg>\n'
	2006
[305]	2007	return s
	2008
[319]	2009	#############################################
	2010	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
	2011
	2012	if ( verbose ):
	2013	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
	2014
	2015	# check index
	2016	if (self.index != expected):
[348]	2017	print '[genmap error] in Vseg.cbin() : vseg global index = %d / expected = %d' \
[319]	2018	% (self.index, expected )
	2019	sys.exit(1)
	2020
	2021	# compute pseg_id
	2022	pseg_id = 0xFFFFFFFF
	2023	cluster_id = (self.x * mapping.y_size) + self.y
	2024	cluster = mapping.clusters[cluster_id]
	2025	for pseg in cluster.psegs:
	2026	if (self.psegname == pseg.name):
	2027	pseg_id = pseg.index
	2028	if (pseg_id == 0xFFFFFFFF):
[348]	2029	print '[genmap error] in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \
[319]	2030	% ( self.psegname, self.name, cluster_id )
	2031	sys.exit(1)
	2032
	2033	# compute numerical value for mode
	2034	mode_id = 0xFFFFFFFF
	2035	for x in xrange( len(VSEGMODES) ):
	2036	if ( self.mode == VSEGMODES[x] ):
	2037	mode_id = x
	2038	if ( mode_id == 0xFFFFFFFF ):
[348]	2039	print '[genmap error] in Vseg.cbin() : undefined vseg mode %s' % self.mode
[319]	2040	sys.exit(1)
	2041
	2042	# compute vobj_id
	2043	vobj_id = self.vobjs[0].index
	2044
	2045	byte_stream = bytearray()
	2046	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
	2047	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
	2048	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
	2049	byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes)
	2050	byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index
	2051	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
	2052	byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg
	2053	byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index
	2054	byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg
	2055	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
[348]	2056	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping when non zero
	2057	byte_stream += mapping.int2bytes( 1, self.local ) # non shared if non zero
	2058	byte_stream += mapping.int2bytes( 1, 0 ) # reserved (padding)
[319]	2059
	2060	if ( verbose ):
	2061	print 'vbase = %x' % self.vbase
	2062	print 'pseg_id = %d' % pseg_id
	2063	print 'mode = %s' % self.mode
	2064	print 'nb_vobjs = %d' % len(self.vobjs)
	2065	print 'vobj_id = %d' % vobj_id
	2066
	2067	return byte_stream
	2068
	2069	###########################################################################################
[305]	2070	class Vobj( object ):
[319]	2071	###########################################################################################
	2072	def __init__( self,
	2073	name,
	2074	length,
	2075	vtype,
	2076	binpath = '',
	2077	align = 0,
	2078	init = 0 ):
	2079
[305]	2080	assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \
	2081	'BUFFER','BARRIER','CONST','MEMSPACE','SCHED']
[319]	2082
	2083	assert (vtype != 'ELF') or (binpath != '')
	2084
	2085	self.index = 0 # global index ( set by addVobj() )
	2086	self.name = name # vobj name (unique in vspace)
	2087	self.vtype = vtype # vobj type (defined in mapping_info.h)
	2088	self.length = length # vobj size (bytes)
	2089	self.binpath = binpath # pathname for (ELF type)
	2090	self.align = align # required alignment (logarithm of 2)
	2091	self.init = init # initialisation value (for BARRIER or MWMR types)
	2092
[305]	2093	return
	2094
[319]	2095	################
	2096	def xml( self ): # xml for a vobj
	2097
[305]	2098	s = ' <vobj name="%s" type="%s" length="0x%x"' \
	2099	% ( self.name, self.vtype, self.length )
[319]	2100	if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath)
	2101	if (self.align != 0 ): s += ' align="%d"' % (self.align)
	2102	if (self.init != 0 ): s += ' init="%d"' % (self.init)
[305]	2103	s += ' />\n'
[319]	2104
[305]	2105	return s
	2106
[319]	2107	#############################################
	2108	def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj
[305]	2109
[319]	2110	# check index
	2111	if (self.index != expected):
[348]	2112	print '[genmap error] in Vobj.cbin() : vobj global index = %d / expected = %d' \
[319]	2113	% (self.index, expected )
	2114	sys.exit(1)
	2115	elif ( verbose ):
	2116	print '*** cbin for vobj[%d] %s' % (self.index, self.name)
[305]	2117
[319]	2118	# compute numerical value for vtype
	2119	vtype_int = 0xFFFFFFFF
	2120	for x in xrange( len(VOBJTYPES) ):
	2121	if ( self.vtype == VOBJTYPES[x] ):
	2122	vtype_int = x
	2123	if ( vtype_int == 0xFFFFFFFF ):
[348]	2124	print '[genmap error] in Vobj.cbin() : undefined vobj type %s' % self.vtype
[319]	2125	sys.exit(1)
	2126
	2127	byte_stream = bytearray()
	2128	byte_stream += mapping.str2bytes( 32, self.name ) # vobj name
	2129	byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file
	2130	byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type
	2131	byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size
	2132	byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment
	2133	byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address
	2134	byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address
	2135	byte_stream += mapping.int2bytes( 4 , self.init ) # init value
	2136
	2137	if ( verbose ):
	2138	print 'binpath = %s' % self.binpath
	2139	print 'type = %s' % self.vtype
	2140	print 'length = %x' % self.length
	2141
	2142	return byte_stream
	2143
	2144	###########################################################################################
[305]	2145	class Processor ( object ):
[319]	2146	###########################################################################################
	2147	def __init__( self,
	2148	x,
	2149	y,
	2150	lpid ):
	2151
	2152	self.index = 0 # global index ( set by addProc() )
	2153	self.x = x # x cluster coordinate
	2154	self.y = y # y cluster coordinate
	2155	self.lpid = lpid # processor local index
	2156
[305]	2157	return
	2158
[319]	2159	################
	2160	def xml( self ): # xml for a processor
[305]	2161	return ' <proc index="%d" />\n' % (self.lpid)
	2162
[319]	2163	#############################################
	2164	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
	2165
	2166	if ( verbose ):
	2167	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
	2168
	2169	# check index
	2170	if (self.index != expected):
[348]	2171	print '[genmap error] in Proc.cbin() : proc global index = %d / expected = %d' \
[319]	2172	% (self.index, expected )
	2173	sys.exit(1)
	2174
	2175	byte_stream = bytearray()
	2176	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
	2177
	2178	return byte_stream
	2179
	2180	###########################################################################################
[305]	2181	class Pseg ( object ):
[319]	2182	###########################################################################################
	2183	def __init__( self,
	2184	name,
	2185	base,
	2186	size,
	2187	x,
	2188	y,
	2189	segtype ):
	2190
	2191	assert( segtype in PSEGTYPES )
	2192
	2193	self.index = 0 # global index ( set by addPseg() )
	2194	self.name = name # pseg name (unique in cluster)
	2195	self.base = base # physical base address
	2196	self.size = size # segment size (bytes)
	2197	self.x = x # cluster x coordinate
	2198	self.y = y # cluster y coordinate
	2199	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
	2200
[305]	2201	return
	2202
[319]	2203	################
	2204	def xml( self ): # xml for a pseg
	2205
[305]	2206	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
	2207	% (self.name, self.segtype, self.base, self.size)
	2208
[319]	2209	######################################################
	2210	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
	2211
	2212	if ( verbose ):
	2213	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
	2214	% (self.index, self.name, cluster.x, cluster.y)
	2215
	2216	# check index
	2217	if (self.index != expected):
[348]	2218	print '[genmap error] in Pseg.cbin() : pseg global index = %d / expected = %d' \
[319]	2219	% (self.index, expected )
	2220	sys.exit(1)
	2221
	2222	# compute numerical value for segtype
	2223	segtype_int = 0xFFFFFFFF
	2224	for x in xrange( len(PSEGTYPES) ):
	2225	if ( self.segtype == PSEGTYPES[x] ):
	2226	segtype_int = x
	2227	if ( segtype_int == 0xFFFFFFFF ):
[348]	2228	print '[genmap error] in Pseg.cbin() : undefined segment type %s' % self.segtype
[319]	2229	sys.exit(1)
	2230
	2231	byte_stream = bytearray()
	2232	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
	2233	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
	2234	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
	2235	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
	2236	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
	2237	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
	2238
	2239	if ( verbose ):
	2240	print 'pbase = %x' % self.base
	2241	print 'size = %x' % self.size
	2242	print 'type = %s' % self.segtype
	2243
	2244	return byte_stream
	2245
	2246	###########################################################################################
	2247	class Periph ( object ):
	2248	###########################################################################################
	2249	def __init__( self,
	2250	pseg, # associated pseg
	2251	ptype, # peripheral type
	2252	subtype = 'NONE', # peripheral subtype
	2253	channels = 1, # for multi-channels peripherals
	2254	arg = 0 ): # optional argument (semantic depends on ptype)
	2255
	2256	assert ptype in PERIPHTYPES
	2257
	2258	assert subtype in PERIPHSUBTYPES
	2259
	2260	self.index = 0 # global index ( set by addPeriph() )
	2261	self.channels = channels
	2262	self.ptype = ptype
	2263	self.subtype = subtype
	2264	self.arg = arg
	2265	self.pseg = pseg
	2266	self.irqs = []
[305]	2267	return
	2268
[319]	2269	################
	2270	def xml( self ): # xml for a periph
	2271
	2272	s = ' <periph type="%s"' % self.ptype
	2273	s += ' subtype="%s"' % self.subtype
	2274	s += ' psegname="%s"' % self.pseg.name
	2275	s += ' channels="%d"' % self.channels
	2276	s += ' arg="%d" >\n' % self.arg
	2277	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ):
	2278	for irq in self.irqs: s += irq.xml()
[305]	2279	s += ' </periph>\n'
[319]	2280
[305]	2281	return s
	2282
[319]	2283	#############################################
	2284	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
[305]	2285
[319]	2286	if ( verbose ):
	2287	print '*** cbin for periph %s in cluster [%d,%d]' \
	2288	% (self.ptype, self.pseg.x, self.pseg.y)
[305]	2289
[319]	2290	# check index
	2291	if (self.index != expected):
[348]	2292	print '[genmap error] in Periph.cbin() : periph global index = %d / expected = %d' \
[319]	2293	% (self.index, expected )
	2294	sys.exit(1)
[305]	2295
[319]	2296	# compute pseg global index
	2297	pseg_id = self.pseg.index
[305]	2298
[319]	2299	# compute first irq global index
	2300	if ( len(self.irqs) > 0 ):
	2301	irq_id = self.irqs[0].index
	2302	else:
	2303	irq_id = 0
[305]	2304
[319]	2305	# compute numerical value for ptype
	2306	ptype_id = 0xFFFFFFFF
	2307	for x in xrange( len(PERIPHTYPES) ):
	2308	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
	2309	if ( ptype_id == 0xFFFFFFFF ):
[348]	2310	print '[genmap error] in Periph.cbin() : undefined peripheral type %s' % self.ptype
[319]	2311	sys.exit(1)
[305]	2312
[319]	2313	# compute numerical value for subtype
	2314	subtype_id = 0xFFFFFFFF
	2315	for x in xrange( len(PERIPHSUBTYPES) ):
	2316	if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x
[305]	2317
[319]	2318	# compute
	2319	byte_stream = bytearray()
	2320	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
	2321	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
	2322	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
	2323	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
	2324	byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument
	2325	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
	2326	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
[305]	2327
[319]	2328	if ( verbose ):
	2329	print 'ptype = %d' % ptype_id
	2330	print 'pseg_id = %d' % pseg_id
	2331	print 'nb_irqs = %d' % len( self.irqs )
	2332	print 'irq_id = %d' % irq_id
	2333	return byte_stream
[305]	2334
[319]	2335	###########################################################################################
	2336	class Irq ( object ):
	2337	###########################################################################################
	2338	def __init__( self,
	2339	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
	2340	srcid, # input IRQ index (for XCU or PIC)
	2341	isrtype, # Type of ISR to be executed
	2342	channel = 0 ): # channel index for multi-channel ISR
[305]	2343
[319]	2344	assert irqtype in IRQTYPES
	2345	assert isrtype in ISRTYPES
	2346	assert srcid < 32
[305]	2347
[319]	2348	self.index = 0 # global index ( set by addIrq() )
	2349	self.irqtype = irqtype # IRQ type
	2350	self.srcid = srcid # source IRQ index
	2351	self.isrtype = isrtype # ISR type
	2352	self.channel = channel # channel index (for multi-channels ISR)
[305]	2353	return
	2354
[319]	2355	################
	2356	def xml( self ): # xml for Irq
[305]	2357
[319]	2358	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
	2359	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
[305]	2360
[319]	2361	#############################################
	2362	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
[305]	2363
[319]	2364	if ( verbose ):
	2365	print '*** cbin for irq[%d]' % (self.index)
[305]	2366
[319]	2367	# check index
	2368	if (self.index != expected):
[348]	2369	print '[genmap error] in Irq.cbin() : irq global index = %d / expected = %d' \
[319]	2370	% (self.index, expected )
	2371	sys.exit(1)
[305]	2372
[319]	2373	# compute numerical value for irqtype
	2374	irqtype_id = 0xFFFFFFFF
	2375	for x in xrange( len(IRQTYPES) ):
	2376	if ( self.irqtype == IRQTYPES[x] ):
	2377	irqtype_id = x
	2378	if ( irqtype_id == 0xFFFFFFFF ):
[348]	2379	print '[genmap error] in Irq.cbin() : undefined irqtype %s' % self.irqtype
[319]	2380	sys.exit(1)
[305]	2381
[319]	2382	# compute numerical value for isrtype
	2383	isrtype_id = 0xFFFFFFFF
	2384	for x in xrange( len(ISRTYPES) ):
	2385	if ( self.isrtype == ISRTYPES[x] ):
	2386	isrtype_id = x
	2387	if ( isrtype_id == 0xFFFFFFFF ):
[348]	2388	print '[genmap error] in Irq.cbin() : undefined isrtype %s' % self.isrtype
[319]	2389	sys.exit(1)
	2390
	2391	byte_stream = bytearray()
	2392	byte_stream += mapping.int2bytes( 4, irqtype_id )
	2393	byte_stream += mapping.int2bytes( 4, self.srcid )
	2394	byte_stream += mapping.int2bytes( 4, isrtype_id )
	2395	byte_stream += mapping.int2bytes( 4, self.channel )
	2396	byte_stream += mapping.int2bytes( 4, 0 )
	2397	byte_stream += mapping.int2bytes( 4, 0 )
	2398
	2399	if ( verbose ):
	2400	print 'irqtype = %s' % self.irqtype
	2401	print 'srcid = %d' % self.srcid
	2402	print 'isrtype = %s' % self.isrtype
	2403	print 'channel = %d' % self.channel
	2404
	2405	return byte_stream
	2406
	2407	###########################################################################################
	2408	class Coproc ( object ):
	2409	###########################################################################################
	2410	def __init__( self,
	2411	pseg ): # associated pseg
	2412
	2413	self.index = 0 # global index value set by addCoproc()
	2414	self.pseg = pseg
	2415	self.ports = []
	2416
[305]	2417	return
	2418
[319]	2419	################
	2420	def xml( self ): # xml for Coproc
[305]	2421
[348]	2422	print '[genmap error] in Coproc.xml() : not defined yet'
[319]	2423	sys.exit(1)
	2424
	2425	return
	2426
	2427	#############################################
	2428	def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc
	2429
	2430	if ( verbose ):
	2431	print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y)
	2432
	2433	# check index
	2434	if (self.index != expected):
[348]	2435	print '[genmap error] in Coproc.cbin() : coproc global index = %d / expected = %d' \
[319]	2436	% (self.index, expected )
	2437	sys.exit(1)
	2438
	2439	# compute pseg global index
	2440	pseg_id = self.pseg.index
	2441
	2442	# compute first port global index
	2443	port_id = self.ports[0].index
	2444
	2445	byte_stream = bytearray()
	2446	byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG)
	2447	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
	2448	byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs
	2449	byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index
	2450
	2451	if ( verbose ):
	2452	print 'irqtype = %s' % self.irqtype
	2453	print 'pseg_id = %d' % pseg_id
	2454	print 'nb_ports = %d' % len( self.ports )
	2455	print 'port_id %d' % port_id
	2456
	2457	return byte_stream
	2458
	2459	###########################################################################################
	2460	class Cpport ( object ):
	2461	###########################################################################################
	2462	def __init__( self,
	2463	direction,
	2464	vspacename,
	2465	mwmrname ):
	2466
	2467	self.index = 0 # global index ( set by addCpport() )
	2468	self.direction = direction # TO_COPROC / FROM_COPROC
	2469	self.vspacename = vspacename # name of vspace containing mwmr channel
	2470	self.mwmrname = mwmrname # name of vobj defining mwmr channel
	2471
[305]	2472	return
	2473
[319]	2474	################
	2475	def xml( self ): # xml for Cpport
[305]	2476
[348]	2477	print '[genmap error] in Cpport.xml() : not defined yet'
[319]	2478	sys.exit(1)
[305]	2479
[319]	2480	return
	2481
	2482	#############################################
	2483	def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport
	2484
	2485	if ( verbose ):
	2486	print '*** cbin for cpport[%d]' % (self.index)
	2487
	2488	# check index
	2489	if ( self.index != expected ):
[348]	2490	print '[genmap error] in Cpport.cbin() : port global index = %d / expected = %d' \
[319]	2491	% ( self.index, expected )
	2492	sys.exit(1)
	2493
	2494	# compute numerical value for direction
	2495	if ( self.direction == 'TO_COPROC' ):
	2496	dir_int = 0
	2497	else:
	2498	dir_int = 1
	2499
	2500	# compute vspace global index
	2501	vspace_id = 0xFFFFFFFF
	2502	for vspace in mapping.vspaces:
	2503	if ( self.vspacename == vspace.name ):
	2504	vspace_id = vspace.index
	2505	if (vspace_id == 0xFFFFFFFF):
[348]	2506	print '[genmap error] in Cpport.cbin() : vspace name %s not found' \
[319]	2507	% ( self.vspacename )
	2508	sys.exit(1)
	2509
	2510	# compute mwmr global index
	2511	mwmr_id = 0xFFFFFFFF
	2512	for vseg in mapping.vspace[vspace_id].vsegs:
	2513	for vobj in vseg.vobjs:
	2514	if (self.mwmrname == vobj.name):
	2515	mwmr_id = vobj.index
	2516	if (mwmr_id == 0xFFFFFFFF):
[348]	2517	print '[genmap error] in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \
[319]	2518	% ( self.mwmrname, self.vspacename )
	2519	sys.exit(1)
	2520
	2521	byte_stream = bytearray()
	2522	byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index
	2523	byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index
	2524	byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index
	2525
	2526	if ( verbose ):
	2527	print 'direction = %s' % self.direction
	2528	print 'vspace_id = %d' % vspace_id
	2529	print 'mwmr_id = %d' % mwmr_id
	2530
	2531	return byte_stream
	2532
	2533
[305]	2534	# Local Variables:
	2535	# tab-width: 4;
	2536	# c-basic-offset: 4;
	2537	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	2538	# indent-tabs-mode: nil;
	2539	# End:
	2540	#
	2541	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	2542

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