[81] | 1 | #ifndef ENVIRONMENT_PARAMETERS_H |
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| 2 | #define ENVIRONMENT_PARAMETERS_H |
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| 3 | |
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| 4 | #include "../Cache/include/Cache_Parameters.h" |
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| 5 | #include "../Data/include/Data_Parameters.h" |
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| 6 | #include "../Queue/include/Parameters.h" |
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| 7 | #include "../TTY/include/TTY_Parameters.h" |
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| 8 | #include "../RamLock/include/RamLock_Parameters.h" |
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| 9 | #include "../Sim2OS/include/Sim2OS_Parameters.h" |
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[88] | 10 | #include "../../processor/Morpheo/Common/include/ToString.h" |
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[81] | 11 | |
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| 12 | namespace environment { |
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| 13 | |
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| 14 | class Parameters |
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| 15 | { |
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[88] | 16 | public : uint32_t nb_iport ; |
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| 17 | public : uint32_t nb_dport ; |
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| 18 | public : uint32_t nb_entity ; |
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| 19 | public : uint32_t * icache_dedicated_nb_port; //[nb_entity] |
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| 20 | public : uint32_t * dcache_dedicated_nb_port; //[nb_entity] |
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| 21 | |
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| 22 | public : uint32_t * iaccess_nb_context ; //[nb_entity] |
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| 23 | public : uint32_t * iaccess_nb_packet ; //[nb_entity] |
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| 24 | public : uint32_t * iaccess_size_address ; //[nb_entity] |
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| 25 | public : uint32_t * iaccess_nb_instruction ; //[nb_entity] |
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| 26 | public : uint32_t * iaccess_size_instruction; //[nb_entity] |
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| 27 | |
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| 28 | public : uint32_t * daccess_nb_context ; //[nb_entity] |
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| 29 | public : uint32_t * daccess_nb_packet ; //[nb_entity] |
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| 30 | public : uint32_t * daccess_size_address ; //[nb_entity] |
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| 31 | public : uint32_t * daccess_size_data ; //[nb_entity] |
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[81] | 32 | |
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| 33 | // Parameters cache |
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[88] | 34 | public : cache::Parameters * param_cache ; |
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[81] | 35 | // Parameters tty |
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[88] | 36 | public : uint32_t nb_component_tty ; |
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| 37 | public : uint32_t * tty_address ; //[nb_component_tty] |
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| 38 | public : tty::Parameters ** param_tty ; //[nb_component_tty] |
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[81] | 39 | // Parameters ramlock |
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[88] | 40 | public : uint32_t nb_component_ramlock ; |
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| 41 | public : uint32_t * ramlock_address ; //[nb_component_ramlock] |
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| 42 | public : ramlock::Parameters ** param_ramlock ; //[nb_component_ramlock] |
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[81] | 43 | // Parameters sim2OS |
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[88] | 44 | public : uint32_t sim2os_address ; |
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| 45 | public : uint32_t sim2os_size ; |
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| 46 | public : sim2os::Parameters * param_sim2os ; |
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[81] | 47 | // Parameters data |
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[88] | 48 | public : data::Parameters * param_data ; |
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[81] | 49 | |
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| 50 | // Parameters buffer_respons |
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[88] | 51 | public : queue::Parameters ** param_buffer_irsp ; //[nb_entity] |
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| 52 | public : queue::Parameters ** param_buffer_drsp ; //[nb_entity] |
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[81] | 53 | |
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| 54 | public : Parameters (// General |
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| 55 | uint32_t nb_cache_dedicated, |
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| 56 | |
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| 57 | uint32_t * iaccess_nb_context, |
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| 58 | uint32_t * iaccess_nb_instruction, |
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| 59 | uint32_t * iaccess_nb_packet, |
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| 60 | uint32_t * iaccess_size_address, |
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| 61 | uint32_t * iaccess_size_instruction, |
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| 62 | |
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| 63 | uint32_t * daccess_nb_context, |
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| 64 | uint32_t * daccess_nb_packet, |
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| 65 | uint32_t * daccess_size_address, |
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| 66 | uint32_t * daccess_size_data, |
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| 67 | |
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| 68 | // buffer |
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| 69 | uint32_t * buffer_irsp_size, |
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| 70 | uint32_t * buffer_drsp_size, |
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| 71 | |
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| 72 | // Cache |
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| 73 | uint32_t * icache_dedicated_nb_level , |
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| 74 | uint32_t * icache_dedicated_nb_port , |
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| 75 | uint32_t ** icache_dedicated_nb_line , |
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| 76 | uint32_t ** icache_dedicated_size_line , |
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| 77 | uint32_t ** icache_dedicated_size_word , |
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| 78 | uint32_t ** icache_dedicated_associativity, |
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| 79 | uint32_t ** icache_dedicated_hit_latence , |
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| 80 | uint32_t ** icache_dedicated_miss_penality, |
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| 81 | uint32_t * dcache_dedicated_nb_level , |
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| 82 | uint32_t * dcache_dedicated_nb_port , |
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| 83 | uint32_t ** dcache_dedicated_nb_line , |
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| 84 | uint32_t ** dcache_dedicated_size_line , |
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| 85 | uint32_t ** dcache_dedicated_size_word , |
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| 86 | uint32_t ** dcache_dedicated_associativity, |
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| 87 | uint32_t ** dcache_dedicated_hit_latence , |
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| 88 | uint32_t ** dcache_dedicated_miss_penality, |
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| 89 | uint32_t cache_shared_nb_level , |
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| 90 | // uint32_t cache_shared_nb_port , |
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| 91 | uint32_t * cache_shared_nb_line , |
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| 92 | uint32_t * cache_shared_size_line , |
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| 93 | uint32_t * cache_shared_size_word , |
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| 94 | uint32_t * cache_shared_associativity , |
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| 95 | uint32_t * cache_shared_hit_latence , |
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| 96 | uint32_t * cache_shared_miss_penality , |
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| 97 | |
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| 98 | // TTY |
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| 99 | uint32_t nb_component_tty, |
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| 100 | uint32_t * tty_address, |
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| 101 | uint32_t * nb_tty, |
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| 102 | std::string ** name_tty, |
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| 103 | bool with_xtty, |
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| 104 | |
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| 105 | // RAMLOCK |
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| 106 | uint32_t nb_component_ramlock, |
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| 107 | uint32_t * ramlock_address, |
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| 108 | uint32_t * nb_lock, |
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| 109 | |
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| 110 | // SIM2OS |
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| 111 | uint32_t sim2os_address, |
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| 112 | uint32_t sim2os_size, |
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| 113 | SOCLIB_SEGMENT_TABLE * segment_table |
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| 114 | ) |
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| 115 | { |
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| 116 | this->nb_entity = nb_cache_dedicated; |
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| 117 | |
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| 118 | this->icache_dedicated_nb_port = icache_dedicated_nb_port; |
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| 119 | this->dcache_dedicated_nb_port = dcache_dedicated_nb_port; |
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| 120 | |
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| 121 | this->iaccess_nb_context = iaccess_nb_context ; |
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| 122 | this->iaccess_nb_instruction = iaccess_nb_instruction ; |
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| 123 | this->iaccess_nb_packet = iaccess_nb_packet ; |
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| 124 | this->iaccess_size_address = iaccess_size_address ; |
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| 125 | this->iaccess_size_instruction = iaccess_size_instruction; |
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| 126 | this->daccess_nb_context = daccess_nb_context ; |
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| 127 | this->daccess_nb_packet = daccess_nb_packet ; |
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| 128 | this->daccess_size_address = daccess_size_address ; |
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| 129 | this->daccess_size_data = daccess_size_data ; |
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| 130 | |
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| 131 | param_cache = new cache::Parameters |
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| 132 | (nb_cache_dedicated , |
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| 133 | icache_dedicated_nb_level , |
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| 134 | icache_dedicated_nb_port , |
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| 135 | icache_dedicated_nb_line , |
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| 136 | icache_dedicated_size_line , |
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| 137 | icache_dedicated_size_word , |
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| 138 | icache_dedicated_associativity, |
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| 139 | icache_dedicated_hit_latence , |
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| 140 | icache_dedicated_miss_penality, |
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| 141 | dcache_dedicated_nb_level , |
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| 142 | dcache_dedicated_nb_port , |
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| 143 | dcache_dedicated_nb_line , |
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| 144 | dcache_dedicated_size_line , |
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| 145 | dcache_dedicated_size_word , |
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| 146 | dcache_dedicated_associativity, |
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| 147 | dcache_dedicated_hit_latence , |
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| 148 | dcache_dedicated_miss_penality, |
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| 149 | cache_shared_nb_level , |
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| 150 | // cache_shared_nb_port , |
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| 151 | cache_shared_nb_line , |
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| 152 | cache_shared_size_line , |
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| 153 | cache_shared_size_word , |
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| 154 | cache_shared_associativity , |
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| 155 | cache_shared_hit_latence , |
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| 156 | cache_shared_miss_penality |
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| 157 | ); |
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| 158 | |
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| 159 | nb_iport = 0; |
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| 160 | nb_dport = 0; |
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| 161 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
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| 162 | { |
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| 163 | nb_iport += icache_dedicated_nb_port [i]; |
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| 164 | nb_dport += dcache_dedicated_nb_port [i]; |
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| 165 | } |
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| 166 | |
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| 167 | this->nb_component_tty = nb_component_tty; |
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| 168 | this->tty_address = tty_address; |
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| 169 | |
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| 170 | param_tty = new tty::Parameters * [nb_component_tty]; |
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| 171 | for (uint32_t i=0; i<nb_component_tty; i++) |
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| 172 | { |
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| 173 | uint32_t tty_size = nb_tty [i] * 16; // 4 32bit-register by tty |
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| 174 | |
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| 175 | // std::ostringstream str(""); |
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| 176 | // str << "tty_" << i; |
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| 177 | segment_table->addSegment("tty",tty_address[i],tty_size,0,0,true); |
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| 178 | |
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| 179 | param_tty [i] = new tty::Parameters (nb_tty [i], |
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| 180 | name_tty [i], |
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| 181 | with_xtty ); |
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| 182 | } |
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| 183 | |
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| 184 | this->nb_component_ramlock = nb_component_ramlock; |
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| 185 | this->ramlock_address = ramlock_address; |
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| 186 | |
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| 187 | param_ramlock = new ramlock::Parameters * [nb_component_ramlock]; |
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| 188 | for (uint32_t i=0; i<nb_component_ramlock; i++) |
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| 189 | { |
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| 190 | uint32_t ramlock_size = nb_lock[i]; // registre 8 bits because it's min size access |
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| 191 | // std::ostringstream str (""); |
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| 192 | // str << "ramlock" << i; |
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| 193 | segment_table->addSegment("ramlock",ramlock_address[i],ramlock_size,0,0,true); |
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| 194 | |
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| 195 | param_ramlock [i] = new ramlock::Parameters (nb_lock [i]); |
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| 196 | } |
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| 197 | |
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| 198 | this->sim2os_address = sim2os_address ; |
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| 199 | this->sim2os_size = sim2os_size ; |
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| 200 | |
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| 201 | segment_table->addSegment("sim2os",sim2os_address,sim2os_size,0,0,true); |
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| 202 | param_sim2os = new sim2os::Parameters (segment_table); |
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| 203 | |
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| 204 | param_data = new data::Parameters (16,0,0, segment_table); |
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| 205 | |
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| 206 | param_buffer_irsp = new queue::Parameters * [nb_entity]; |
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| 207 | for (uint32_t i=0; i<nb_entity; i++) |
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| 208 | param_buffer_irsp [i] = new queue::Parameters (buffer_irsp_size [i]); |
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| 209 | |
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| 210 | param_buffer_drsp = new queue::Parameters * [nb_entity]; |
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| 211 | for (uint32_t i=0; i<nb_entity; i++) |
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| 212 | param_buffer_drsp [i] = new queue::Parameters (buffer_drsp_size [i]); |
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| 213 | } |
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| 214 | |
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| 215 | public : ~Parameters (void) |
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| 216 | { |
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| 217 | for (uint32_t i=0; i<nb_entity; i++) |
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| 218 | delete param_buffer_irsp [i]; |
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| 219 | delete [] param_buffer_irsp; |
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| 220 | |
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| 221 | for (uint32_t i=0; i<nb_entity; i++) |
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| 222 | delete param_buffer_drsp [i]; |
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| 223 | delete [] param_buffer_drsp; |
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| 224 | |
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| 225 | delete param_data ; |
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| 226 | delete param_sim2os; |
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| 227 | for (uint32_t i=0; i<nb_component_ramlock; i++) |
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| 228 | delete param_ramlock [i]; |
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| 229 | delete [] param_ramlock; |
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| 230 | for (uint32_t i=0; i<nb_component_tty; i++) |
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| 231 | delete param_tty [i]; |
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| 232 | delete [] param_tty; |
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| 233 | delete param_cache; |
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| 234 | } |
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[88] | 235 | |
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| 236 | public : std::string print (uint32_t depth) |
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| 237 | { |
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| 238 | std::string tab = std::string(depth,'\t'); |
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| 239 | std::string str = ""; |
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| 240 | |
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| 241 | str+=tab+"nb_entity : "+morpheo::toString(nb_entity)+"\n"; |
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| 242 | str+=tab+"nb_iport : "+morpheo::toString(nb_iport )+"\n"; |
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| 243 | str+=tab+"nb_dport : "+morpheo::toString(nb_dport )+"\n"; |
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| 244 | for (uint32_t i=0; i<nb_entity; ++i) |
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| 245 | { |
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| 246 | str+=tab+"ENTITY ["+morpheo::toString(i)+"]\n"; |
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| 247 | str+=tab+" * icache_dedicated_nb_port : "+morpheo::toString(icache_dedicated_nb_port[i])+"\n"; |
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| 248 | str+=tab+" * dcache_dedicated_nb_port : "+morpheo::toString(dcache_dedicated_nb_port[i])+"\n"; |
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| 249 | str+=tab+" * iaccess_nb_context : "+morpheo::toString(iaccess_nb_context [i])+"\n"; |
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| 250 | str+=tab+" * iaccess_nb_packet : "+morpheo::toString(iaccess_nb_packet [i])+"\n"; |
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| 251 | str+=tab+" * iaccess_size_address : "+morpheo::toString(iaccess_size_address [i])+"\n"; |
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| 252 | str+=tab+" * iaccess_nb_instruction : "+morpheo::toString(iaccess_nb_instruction [i])+"\n"; |
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| 253 | str+=tab+" * iaccess_size_instruction : "+morpheo::toString(iaccess_size_instruction[i])+"\n"; |
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| 254 | str+=tab+" * daccess_nb_context : "+morpheo::toString(daccess_nb_context [i])+"\n"; |
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| 255 | str+=tab+" * daccess_nb_packet : "+morpheo::toString(daccess_nb_packet [i])+"\n"; |
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| 256 | str+=tab+" * daccess_size_address : "+morpheo::toString(daccess_size_address [i])+"\n"; |
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| 257 | str+=tab+" * daccess_size_data : "+morpheo::toString(daccess_size_data [i])+"\n"; |
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| 258 | } |
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| 259 | |
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| 260 | str+=tab+"CACHE\n"; |
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| 261 | str+=param_cache->print(depth+1); |
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| 262 | |
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| 263 | // str+=tab+"nb_component_tty : "+morpheo::toString(nb_component_tty )+"\n"; |
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| 264 | // for (uint32_t i=0; i<nb_component_tty; ++i) |
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| 265 | // { |
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| 266 | // str+=tab+"TTY ["+morpheo::toString(i)+"]\n"; |
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| 267 | // str+=tab+" * tty_address : "+morpheo::toString(tty_address [i])+"\n"; |
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| 268 | // str+=param_tty->print(depth+1); |
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| 269 | // } |
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| 270 | |
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| 271 | // str+=tab+"nb_component_ramlock : "+morpheo::toString(nb_component_ramlock )+"\n"; |
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| 272 | // for (uint32_t i=0; i<nb_component_ramlock; ++i) |
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| 273 | // { |
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| 274 | // str+=tab+"RAMLOCK ["+morpheo::toString(i)+"]\n"; |
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| 275 | // str+=tab+" * ramlock_address : "+morpheo::toString(ramlock_address [i])+"\n"; |
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| 276 | // str+=param_ramlock->print(depth+1); |
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| 277 | // } |
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| 278 | |
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| 279 | // str+=tab+"SIM2OS\n"; |
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| 280 | // str+=tab+"sim2os_address : "+morpheo::toString(sim2os_address)+"\n"; |
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| 281 | // str+=tab+"sim2os_size : "+morpheo::toString(sim2os_size )+"\n"; |
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| 282 | // str+=param_sim2os->print(depth+1); |
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| 283 | |
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| 284 | // str+=tab+"DATA\n"; |
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| 285 | // str+=param_data->print(depth+1); |
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| 286 | |
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| 287 | // for (uint32_t i=0; i<nb_entity; ++i) |
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| 288 | // { |
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| 289 | // str+=tab+"BUFFER_IRSP ["+morpheo::toString(i)+"]\n"; |
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| 290 | // str+=param_buffer_irsp[i]_data->print(depth+1); |
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| 291 | // } |
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| 292 | |
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| 293 | // for (uint32_t i=0; i<nb_entity; ++i) |
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| 294 | // { |
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| 295 | // str+=tab+"BUFFER_DRSP ["+morpheo::toString(i)+"]\n"; |
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| 296 | // str+=param_buffer_drsp[i]_data->print(depth+1); |
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| 297 | // } |
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| 298 | |
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| 299 | return str; |
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| 300 | } |
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| 301 | |
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| 302 | // public : friend std::ostream& operator<< (std::ostream& output, const Parameters &x) |
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| 303 | // { |
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| 304 | // x.print(0); |
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| 305 | // return output; |
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| 306 | // } |
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[81] | 307 | }; |
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| 308 | |
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| 309 | }; |
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| 310 | #endif |
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