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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 13.9 KB

Rev	Line
[59]	1	#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Load_store_unit_h
	2	#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Load_store_unit_h
	3
	4	/*
	5	* $Id: Load_store_unit.h 88 2008-12-10 18:31:39Z rosiere $
	6	*
[78]	7	* [ Description ]
[59]	8	*
[62]	9	* Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit
[59]	10	*/
	11
	12	#ifdef SYSTEMC
	13	#include "systemc.h"
	14	#endif
	15
	16	#include <iostream>
	17	#include "Common/include/ToString.h"
	18	#include "Common/include/Debug.h"
	19
	20	#include "Behavioural/Generic/Queue_Control/include/Queue_Control.h"
	21
	22	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h"
	23	#include "Behavioural/Generic/Queue_Control/include/Queue_Control.h"
	24	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
	25	#ifdef STATISTICS
[71]	26	#include "Behavioural/include/Stat.h"
[59]	27	#endif
	28	#include "Behavioural/include/Component.h"
	29	#ifdef VHDL
	30	#include "Behavioural/include/Vhdl.h"
	31	#endif
[82]	32	#include "Behavioural/include/Usage.h"
[59]	33
	34	namespace morpheo {
	35	namespace behavioural {
	36	namespace core {
	37	namespace multi_execute_loop {
	38	namespace execute_loop {
	39	namespace multi_execute_unit {
	40	namespace execute_unit {
	41	namespace load_store_unit {
	42
	43
	44	class Load_store_unit
	45	#if SYSTEMC
	46	: public sc_module
	47	#endif
	48	{
[78]	49	// -----[ fields ]----------------------------------------------------
[59]	50	// Parameters
[82]	51	protected : const std::string _name;
[59]	52	protected : const Parameters * _param;
[82]	53	private : const Tusage_t _usage;
[59]	54
	55	#ifdef STATISTICS
[78]	56	public : Stat * _stat;
[71]	57
	58	private : counter_t * _stat_use_store_queue;
	59	private : counter_t * _stat_use_load_queue;
	60	private : counter_t * _stat_use_speculative_access_queue;
	61
	62	private : counter_t * _stat_average_use_store_queue;
	63	private : counter_t * _stat_average_use_load_queue;
	64	private : counter_t * _stat_average_use_speculative_access_queue;
	65
	66	private : counter_t * _stat_percent_use_store_queue;
	67	private : counter_t * _stat_percent_use_load_queue;
	68	private : counter_t * _stat_percent_use_speculative_access_queue;
	69
	70	// private : counter_t * _stat_nb_load_miss_speculation;
	71	// private : counter_t * _stat_nb_head_ko;
	72
	73	// private : counter_t * _stat_nb_inst_load;
	74	// private : counter_t * _stat_nb_inst_store;
	75	// private : counter_t * _stat_nb_inst_lock;
	76	// private : counter_t * _stat_nb_inst_prefetch;
	77	// private : counter_t * _stat_nb_inst_invalid;
	78	// private : counter_t * _stat_nb_inst_flush;
	79	// private : counter_t * _stat_nb_inst_sync;
[59]	80	#endif
	81
	82	public : Component * _component;
	83	private : Interfaces * _interfaces;
	84
	85	#ifdef SYSTEMC
[78]	86	// ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	87	// Interface
	88	public : SC_CLOCK * in_CLOCK ;
	89	public : SC_IN (Tcontrol_t) * in_NRESET ;
	90
[78]	91	// ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[88]	92	public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_VAL ;//[nb_inst_memory]
	93	public : SC_OUT(Tcontrol_t ) ** out_MEMORY_IN_ACK ;//[nb_inst_memory]
	94	public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_CONTEXT_ID ;//[nb_inst_memory]
	95	public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_FRONT_END_ID ;//[nb_inst_memory]
	96	public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_OOO_ENGINE_ID ;//[nb_inst_memory]
	97	public : SC_IN (Tpacket_t ) ** in_MEMORY_IN_PACKET_ID ;//[nb_inst_memory]
	98	public : SC_IN (Toperation_t ) ** in_MEMORY_IN_OPERATION ;//[nb_inst_memory]
	99	public : SC_IN (Ttype_t ) ** in_MEMORY_IN_TYPE ;//[nb_inst_memory]
	100	public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory]
	101	public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory]
	102	public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_HAS_IMMEDIAT ;//[nb_inst_memory]
	103	public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_IMMEDIAT ;//[nb_inst_memory] // memory address
	104	public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RA ;//[nb_inst_memory] // memory address
	105	public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RB ;//[nb_inst_memory] // data (store)
	106	public : SC_IN (Tspecial_data_t ) ** in_MEMORY_IN_DATA_RC ;//[nb_inst_memory]
	107	public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RD ;//[nb_inst_memory] // = (operation==load)
	108	public : SC_IN (Tgeneral_address_t) ** in_MEMORY_IN_NUM_REG_RD ;//[nb_inst_memory] // destination (load)
	109	public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RE ;//[nb_inst_memory]
	110	public : SC_IN (Tspecial_address_t) ** in_MEMORY_IN_NUM_REG_RE ;//[nb_inst_memory]
[59]	111
[78]	112	// ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[88]	113	public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_VAL ;//[nb_inst_memory]
	114	public : SC_IN (Tcontrol_t ) ** in_MEMORY_OUT_ACK ;//[nb_inst_memory]
	115	public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_CONTEXT_ID ;//[nb_inst_memory]
	116	public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_FRONT_END_ID ;//[nb_inst_memory]
	117	public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_OOO_ENGINE_ID ;//[nb_inst_memory]
	118	public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory]
	119	//public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory]
	120	public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory]
	121	public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load)
	122	public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load)
	123	public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_DATA_RD ;//[nb_inst_memory] // data (load)
	124	public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RE ;//[nb_inst_memory]
	125	public : SC_OUT(Tspecial_address_t) ** out_MEMORY_OUT_NUM_REG_RE ;//[nb_inst_memory]
	126	public : SC_OUT(Tspecial_data_t ) ** out_MEMORY_OUT_DATA_RE ;//[nb_inst_memory]
	127	public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory]
	128	public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory]
	129	public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory]
[78]	130
	131	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[88]	132	public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_cache_port]
	133	public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_cache_port]
	134	public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_CONTEXT_ID ;//[nb_cache_port]
	135	public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_cache_port]
	136	public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_cache_port]
	137	public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_cache_port]
	138	public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_cache_port]
[59]	139
[78]	140	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[88]	141	public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_cache_port]
	142	public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_cache_port]
	143	public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_CONTEXT_ID ;//[nb_cache_port]
	144	public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_cache_port]
	145	public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_cache_port]
	146	public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_cache_port]
[59]	147
[78]	148	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[88]	149	public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; //[nb_bypass_memory]
	150	public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; //[nb_bypass_memory]
	151	public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; //[nb_bypass_memory]
	152	public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; //[nb_bypass_memory]
[59]	153
[78]	154	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	155	protected : Tstore_queue_entry_t * _store_queue;
	156	protected : Tload_queue_entry_t * _load_queue;
	157	protected : Tspeculative_access_queue_entry_t * _speculative_access_queue;
	158	protected : morpheo::behavioural::generic::queue_control::Queue_Control * _speculative_access_queue_control;
	159
	160	// function pointer
	161	public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_transition ) (void);
	162	public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMoore ) (void);
	163	public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_dcache) (void);
	164	public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_insert) (void);
	165	public : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_retire) (void);
	166
[78]	167	// ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	168
[78]	169	// ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]	170
[62]	171	// Registers
[71]	172	public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ;
	173	//public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ;
	174	public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY ;
[59]	175
[62]	176	// signal
[71]	177	public : Tlsq_ptr_t internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ;
[88]	178
	179	private : Tcontrol_t internal_MEMORY_IN_ACK ;
	180	private : uint32_t internal_MEMORY_IN_PORT ;
[71]	181
[88]	182	private : Tcontrol_t internal_MEMORY_OUT_VAL ;
[59]	183	private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE;
[88]	184	private : Tlsq_ptr_t internal_MEMORY_OUT_PTR ;
	185
	186	private : Tcontrol_t internal_DCACHE_RSP_ACK ;
	187	private : Tcontrol_t internal_DCACHE_REQ_VAL ;
[62]	188	private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE;
[59]	189	#endif
	190
[78]	191	// -----[ methods ]---------------------------------------------------
[59]	192
	193	#ifdef SYSTEMC
	194	SC_HAS_PROCESS (Load_store_unit);
	195	#endif
	196	public : Load_store_unit
	197	(
	198	#ifdef SYSTEMC
	199	sc_module_name name,
	200	#else
[75]	201	std::string name,
[59]	202	#endif
	203	#ifdef STATISTICS
	204	morpheo::behavioural::Parameters_Statistics * param_statistics,
	205	#endif
[82]	206	Parameters * param,
	207	morpheo::behavioural::Tusage_t usage );
[59]	208	public : ~Load_store_unit (void);
	209
	210	#ifdef SYSTEMC
	211	private : void allocation (void);
	212	private : void deallocation (void);
	213
	214	public : void transition (void);
	215	public : void genMoore (void);
	216	public : void genMealy_dcache (void);
	217	public : void genMealy_insert (void);
	218	public : void genMealy_retire (void);
	219
	220	public : void function_speculative_load_commit_transition (void);
	221	public : void function_speculative_load_commit_genMoore (void);
	222	public : void function_speculative_load_commit_genMealy_dcache (void);
	223	public : void function_speculative_load_commit_genMealy_insert (void);
	224	public : void function_speculative_load_commit_genMealy_retire (void);
	225	#endif
[71]	226
[59]	227	#ifdef STATISTICS
[71]	228	public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics);
[59]	229	#endif
	230
	231	#if VHDL
	232	public : void vhdl (void);
	233	private : void vhdl_declaration (Vhdl * & vhdl);
	234	private : void vhdl_body (Vhdl * & vhdl);
	235	#endif
	236
[71]	237	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
	238	private : void end_cycle (void);
[59]	239	#endif
	240	};
	241
	242	}; // end namespace load_store_unit
	243	}; // end namespace execute_unit
	244	}; // end namespace multi_execute_unit
	245	}; // end namespace execute_loop
	246	}; // end namespace multi_execute_loop
	247	}; // end namespace core
	248
	249	}; // end namespace behavioural
	250	}; // end namespace morpheo
	251
	252	#endif

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