[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_genMoore.cpp 123 2009-06-08 20:43:30Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Context_State::genMoore" |
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| 21 | void Context_State::genMoore (void) |
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| 22 | { |
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| 23 | log_begin(Context_State,FUNCTION); |
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[88] | 24 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 25 | |
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[123] | 26 | if (PORT_READ(in_NRESET)) |
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| 27 | { |
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[83] | 28 | // ------------------------------------------------------------------- |
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| 29 | // -----[ EVENT ]----------------------------------------------------- |
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| 30 | // ------------------------------------------------------------------- |
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| 31 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 32 | { |
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| 33 | context_state_t state = reg_STATE [i]; |
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| 34 | |
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[105] | 35 | Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or |
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| 36 | (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or |
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[111] | 37 | (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR) or |
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[105] | 38 | (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or |
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| 39 | (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or |
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[88] | 40 | (state == CONTEXT_STATE_KO_CSYNC_ADDR)); |
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| 41 | |
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| 42 | // SR can't change in this cycle |
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| 43 | // Exception Prefix High |
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[97] | 44 | Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); |
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| 45 | Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; |
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[105] | 46 | Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); |
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| 47 | Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); |
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[83] | 48 | // excep : address exception |
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| 49 | // miss : address delay_slot, and address dest |
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| 50 | // psync : address next |
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| 51 | // csync : address next |
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[97] | 52 | Tevent_type_t type ;//[nb_context] |
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| 53 | Tdepth_t depth = reg_EVENT_DEPTH [i]; |
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[119] | 54 | Tcontrol_t flush_only = reg_EVENT_FLUSH_ONLY [i]; |
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[97] | 55 | |
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| 56 | switch (state) |
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| 57 | { |
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[105] | 58 | case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; |
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[111] | 59 | case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR: |
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[105] | 60 | case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; |
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| 61 | case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; |
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| 62 | case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; |
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| 63 | case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; |
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| 64 | default : (type = EVENT_TYPE_NONE ); break; |
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[97] | 65 | } |
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| 66 | // (type = EVENT_TYPE_SPR_ACCESS ); |
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| 67 | // (type = EVENT_TYPE_MSYNC ); |
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| 68 | // (type = EVENT_TYPE_BRANCH_NO_ACCURATE); |
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| 69 | |
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[88] | 70 | internal_EVENT_VAL [i] = val; |
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| 71 | PORT_WRITE(out_EVENT_ADDRESS [i], address); |
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| 72 | PORT_WRITE(out_EVENT_ADDRESS_NEXT [i], address_next); |
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| 73 | PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val); |
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| 74 | PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take); |
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[97] | 75 | PORT_WRITE(out_EVENT_TYPE [i], type); |
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| 76 | if (_param->_have_port_depth) |
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| 77 | PORT_WRITE(out_EVENT_DEPTH [i], depth); |
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[119] | 78 | PORT_WRITE(out_EVENT_FLUSH_ONLY [i], flush_only); |
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[88] | 79 | |
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| 80 | log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i); |
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| 81 | log_printf(TRACE,Context_State,FUNCTION," * VAL : %d", val); |
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| 82 | log_printf(TRACE,Context_State,FUNCTION," * ADDRESS : %.8x (%.8x)", address , address <<2); |
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| 83 | log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)", address_next, address_next<<2); |
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| 84 | log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val); |
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| 85 | log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take); |
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[97] | 86 | log_printf(TRACE,Context_State,FUNCTION," * TYPE : %d", type); |
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| 87 | log_printf(TRACE,Context_State,FUNCTION," * DEPTH : %d", depth); |
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[119] | 88 | log_printf(TRACE,Context_State,FUNCTION," * FLUSH_ONLY : %d", flush_only); |
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[83] | 89 | } |
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| 90 | |
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| 91 | // ------------------------------------------------------------------- |
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[88] | 92 | // -----[ SPR_EVENT ]------------------------------------------------- |
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[83] | 93 | // ------------------------------------------------------------------- |
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| 94 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 95 | { |
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| 96 | context_state_t state = reg_STATE [i]; |
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| 97 | |
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[88] | 98 | internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR ); |
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[83] | 99 | |
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[88] | 100 | PORT_WRITE(out_SPR_EVENT_EPCR [i], reg_EVENT_ADDRESS_EPCR [i]); |
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| 101 | PORT_WRITE(out_SPR_EVENT_EEAR [i], reg_EVENT_ADDRESS_EEAR [i]); |
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| 102 | PORT_WRITE(out_SPR_EVENT_EEAR_WEN [i], reg_EVENT_ADDRESS_EEAR_VAL [i]); |
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| 103 | PORT_WRITE(out_SPR_EVENT_SR_DSX [i], reg_EVENT_IS_DELAY_SLOT [i]); |
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| 104 | PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1); |
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[83] | 105 | } |
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| 106 | |
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| 107 | // ------------------------------------------------------------------- |
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| 108 | // -----[ CONTEXT ]--------------------------------------------------- |
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| 109 | // ------------------------------------------------------------------- |
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| 110 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 111 | { |
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| 112 | context_state_t state = reg_STATE [i]; |
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| 113 | |
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[101] | 114 | // PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or |
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| 115 | // (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or |
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| 116 | // (state==CONTEXT_STATE_KO_SPR_ISSUE ))); |
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| 117 | PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK)); |
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[83] | 118 | } |
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[123] | 119 | } |
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| 120 | else |
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| 121 | { |
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| 122 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 123 | { |
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| 124 | internal_EVENT_VAL [i] = 0; |
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| 125 | internal_SPR_EVENT_VAL [i] = 0; |
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[83] | 126 | |
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[123] | 127 | PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], 0); |
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| 128 | } |
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| 129 | } |
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| 130 | |
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| 131 | // Write output |
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| 132 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 133 | { |
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| 134 | PORT_WRITE(out_EVENT_VAL [i], internal_EVENT_VAL [i]); |
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| 135 | PORT_WRITE(out_SPR_EVENT_VAL [i], internal_SPR_EVENT_VAL [i]); |
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| 136 | } |
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| 137 | |
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[83] | 138 | log_end(Context_State,FUNCTION); |
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| 139 | }; |
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| 140 | |
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| 141 | }; // end namespace context_state |
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| 142 | }; // end namespace front_end |
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| 143 | }; // end namespace multi_front_end |
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| 144 | }; // end namespace core |
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| 145 | |
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| 146 | }; // end namespace behavioural |
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| 147 | }; // end namespace morpheo |
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| 148 | #endif |
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