[83] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Context_State_transition.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace context_state { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Context_State::transition" |
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| 21 | void Context_State::transition (void) |
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| 22 | { |
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| 23 | log_begin(Context_State,FUNCTION); |
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[88] | 24 | log_function(Context_State,FUNCTION,_name.c_str()); |
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[83] | 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[88] | 28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 29 | { |
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| 30 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 31 | reg_INTERRUPT_ENABLE [i] = 0; |
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| 32 | } |
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[83] | 33 | } |
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| 34 | else |
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| 35 | { |
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[88] | 36 | // ------------------------------------------------------------------- |
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| 37 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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| 38 | // ------------------------------------------------------------------- |
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| 39 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 40 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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| 41 | { |
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| 42 | // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); |
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[83] | 43 | |
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[88] | 44 | context_state_t state = reg_STATE [i]; |
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[83] | 45 | |
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[88] | 46 | Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): |
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| 47 | 0; |
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| 48 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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| 49 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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| 50 | Tdepth_t depth_max = _param->_array_size_depth [i]; |
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| 51 | |
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| 52 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 53 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 54 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 55 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 56 | |
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[88] | 57 | // priority : miss > excep > spr/sync |
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| 58 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0); |
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| 59 | uint8_t priority1 = 2; // miss |
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[83] | 60 | |
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[88] | 61 | // is_valid = can modify local information |
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| 62 | // if context_state_ok : yes |
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| 63 | // if context_state_ko : test the depth, and the priority of envent |
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[83] | 64 | |
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[88] | 65 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 66 | (depth1< depth0) or |
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| 67 | ((depth1==depth0) and (priority1>priority0))); |
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[83] | 68 | |
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[88] | 69 | if (is_valid) |
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| 70 | { |
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| 71 | reg_STATE [i] = CONTEXT_STATE_KO_MISS; |
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| 72 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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| 73 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST[i]); // address_next |
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| 74 | reg_EVENT_ADDRESS_EPCR_VAL [i] = 1; // address_dest is valid |
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| 75 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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| 76 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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| 77 | reg_EVENT_IS_DELAY_SLOT [i] = 1; |
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| 78 | reg_EVENT_IS_DS_TAKE [i] = 0;// ?? |
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| 79 | reg_EVENT_DEPTH [i] = depth; |
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| 80 | } |
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| 81 | } |
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| 82 | |
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| 83 | // ------------------------------------------------------------------- |
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| 84 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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| 85 | // ------------------------------------------------------------------- |
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[83] | 86 | |
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[88] | 87 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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| 88 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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| 89 | { |
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| 90 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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| 91 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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| 92 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 93 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 94 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 95 | |
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| 96 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 97 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 98 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 99 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 100 | |
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[88] | 101 | context_state_t state = reg_STATE [context]; |
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| 102 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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| 103 | |
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| 104 | // miss > excep > spr/sync |
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| 105 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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| 106 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; |
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[83] | 107 | |
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[88] | 108 | // is_valid = can modify local information |
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| 109 | // if context_state_ok : yes |
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| 110 | // if context_state_ko : test the depth, and the priority of envent |
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[83] | 111 | |
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[88] | 112 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 113 | (depth1< depth0) or |
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| 114 | ((depth1==depth0) and (priority1>priority0))); |
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[83] | 115 | |
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[88] | 116 | if (is_valid) |
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| 117 | { |
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| 118 | // decod : |
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| 119 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
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| 120 | context_state_t state_next = state; |
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| 121 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
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| 122 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
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[83] | 123 | |
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[88] | 124 | switch (type) |
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| 125 | { |
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| 126 | case EVENT_TYPE_EXCEPTION : |
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| 127 | { |
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| 128 | state_next = CONTEXT_STATE_KO_EXCEP; |
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[83] | 129 | |
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[88] | 130 | break; |
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| 131 | } |
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| 132 | case EVENT_TYPE_SPR_ACCESS : |
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| 133 | { |
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| 134 | state_next = CONTEXT_STATE_KO_SPR ; |
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| 135 | address++; // take next address |
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| 136 | if (is_delay_slot) |
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| 137 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 138 | break; |
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| 139 | } |
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| 140 | case EVENT_TYPE_MSYNC : |
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| 141 | { |
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| 142 | state_next = CONTEXT_STATE_KO_MSYNC; |
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| 143 | address++; // take next address |
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| 144 | if (is_delay_slot) |
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| 145 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 146 | break; |
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| 147 | } |
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| 148 | case EVENT_TYPE_PSYNC : |
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| 149 | { |
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| 150 | state_next = CONTEXT_STATE_KO_PSYNC; |
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| 151 | address++; // take next address |
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| 152 | if (is_delay_slot) |
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| 153 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 154 | break; |
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| 155 | } |
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| 156 | case EVENT_TYPE_CSYNC : |
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| 157 | { |
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| 158 | state_next = CONTEXT_STATE_KO_CSYNC; |
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| 159 | address++; // take next address |
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| 160 | if (is_delay_slot) |
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| 161 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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| 162 | break; |
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| 163 | } |
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| 164 | case EVENT_TYPE_NONE : |
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| 165 | case EVENT_TYPE_MISS_SPECULATION : |
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| 166 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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| 167 | default : |
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| 168 | { |
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| 169 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
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| 170 | } |
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| 171 | } |
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[83] | 172 | |
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[88] | 173 | reg_STATE [context] = state_next; |
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| 174 | reg_EVENT_ADDRESS [context] = address; |
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| 175 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
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| 176 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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| 177 | //reg_EVENT_ADDRESS_EEAR [context] |
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| 178 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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| 179 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
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| 180 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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| 181 | reg_EVENT_DEPTH [context] = depth; |
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| 182 | } |
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| 183 | } |
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[83] | 184 | |
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[88] | 185 | // ------------------------------------------------------------------- |
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| 186 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
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| 187 | // ------------------------------------------------------------------- |
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[83] | 188 | |
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[88] | 189 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
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| 190 | { |
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| 191 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
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| 192 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
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| 193 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 194 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 195 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 196 | |
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| 197 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 198 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 199 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 200 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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[83] | 201 | |
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[88] | 202 | context_state_t state = reg_STATE [context]; |
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| 203 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
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| 204 | |
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| 205 | // miss > excep > spr/sync |
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| 206 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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| 207 | uint8_t priority1 = 1; // exception |
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| 208 | |
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| 209 | // is_valid = can modify local information |
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| 210 | // if context_state_ok : yes |
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| 211 | // if context_state_ko : test the depth, and the priority of envent |
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| 212 | |
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| 213 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 214 | (depth1< depth0) or |
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| 215 | ((depth1==depth0) and (priority1>priority0))); |
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| 216 | |
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| 217 | if (is_valid) |
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| 218 | { |
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| 219 | // commit |
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| 220 | // type : exception |
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| 221 | context_state_t state_next = state; |
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| 222 | switch (type) |
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| 223 | { |
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| 224 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
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| 225 | case EVENT_TYPE_SPR_ACCESS : |
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| 226 | case EVENT_TYPE_MSYNC : |
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| 227 | case EVENT_TYPE_PSYNC : |
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| 228 | case EVENT_TYPE_CSYNC : |
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| 229 | case EVENT_TYPE_NONE : |
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| 230 | case EVENT_TYPE_MISS_SPECULATION : |
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| 231 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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| 232 | default : |
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| 233 | { |
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| 234 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
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| 235 | } |
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| 236 | } |
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| 237 | reg_STATE [context] = state_next; |
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| 238 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
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| 239 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
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| 240 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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| 241 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
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| 242 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
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| 243 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
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| 244 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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| 245 | reg_EVENT_DEPTH [context] = depth; |
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| 246 | } |
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| 247 | } |
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| 248 | |
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| 249 | // ------------------------------------------------------------------- |
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| 250 | // -----[ BRANCH_COMPLETE ]------------------------------------------- |
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| 251 | // ------------------------------------------------------------------- |
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| 252 | |
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| 253 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 254 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) |
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| 255 | { |
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| 256 | if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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| 257 | { |
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| 258 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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| 259 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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| 260 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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| 261 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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| 262 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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| 263 | |
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| 264 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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| 265 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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| 266 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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| 267 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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| 268 | |
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| 269 | context_state_t state = reg_STATE [context]; |
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| 270 | |
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| 271 | // miss > excep > spr/sync |
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| 272 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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| 273 | uint8_t priority1 = 2; // miss |
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| 274 | |
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| 275 | // is_valid = can modify local information |
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| 276 | // if context_state_ok : yes |
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| 277 | // if context_state_ko : test the depth, and the priority of envent |
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| 278 | |
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| 279 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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| 280 | (depth1< depth0) or |
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| 281 | ((depth1==depth0) and (priority1>priority0))); |
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| 282 | |
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| 283 | if (is_valid) |
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| 284 | { |
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| 285 | // commit |
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| 286 | Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); |
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| 287 | reg_STATE [context] = CONTEXT_STATE_KO_MISS; |
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| 288 | reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT |
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| 289 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); |
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| 290 | reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence |
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| 291 | //reg_EVENT_ADDRESS_EEAR [context]; |
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| 292 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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| 293 | reg_EVENT_IS_DELAY_SLOT [context] = take; |
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| 294 | reg_EVENT_IS_DS_TAKE [context] = take; |
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| 295 | reg_EVENT_DEPTH [context] = depth; |
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| 296 | } |
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| 297 | } |
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| 298 | } |
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| 299 | |
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| 300 | // ------------------------------------------------------------------- |
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| 301 | // -----[ EVENT ]----------------------------------------------------- |
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| 302 | // ------------------------------------------------------------------- |
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| 303 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 304 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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| 305 | { |
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| 306 | // Write pc |
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| 307 | context_state_t state = reg_STATE [i]; |
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| 308 | |
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| 309 | switch (state) |
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| 310 | { |
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| 311 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 312 | { |
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| 313 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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| 314 | break; |
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| 315 | } |
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| 316 | case CONTEXT_STATE_KO_MISS_ADDR : |
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| 317 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 318 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 319 | { |
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| 320 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 321 | break; |
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| 322 | } |
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| 323 | default : |
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| 324 | { |
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[83] | 325 | #ifdef DEBUG_TEST |
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[88] | 326 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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[83] | 327 | #endif |
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[88] | 328 | break; |
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| 329 | } |
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| 330 | } |
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| 331 | } |
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[83] | 332 | |
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[88] | 333 | // ------------------------------------------------------------------- |
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| 334 | // -----[ SPR_EVENT ]------------------------------------------------- |
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| 335 | // ------------------------------------------------------------------- |
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| 336 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 337 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
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| 338 | { |
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| 339 | // Write spr |
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[83] | 340 | #ifdef DEBUG_TEST |
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[88] | 341 | context_state_t state = reg_STATE [i]; |
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| 342 | |
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| 343 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
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| 344 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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[83] | 345 | #endif |
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[88] | 346 | |
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| 347 | reg_STATE [i] = CONTEXT_STATE_OK; |
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| 348 | } |
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[83] | 349 | |
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[88] | 350 | // ------------------------------------------------------------------- |
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| 351 | // -----[ next state ]------------------------------------------------ |
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| 352 | // ------------------------------------------------------------------- |
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| 353 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 354 | { |
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| 355 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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[83] | 356 | |
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[88] | 357 | Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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| 358 | Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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[83] | 359 | |
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[88] | 360 | context_state_t state = reg_STATE [i]; |
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[83] | 361 | |
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[88] | 362 | switch (state) |
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| 363 | { |
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| 364 | case CONTEXT_STATE_OK : |
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| 365 | { |
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| 366 | // nothing, wait an event |
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| 367 | break; |
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| 368 | } |
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| 369 | case CONTEXT_STATE_KO_EXCEP : |
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| 370 | { |
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| 371 | // Wait end of all instruction |
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| 372 | if (inst_all == 0) |
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| 373 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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| 374 | break; |
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| 375 | } |
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| 376 | case CONTEXT_STATE_KO_MISS : |
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| 377 | { |
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| 378 | // Wait end of all instruction |
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| 379 | if (inst_all == 0) |
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| 380 | state = CONTEXT_STATE_KO_MISS_ADDR; |
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| 381 | break; |
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| 382 | } |
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| 383 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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| 384 | { |
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| 385 | // nothing, wait the update of internal register (pc) |
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| 386 | break; |
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| 387 | } |
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| 388 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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| 389 | { |
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| 390 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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| 391 | break; |
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| 392 | } |
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| 393 | case CONTEXT_STATE_KO_MISS_ADDR : |
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| 394 | { |
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| 395 | // nothing, wait the update of internal register (pc) |
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| 396 | break; |
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| 397 | } |
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| 398 | case CONTEXT_STATE_KO_PSYNC : |
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| 399 | { |
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| 400 | // Wait end of all instruction |
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| 401 | if (inst_all == 0) |
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| 402 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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| 403 | state = CONTEXT_STATE_KO_PSYNC_ADDR ; |
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| 404 | break; |
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| 405 | } |
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| 406 | // case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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| 407 | // { |
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| 408 | // // nothing, wait end of flush (ifetch) |
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| 409 | // break; |
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| 410 | // } |
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| 411 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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| 412 | { |
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| 413 | // nothing, wait the pc write |
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| 414 | break; |
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| 415 | } |
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| 416 | case CONTEXT_STATE_KO_CSYNC : |
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| 417 | { |
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| 418 | // Wait end of all instruction |
---|
| 419 | if (inst_all == 0) |
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| 420 | state = CONTEXT_STATE_KO_CSYNC_ADDR ; |
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| 421 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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| 422 | break; |
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| 423 | } |
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| 424 | // case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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| 425 | // { |
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| 426 | // // nothing, wait end of flush (all internal structure) |
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| 427 | // break; |
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| 428 | // } |
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| 429 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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| 430 | { |
---|
| 431 | // nothing, wait the pc write |
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| 432 | break; |
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| 433 | } |
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| 434 | case CONTEXT_STATE_KO_MSYNC : |
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| 435 | { |
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| 436 | // Wait end of memory instruction |
---|
| 437 | if (inst_mem == 0) |
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| 438 | state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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| 439 | break; |
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| 440 | } |
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| 441 | case CONTEXT_STATE_KO_MSYNC_ISSUE : |
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| 442 | { |
---|
| 443 | // Wait the msync issue |
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| 444 | if (inst_mem != 0) |
---|
| 445 | state = CONTEXT_STATE_KO_MSYNC_EXEC; |
---|
| 446 | break; |
---|
| 447 | } |
---|
| 448 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
---|
| 449 | { |
---|
| 450 | // Wait the end of msync |
---|
| 451 | if (inst_mem == 0) |
---|
| 452 | state = CONTEXT_STATE_OK; |
---|
| 453 | break; |
---|
| 454 | } |
---|
| 455 | case CONTEXT_STATE_KO_SPR : |
---|
| 456 | { |
---|
| 457 | // Wait end of all instruction |
---|
| 458 | if (inst_all == 0) |
---|
| 459 | state = CONTEXT_STATE_KO_SPR_ISSUE; |
---|
| 460 | break; |
---|
| 461 | } |
---|
| 462 | case CONTEXT_STATE_KO_SPR_ISSUE : |
---|
| 463 | { |
---|
| 464 | // Wait the spr_access issue |
---|
| 465 | if (inst_all != 0) |
---|
| 466 | state = CONTEXT_STATE_KO_SPR_EXEC; |
---|
| 467 | break; |
---|
| 468 | } |
---|
| 469 | case CONTEXT_STATE_KO_SPR_EXEC : |
---|
| 470 | { |
---|
| 471 | // Wait the spr_access execution |
---|
| 472 | if (inst_all == 0) |
---|
| 473 | state = CONTEXT_STATE_OK; |
---|
| 474 | break; |
---|
| 475 | } |
---|
[83] | 476 | |
---|
[88] | 477 | default : |
---|
| 478 | { |
---|
| 479 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
---|
| 480 | } |
---|
| 481 | } |
---|
| 482 | reg_STATE [i] = state; |
---|
| 483 | } |
---|
| 484 | |
---|
| 485 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 486 | { |
---|
| 487 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
| 488 | |
---|
| 489 | if (reg_INTERRUPT_ENABLE [i]) |
---|
| 490 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
| 491 | } |
---|
[83] | 492 | } |
---|
| 493 | |
---|
| 494 | #if DEBUG >= DEBUG_TRACE |
---|
| 495 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 496 | { |
---|
[88] | 497 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
---|
| 498 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
---|
| 499 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
---|
| 500 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
---|
| 501 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
---|
| 502 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
---|
| 503 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
---|
| 504 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
---|
| 505 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
---|
| 506 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
[83] | 507 | } |
---|
| 508 | #endif |
---|
| 509 | |
---|
| 510 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 511 | end_cycle (); |
---|
| 512 | #endif |
---|
| 513 | |
---|
| 514 | log_end(Context_State,FUNCTION); |
---|
| 515 | }; |
---|
| 516 | |
---|
| 517 | }; // end namespace context_state |
---|
| 518 | }; // end namespace front_end |
---|
| 519 | }; // end namespace multi_front_end |
---|
| 520 | }; // end namespace core |
---|
| 521 | |
---|
| 522 | }; // end namespace behavioural |
---|
| 523 | }; // end namespace morpheo |
---|
| 524 | #endif |
---|