Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r83 r88 22 22 { 23 23 log_begin(Context_State,FUNCTION); 24 log_function(Context_State,FUNCTION,_name.c_str()); 24 25 25 26 if (PORT_READ(in_NRESET) == 0) 26 27 { 27 for (uint32_t i=0; i<_param->_nb_context; i++) 28 reg_STATE [i] = CONTEXT_STATE_OK; 28 for (uint32_t i=0; i<_param->_nb_context; i++) 29 { 30 reg_STATE [i] = CONTEXT_STATE_OK; 31 reg_INTERRUPT_ENABLE [i] = 0; 32 } 29 33 } 30 34 else 31 35 { 32 // ------------------------------------------------------------------- 33 // -----[ DECOD_EVENT ]----------------------------------------------- 34 // ------------------------------------------------------------------- 35 36 for (uint32_t i=0; i<_param->_nb_decod_unit; i++) 37 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) 38 { 39 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; 40 Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; 41 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 42 Tdepth_t depth_base = (_param->_have_port_depth [context])?PORT_READ(in_DEPTH_TAIL [context]):0; 43 Tdepth_t depth_max = _param->_size_depth [context]; 44 45 Tdepth_t depth0 = (depth_cur>=depth_base)?(depth_cur-depth_base):((depth_cur+depth_max-depth_base)); 46 Tdepth_t depth1 = (depth >=depth_base)?(depth -depth_base):((depth +depth_max-depth_base)); 47 48 context_state_t state = reg_STATE [context]; 49 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); 50 51 // miss > excep > spr/sync 52 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 53 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 54 55 // is_valid = can modify local information 56 // if context_state_ok : yes 57 // if context_state_ko : test the depth, and the priority of envent 58 59 bool is_valid = ((state == CONTEXT_STATE_OK) or 60 (depth1< depth0) or 61 ((depth1==depth0) and (priority1>priority0))); 62 63 if (is_valid) 64 { 65 // decod : 66 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) 67 context_state_t state_next = state; 68 Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); 69 Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); 70 71 switch (type) 72 { 73 case EVENT_TYPE_EXCEPTION : 74 { 75 state_next = CONTEXT_STATE_KO_EXCEP; 76 break; 77 } 78 case EVENT_TYPE_SPR_ACCESS : 79 { 80 state_next = CONTEXT_STATE_KO_SPR ; 81 address++; // take next address 82 if (is_delay_slot) 83 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 84 break; 85 } 86 case EVENT_TYPE_MSYNC : 87 { 88 state_next = CONTEXT_STATE_KO_MSYNC; 89 address++; // take next address 90 if (is_delay_slot) 91 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 92 break; 93 } 94 case EVENT_TYPE_PSYNC : 95 { 96 state_next = CONTEXT_STATE_KO_PSYNC; 97 address++; // take next address 98 if (is_delay_slot) 99 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 100 break; 101 } 102 case EVENT_TYPE_CSYNC : 103 { 104 state_next = CONTEXT_STATE_KO_CSYNC; 105 address++; // take next address 106 if (is_delay_slot) 107 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 108 break; 109 } 110 case EVENT_TYPE_NONE : 111 case EVENT_TYPE_MISS_SPECULATION : 112 case EVENT_TYPE_BRANCH_NO_ACCURATE : 113 default : 114 { 115 throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); 116 } 117 } 118 119 reg_STATE [context] = state_next; 120 reg_EVENT_ADDRESS [context] = address; 121 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); 122 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; 123 //reg_EVENT_ADDRESS_EEAR [context] 124 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 125 reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; 126 //reg_EVENT_IS_DS_TAKE [context] = 0; 127 reg_EVENT_DEPTH [context] = depth; 128 } 129 } 130 131 // ------------------------------------------------------------------- 132 // -----[ COMMIT_EVENT ]---------------------------------------------- 133 // ------------------------------------------------------------------- 134 135 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 136 if (PORT_READ(in_COMMIT_EVENT_VAL [i]) and internal_COMMIT_EVENT_ACK [i]) 137 { 138 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID [i]):0; 139 Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH [i]):0; 140 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 141 Tdepth_t depth_base = (_param->_have_port_depth [context])?PORT_READ(in_DEPTH_TAIL [context]):0; 142 Tdepth_t depth_max = _param->_size_depth [context]; 143 144 Tdepth_t depth0 = (depth_cur>=depth_base)?(depth_cur-depth_base):((depth_cur+depth_max-depth_base)); 145 Tdepth_t depth1 = (depth >=depth_base)?(depth -depth_base):((depth +depth_max-depth_base)); 146 147 context_state_t state = reg_STATE [context]; 148 Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE [i]); 149 150 // miss > excep > spr/sync 151 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 152 uint8_t priority1 = 1; 153 154 // is_valid = can modify local information 155 // if context_state_ok : yes 156 // if context_state_ko : test the depth, and the priority of envent 157 158 bool is_valid = ((state == CONTEXT_STATE_OK) or 159 (depth1< depth0) or 160 ((depth1==depth0) and (priority1>priority0))); 161 162 if (is_valid) 163 { 164 // commit 165 // type : exception 166 context_state_t state_next = state; 167 switch (type) 168 { 169 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 170 case EVENT_TYPE_SPR_ACCESS : 171 case EVENT_TYPE_MSYNC : 172 case EVENT_TYPE_PSYNC : 173 case EVENT_TYPE_CSYNC : 174 case EVENT_TYPE_NONE : 175 case EVENT_TYPE_MISS_SPECULATION : 176 case EVENT_TYPE_BRANCH_NO_ACCURATE : 177 default : 178 { 179 throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); 180 } 181 } 182 reg_STATE [context] = state_next; 183 reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS [i]); 184 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR [i]); 185 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; 186 reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR [i]); 187 reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL [i]); 188 reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT [i]); 189 //reg_EVENT_IS_DS_TAKE [context] = 0; 190 reg_EVENT_DEPTH [context] = depth; 191 } 192 } 193 194 // ------------------------------------------------------------------- 195 // -----[ BRANCH_COMPLETE ]------------------------------------------- 196 // ------------------------------------------------------------------- 197 198 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 199 if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) 200 { 201 if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 202 { 203 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 204 Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 205 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 206 Tdepth_t depth_base = (_param->_have_port_depth [context])?PORT_READ(in_DEPTH_TAIL [context]):0; 207 Tdepth_t depth_max = _param->_size_depth [context]; 208 209 Tdepth_t depth0 = (depth_cur>=depth_base)?(depth_cur-depth_base):((depth_cur+depth_max-depth_base)); 210 Tdepth_t depth1 = (depth >=depth_base)?(depth -depth_base):((depth +depth_max-depth_base)); 211 212 context_state_t state = reg_STATE [context]; 213 214 // miss > excep > spr/sync 215 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 216 uint8_t priority1 = 2; 217 218 // is_valid = can modify local information 219 // if context_state_ok : yes 220 // if context_state_ko : test the depth, and the priority of envent 221 222 bool is_valid = ((state == CONTEXT_STATE_OK) or 223 (depth1< depth0) or 224 ((depth1==depth0) and (priority1>priority0))); 225 226 if (is_valid) 227 { 228 // commit 229 Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); 230 reg_STATE [context] = CONTEXT_STATE_KO_MISS; 231 reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT 232 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); 233 reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence 234 //reg_EVENT_ADDRESS_EEAR [context]; 235 //reg_EVENT_ADDRESS_EEAR_VAL [context]; 236 reg_EVENT_IS_DELAY_SLOT [context] = take; 237 reg_EVENT_IS_DS_TAKE [context] = take; 238 reg_EVENT_DEPTH [context] = depth; 239 } 240 } 241 } 242 243 // ------------------------------------------------------------------- 244 // -----[ EVENT ]----------------------------------------------------- 245 // ------------------------------------------------------------------- 246 for (uint32_t i=0; i<_param->_nb_context; i++) 247 if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) 248 { 249 // Write pc 250 context_state_t state = reg_STATE [i]; 251 252 switch (state) 253 { 254 case CONTEXT_STATE_KO_EXCEP_ADDR : 255 { 256 reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; 257 break; 258 } 259 case CONTEXT_STATE_KO_MISS_ADDR : 260 case CONTEXT_STATE_KO_PSYNC_ADDR : 261 case CONTEXT_STATE_KO_CSYNC_ADDR : 262 { 263 reg_STATE [i] = CONTEXT_STATE_OK; 264 break; 265 } 266 default : 267 { 36 // ------------------------------------------------------------------- 37 // -----[ BRANCH_EVENT ]---------------------------------------------- 38 // ------------------------------------------------------------------- 39 for (uint32_t i=0; i<_param->_nb_context; ++i) 40 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) 41 { 42 // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); 43 44 context_state_t state = reg_STATE [i]; 45 46 Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): 47 0; 48 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 49 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; 50 Tdepth_t depth_max = _param->_array_size_depth [i]; 51 52 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 53 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 54 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 55 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 56 57 // priority : miss > excep > spr/sync 58 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 59 uint8_t priority1 = 2; // miss 60 61 // is_valid = can modify local information 62 // if context_state_ok : yes 63 // if context_state_ko : test the depth, and the priority of envent 64 65 bool is_valid = ((state == CONTEXT_STATE_OK) or 66 (depth1< depth0) or 67 ((depth1==depth0) and (priority1>priority0))); 68 69 if (is_valid) 70 { 71 reg_STATE [i] = CONTEXT_STATE_KO_MISS; 72 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 73 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST[i]); // address_next 74 reg_EVENT_ADDRESS_EPCR_VAL [i] = 1; // address_dest is valid 75 //reg_EVENT_ADDRESS_EEAR [i] = 0; 76 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 77 reg_EVENT_IS_DELAY_SLOT [i] = 1; 78 reg_EVENT_IS_DS_TAKE [i] = 0;// ?? 79 reg_EVENT_DEPTH [i] = depth; 80 } 81 } 82 83 // ------------------------------------------------------------------- 84 // -----[ DECOD_EVENT ]----------------------------------------------- 85 // ------------------------------------------------------------------- 86 87 for (uint32_t i=0; i<_param->_nb_decod_unit; i++) 88 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) 89 { 90 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; 91 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; 92 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 93 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 94 Tdepth_t depth_max = _param->_array_size_depth [context]; 95 96 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 97 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 98 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 99 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 100 101 context_state_t state = reg_STATE [context]; 102 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); 103 104 // miss > excep > spr/sync 105 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 106 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 107 108 // is_valid = can modify local information 109 // if context_state_ok : yes 110 // if context_state_ko : test the depth, and the priority of envent 111 112 bool is_valid = ((state == CONTEXT_STATE_OK) or 113 (depth1< depth0) or 114 ((depth1==depth0) and (priority1>priority0))); 115 116 if (is_valid) 117 { 118 // decod : 119 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) 120 context_state_t state_next = state; 121 Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); 122 Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); 123 124 switch (type) 125 { 126 case EVENT_TYPE_EXCEPTION : 127 { 128 state_next = CONTEXT_STATE_KO_EXCEP; 129 130 break; 131 } 132 case EVENT_TYPE_SPR_ACCESS : 133 { 134 state_next = CONTEXT_STATE_KO_SPR ; 135 address++; // take next address 136 if (is_delay_slot) 137 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 138 break; 139 } 140 case EVENT_TYPE_MSYNC : 141 { 142 state_next = CONTEXT_STATE_KO_MSYNC; 143 address++; // take next address 144 if (is_delay_slot) 145 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 146 break; 147 } 148 case EVENT_TYPE_PSYNC : 149 { 150 state_next = CONTEXT_STATE_KO_PSYNC; 151 address++; // take next address 152 if (is_delay_slot) 153 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 154 break; 155 } 156 case EVENT_TYPE_CSYNC : 157 { 158 state_next = CONTEXT_STATE_KO_CSYNC; 159 address++; // take next address 160 if (is_delay_slot) 161 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 162 break; 163 } 164 case EVENT_TYPE_NONE : 165 case EVENT_TYPE_MISS_SPECULATION : 166 case EVENT_TYPE_BRANCH_NO_ACCURATE : 167 default : 168 { 169 throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); 170 } 171 } 172 173 reg_STATE [context] = state_next; 174 reg_EVENT_ADDRESS [context] = address; 175 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); 176 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; 177 //reg_EVENT_ADDRESS_EEAR [context] 178 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 179 reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; 180 //reg_EVENT_IS_DS_TAKE [context] = 0; 181 reg_EVENT_DEPTH [context] = depth; 182 } 183 } 184 185 // ------------------------------------------------------------------- 186 // -----[ COMMIT_EVENT ]---------------------------------------------- 187 // ------------------------------------------------------------------- 188 189 if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) 190 { 191 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; 192 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; 193 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 194 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 195 Tdepth_t depth_max = _param->_array_size_depth [context]; 196 197 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 198 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 199 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 200 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 201 202 context_state_t state = reg_STATE [context]; 203 Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); 204 205 // miss > excep > spr/sync 206 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 207 uint8_t priority1 = 1; // exception 208 209 // is_valid = can modify local information 210 // if context_state_ok : yes 211 // if context_state_ko : test the depth, and the priority of envent 212 213 bool is_valid = ((state == CONTEXT_STATE_OK) or 214 (depth1< depth0) or 215 ((depth1==depth0) and (priority1>priority0))); 216 217 if (is_valid) 218 { 219 // commit 220 // type : exception 221 context_state_t state_next = state; 222 switch (type) 223 { 224 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 225 case EVENT_TYPE_SPR_ACCESS : 226 case EVENT_TYPE_MSYNC : 227 case EVENT_TYPE_PSYNC : 228 case EVENT_TYPE_CSYNC : 229 case EVENT_TYPE_NONE : 230 case EVENT_TYPE_MISS_SPECULATION : 231 case EVENT_TYPE_BRANCH_NO_ACCURATE : 232 default : 233 { 234 throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); 235 } 236 } 237 reg_STATE [context] = state_next; 238 reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); 239 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); 240 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; 241 reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); 242 reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 243 reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); 244 //reg_EVENT_IS_DS_TAKE [context] = 0; 245 reg_EVENT_DEPTH [context] = depth; 246 } 247 } 248 249 // ------------------------------------------------------------------- 250 // -----[ BRANCH_COMPLETE ]------------------------------------------- 251 // ------------------------------------------------------------------- 252 253 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 254 if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) 255 { 256 if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) 257 { 258 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 259 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 260 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 261 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 262 Tdepth_t depth_max = _param->_array_size_depth [context]; 263 264 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 265 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 266 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 267 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 268 269 context_state_t state = reg_STATE [context]; 270 271 // miss > excep > spr/sync 272 uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 273 uint8_t priority1 = 2; // miss 274 275 // is_valid = can modify local information 276 // if context_state_ok : yes 277 // if context_state_ko : test the depth, and the priority of envent 278 279 bool is_valid = ((state == CONTEXT_STATE_OK) or 280 (depth1< depth0) or 281 ((depth1==depth0) and (priority1>priority0))); 282 283 if (is_valid) 284 { 285 // commit 286 Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); 287 reg_STATE [context] = CONTEXT_STATE_KO_MISS; 288 reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT 289 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); 290 reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence 291 //reg_EVENT_ADDRESS_EEAR [context]; 292 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 293 reg_EVENT_IS_DELAY_SLOT [context] = take; 294 reg_EVENT_IS_DS_TAKE [context] = take; 295 reg_EVENT_DEPTH [context] = depth; 296 } 297 } 298 } 299 300 // ------------------------------------------------------------------- 301 // -----[ EVENT ]----------------------------------------------------- 302 // ------------------------------------------------------------------- 303 for (uint32_t i=0; i<_param->_nb_context; i++) 304 if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) 305 { 306 // Write pc 307 context_state_t state = reg_STATE [i]; 308 309 switch (state) 310 { 311 case CONTEXT_STATE_KO_EXCEP_ADDR : 312 { 313 reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; 314 break; 315 } 316 case CONTEXT_STATE_KO_MISS_ADDR : 317 case CONTEXT_STATE_KO_PSYNC_ADDR : 318 case CONTEXT_STATE_KO_CSYNC_ADDR : 319 { 320 reg_STATE [i] = CONTEXT_STATE_OK; 321 break; 322 } 323 default : 324 { 268 325 #ifdef DEBUG_TEST 269 326 throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); 270 327 #endif 271 272 273 274 275 276 277 // -----[ SPR ]-------------------------------------------------------278 279 280 if (internal_SPR_VAL [i] and PORT_READ(in_SPR_ACK [i]))281 282 328 break; 329 } 330 } 331 } 332 333 // ------------------------------------------------------------------- 334 // -----[ SPR_EVENT ]------------------------------------------------- 335 // ------------------------------------------------------------------- 336 for (uint32_t i=0; i<_param->_nb_context; i++) 337 if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) 338 { 339 // Write spr 283 340 #ifdef DEBUG_TEST 284 285 286 287 throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));341 context_state_t state = reg_STATE [i]; 342 343 if (state != CONTEXT_STATE_KO_EXCEP_SPR) 344 throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); 288 345 #endif 289 290 reg_STATE [i] = CONTEXT_STATE_OK; 291 } 292 293 // ------------------------------------------------------------------- 294 // -----[ next state ]------------------------------------------------ 295 // ------------------------------------------------------------------- 296 for (uint32_t i=0; i<_param->_nb_context; i++) 297 { 298 uint32_t x = _param->_link_context_to_decod_unit [i]; 299 uint32_t y = _param->_link_decod_unit_to_ooo_engine [x]; 300 301 Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL [y]) + PORT_READ(in_NB_INST_DECOD_ALL [x]); 302 Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM [y]) + PORT_READ(in_NB_INST_DECOD_ALL [x]); 303 304 context_state_t state = reg_STATE [i]; 305 306 switch (state) 307 { 308 case CONTEXT_STATE_OK : 309 { 310 // nothing, wait an event 311 break; 312 } 313 case CONTEXT_STATE_KO_EXCEP : 314 { 315 // Wait end of all instruction 316 if (inst_all == 0) 317 state = CONTEXT_STATE_KO_EXCEP_ADDR; 318 break; 319 } 320 case CONTEXT_STATE_KO_MISS : 321 { 322 // Wait end of all instruction 323 if (inst_all == 0) 324 state = CONTEXT_STATE_KO_MISS_ADDR; 325 break; 326 } 327 case CONTEXT_STATE_KO_EXCEP_ADDR : 328 { 329 // nothing, wait the update of internal register (pc) 330 break; 331 } 332 case CONTEXT_STATE_KO_EXCEP_SPR : 333 { 334 // nothing, wait the update of internal register (epcr, eear, sr, esr) 335 break; 336 } 337 case CONTEXT_STATE_KO_MISS_ADDR : 338 { 339 // nothing, wait the update of internal register (pc) 340 break; 341 } 342 case CONTEXT_STATE_KO_PSYNC : 343 { 344 // Wait end of all instruction 345 if (inst_all == 0) 346 // state = CONTEXT_STATE_KO_PSYNC_FLUSH; 347 state = CONTEXT_STATE_KO_PSYNC_ADDR ; 348 break; 349 } 350 // case CONTEXT_STATE_KO_PSYNC_FLUSH : 351 // { 352 // // nothing, wait end of flush (ifetch) 353 // break; 354 // } 355 case CONTEXT_STATE_KO_PSYNC_ADDR : 356 { 357 // nothing, wait the pc write 358 break; 359 } 360 case CONTEXT_STATE_KO_CSYNC : 361 { 362 // Wait end of all instruction 363 if (inst_all == 0) 364 state = CONTEXT_STATE_KO_CSYNC_ADDR ; 365 // state = CONTEXT_STATE_KO_CSYNC_FLUSH; 366 break; 367 } 368 // case CONTEXT_STATE_KO_CSYNC_FLUSH : 369 // { 370 // // nothing, wait end of flush (all internal structure) 371 // break; 372 // } 373 case CONTEXT_STATE_KO_CSYNC_ADDR : 374 { 375 // nothing, wait the pc write 376 break; 377 } 378 case CONTEXT_STATE_KO_MSYNC : 379 { 380 // Wait end of memory instruction 381 if (inst_mem == 0) 382 state = CONTEXT_STATE_KO_MSYNC_ISSUE; 383 break; 384 } 385 case CONTEXT_STATE_KO_MSYNC_ISSUE : 386 { 387 // Wait the msync issue 388 if (inst_mem != 0) 389 state = CONTEXT_STATE_KO_MSYNC_EXEC; 390 break; 391 } 392 case CONTEXT_STATE_KO_MSYNC_EXEC : 393 { 394 // Wait the end of msync 395 if (inst_mem == 0) 396 state = CONTEXT_STATE_OK; 397 break; 398 } 399 case CONTEXT_STATE_KO_SPR : 400 { 401 // Wait end of all instruction 402 if (inst_all == 0) 403 state = CONTEXT_STATE_KO_SPR_ISSUE; 404 break; 405 } 406 case CONTEXT_STATE_KO_SPR_ISSUE : 407 { 408 // Wait the spr_access issue 409 if (inst_all != 0) 410 state = CONTEXT_STATE_KO_SPR_EXEC; 411 break; 412 } 413 case CONTEXT_STATE_KO_SPR_EXEC : 414 { 415 // Wait the spr_access execution 416 if (inst_all == 0) 417 state = CONTEXT_STATE_OK; 418 break; 419 } 420 421 default : 422 { 423 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); 424 } 425 } 426 reg_STATE [i] = state; 427 } 346 347 reg_STATE [i] = CONTEXT_STATE_OK; 348 } 349 350 // ------------------------------------------------------------------- 351 // -----[ next state ]------------------------------------------------ 352 // ------------------------------------------------------------------- 353 for (uint32_t i=0; i<_param->_nb_context; i++) 354 { 355 // uint32_t x = _param->_link_context_to_decod_unit [i]; 356 357 Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); 358 Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); 359 360 context_state_t state = reg_STATE [i]; 361 362 switch (state) 363 { 364 case CONTEXT_STATE_OK : 365 { 366 // nothing, wait an event 367 break; 368 } 369 case CONTEXT_STATE_KO_EXCEP : 370 { 371 // Wait end of all instruction 372 if (inst_all == 0) 373 state = CONTEXT_STATE_KO_EXCEP_ADDR; 374 break; 375 } 376 case CONTEXT_STATE_KO_MISS : 377 { 378 // Wait end of all instruction 379 if (inst_all == 0) 380 state = CONTEXT_STATE_KO_MISS_ADDR; 381 break; 382 } 383 case CONTEXT_STATE_KO_EXCEP_ADDR : 384 { 385 // nothing, wait the update of internal register (pc) 386 break; 387 } 388 case CONTEXT_STATE_KO_EXCEP_SPR : 389 { 390 // nothing, wait the update of internal register (epcr, eear, sr, esr) 391 break; 392 } 393 case CONTEXT_STATE_KO_MISS_ADDR : 394 { 395 // nothing, wait the update of internal register (pc) 396 break; 397 } 398 case CONTEXT_STATE_KO_PSYNC : 399 { 400 // Wait end of all instruction 401 if (inst_all == 0) 402 // state = CONTEXT_STATE_KO_PSYNC_FLUSH; 403 state = CONTEXT_STATE_KO_PSYNC_ADDR ; 404 break; 405 } 406 // case CONTEXT_STATE_KO_PSYNC_FLUSH : 407 // { 408 // // nothing, wait end of flush (ifetch) 409 // break; 410 // } 411 case CONTEXT_STATE_KO_PSYNC_ADDR : 412 { 413 // nothing, wait the pc write 414 break; 415 } 416 case CONTEXT_STATE_KO_CSYNC : 417 { 418 // Wait end of all instruction 419 if (inst_all == 0) 420 state = CONTEXT_STATE_KO_CSYNC_ADDR ; 421 // state = CONTEXT_STATE_KO_CSYNC_FLUSH; 422 break; 423 } 424 // case CONTEXT_STATE_KO_CSYNC_FLUSH : 425 // { 426 // // nothing, wait end of flush (all internal structure) 427 // break; 428 // } 429 case CONTEXT_STATE_KO_CSYNC_ADDR : 430 { 431 // nothing, wait the pc write 432 break; 433 } 434 case CONTEXT_STATE_KO_MSYNC : 435 { 436 // Wait end of memory instruction 437 if (inst_mem == 0) 438 state = CONTEXT_STATE_KO_MSYNC_ISSUE; 439 break; 440 } 441 case CONTEXT_STATE_KO_MSYNC_ISSUE : 442 { 443 // Wait the msync issue 444 if (inst_mem != 0) 445 state = CONTEXT_STATE_KO_MSYNC_EXEC; 446 break; 447 } 448 case CONTEXT_STATE_KO_MSYNC_EXEC : 449 { 450 // Wait the end of msync 451 if (inst_mem == 0) 452 state = CONTEXT_STATE_OK; 453 break; 454 } 455 case CONTEXT_STATE_KO_SPR : 456 { 457 // Wait end of all instruction 458 if (inst_all == 0) 459 state = CONTEXT_STATE_KO_SPR_ISSUE; 460 break; 461 } 462 case CONTEXT_STATE_KO_SPR_ISSUE : 463 { 464 // Wait the spr_access issue 465 if (inst_all != 0) 466 state = CONTEXT_STATE_KO_SPR_EXEC; 467 break; 468 } 469 case CONTEXT_STATE_KO_SPR_EXEC : 470 { 471 // Wait the spr_access execution 472 if (inst_all == 0) 473 state = CONTEXT_STATE_OK; 474 break; 475 } 476 477 default : 478 { 479 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); 480 } 481 } 482 reg_STATE [i] = state; 483 } 484 485 for (uint32_t i=0; i<_param->_nb_context; ++i) 486 { 487 reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); 488 489 if (reg_INTERRUPT_ENABLE [i]) 490 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); 491 } 428 492 } 429 493 … … 431 495 for (uint32_t i=0; i<_param->_nb_context; i++) 432 496 { 433 log_printf(TRACE,Context_State,FUNCTION,"Context State [%d]",i);434 log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s",toString(reg_STATE [i]).c_str());435 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x",reg_EVENT_ADDRESS [i]);436 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x",reg_EVENT_ADDRESS_EPCR [i]);437 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d",reg_EVENT_ADDRESS_EPCR_VAL [i]);438 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x",reg_EVENT_ADDRESS_EEAR [i]);439 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d",reg_EVENT_ADDRESS_EEAR_VAL [i]);440 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d",reg_EVENT_IS_DELAY_SLOT [i]);441 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d",reg_EVENT_IS_DS_TAKE [i]);442 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d",reg_EVENT_DEPTH [i]);497 log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); 498 log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); 499 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); 500 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); 501 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); 502 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); 503 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); 504 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); 505 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); 506 log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 443 507 } 444 508 #endif
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