1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Context_State_transition.cpp 95 2008-12-16 16:24:26Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace context_state { |
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17 | |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Context_State::transition" |
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21 | void Context_State::transition (void) |
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22 | { |
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23 | log_begin(Context_State,FUNCTION); |
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24 | log_function(Context_State,FUNCTION,_name.c_str()); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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29 | { |
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30 | reg_STATE [i] = CONTEXT_STATE_OK; |
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31 | reg_INTERRUPT_ENABLE [i] = 0; |
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32 | } |
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33 | } |
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34 | else |
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35 | { |
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36 | // ------------------------------------------------------------------- |
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37 | // -----[ BRANCH_EVENT ]---------------------------------------------- |
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38 | // ------------------------------------------------------------------- |
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39 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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40 | if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) |
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41 | { |
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42 | // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); |
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43 | |
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44 | context_state_t state = reg_STATE [i]; |
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45 | |
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46 | Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): |
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47 | 0; |
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48 | Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; |
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49 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; |
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50 | Tdepth_t depth_max = _param->_array_size_depth [i]; |
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51 | |
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52 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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53 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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54 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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55 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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56 | |
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57 | // priority : miss > excep > spr/sync |
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58 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0); |
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59 | uint8_t priority1 = 2; // miss |
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60 | |
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61 | // is_valid = can modify local information |
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62 | // if context_state_ok : yes |
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63 | // if context_state_ko : test the depth, and the priority of envent |
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64 | |
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65 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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66 | (depth1< depth0) or |
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67 | ((depth1==depth0) and (priority1>priority0))); |
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68 | |
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69 | if (is_valid) |
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70 | { |
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71 | Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); |
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72 | reg_STATE [i] = CONTEXT_STATE_KO_MISS; |
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73 | reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot |
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74 | reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next |
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75 | reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; |
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76 | //reg_EVENT_ADDRESS_EEAR [i] = 0; |
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77 | reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; |
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78 | reg_EVENT_IS_DELAY_SLOT [i] = dest_val; |
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79 | reg_EVENT_IS_DS_TAKE [i] = dest_val; |
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80 | reg_EVENT_DEPTH [i] = depth; |
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81 | } |
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82 | } |
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83 | |
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84 | // ------------------------------------------------------------------- |
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85 | // -----[ DECOD_EVENT ]----------------------------------------------- |
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86 | // ------------------------------------------------------------------- |
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87 | |
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88 | for (uint32_t i=0; i<_param->_nb_decod_unit; i++) |
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89 | if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) |
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90 | { |
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91 | Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; |
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92 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; |
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93 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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94 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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95 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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96 | |
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97 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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98 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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99 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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100 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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101 | |
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102 | context_state_t state = reg_STATE [context]; |
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103 | Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); |
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104 | |
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105 | // miss > excep > spr/sync |
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106 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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107 | uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; |
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108 | |
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109 | // is_valid = can modify local information |
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110 | // if context_state_ok : yes |
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111 | // if context_state_ko : test the depth, and the priority of envent |
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112 | |
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113 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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114 | (depth1< depth0) or |
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115 | ((depth1==depth0) and (priority1>priority0))); |
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116 | |
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117 | if (is_valid) |
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118 | { |
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119 | // decod : |
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120 | // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) |
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121 | context_state_t state_next = state; |
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122 | Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); |
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123 | Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); |
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124 | |
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125 | switch (type) |
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126 | { |
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127 | case EVENT_TYPE_EXCEPTION : |
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128 | { |
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129 | state_next = CONTEXT_STATE_KO_EXCEP; |
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130 | |
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131 | break; |
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132 | } |
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133 | case EVENT_TYPE_SPR_ACCESS : |
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134 | { |
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135 | state_next = CONTEXT_STATE_KO_SPR ; |
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136 | address++; // take next address |
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137 | if (is_delay_slot) |
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138 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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139 | break; |
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140 | } |
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141 | case EVENT_TYPE_MSYNC : |
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142 | { |
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143 | state_next = CONTEXT_STATE_KO_MSYNC; |
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144 | address++; // take next address |
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145 | if (is_delay_slot) |
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146 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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147 | break; |
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148 | } |
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149 | case EVENT_TYPE_PSYNC : |
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150 | { |
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151 | state_next = CONTEXT_STATE_KO_PSYNC; |
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152 | address++; // take next address |
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153 | if (is_delay_slot) |
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154 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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155 | break; |
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156 | } |
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157 | case EVENT_TYPE_CSYNC : |
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158 | { |
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159 | state_next = CONTEXT_STATE_KO_CSYNC; |
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160 | address++; // take next address |
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161 | if (is_delay_slot) |
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162 | throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); |
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163 | break; |
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164 | } |
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165 | case EVENT_TYPE_NONE : |
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166 | case EVENT_TYPE_MISS_SPECULATION : |
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167 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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168 | default : |
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169 | { |
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170 | throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); |
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171 | } |
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172 | } |
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173 | |
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174 | reg_STATE [context] = state_next; |
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175 | reg_EVENT_ADDRESS [context] = address; |
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176 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); |
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177 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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178 | //reg_EVENT_ADDRESS_EEAR [context] |
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179 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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180 | reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; |
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181 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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182 | reg_EVENT_DEPTH [context] = depth; |
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183 | } |
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184 | } |
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185 | |
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186 | // ------------------------------------------------------------------- |
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187 | // -----[ COMMIT_EVENT ]---------------------------------------------- |
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188 | // ------------------------------------------------------------------- |
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189 | |
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190 | if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) |
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191 | { |
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192 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; |
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193 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; |
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194 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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195 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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196 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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197 | |
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198 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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199 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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200 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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201 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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202 | |
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203 | context_state_t state = reg_STATE [context]; |
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204 | Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); |
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205 | |
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206 | // miss > excep > spr/sync |
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207 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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208 | uint8_t priority1 = 1; // exception |
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209 | |
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210 | // is_valid = can modify local information |
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211 | // if context_state_ok : yes |
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212 | // if context_state_ko : test the depth, and the priority of envent |
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213 | |
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214 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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215 | (depth1< depth0) or |
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216 | ((depth1==depth0) and (priority1>priority0))); |
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217 | |
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218 | if (is_valid) |
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219 | { |
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220 | // commit |
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221 | // type : exception |
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222 | context_state_t state_next = state; |
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223 | switch (type) |
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224 | { |
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225 | case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} |
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226 | case EVENT_TYPE_SPR_ACCESS : |
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227 | case EVENT_TYPE_MSYNC : |
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228 | case EVENT_TYPE_PSYNC : |
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229 | case EVENT_TYPE_CSYNC : |
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230 | case EVENT_TYPE_NONE : |
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231 | case EVENT_TYPE_MISS_SPECULATION : |
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232 | case EVENT_TYPE_BRANCH_NO_ACCURATE : |
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233 | default : |
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234 | { |
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235 | throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); |
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236 | } |
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237 | } |
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238 | reg_STATE [context] = state_next; |
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239 | reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); |
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240 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); |
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241 | reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; |
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242 | reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); |
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243 | reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); |
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244 | reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); |
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245 | //reg_EVENT_IS_DS_TAKE [context] = 0; |
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246 | reg_EVENT_DEPTH [context] = depth; |
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247 | } |
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248 | } |
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249 | |
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250 | // ------------------------------------------------------------------- |
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251 | // -----[ BRANCH_COMPLETE ]------------------------------------------- |
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252 | // ------------------------------------------------------------------- |
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253 | |
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254 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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255 | if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) |
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256 | { |
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257 | if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) |
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258 | { |
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259 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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260 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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261 | Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; |
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262 | Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; |
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263 | Tdepth_t depth_max = _param->_array_size_depth [context]; |
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264 | |
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265 | // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); |
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266 | // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); |
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267 | Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); |
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268 | Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); |
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269 | |
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270 | context_state_t state = reg_STATE [context]; |
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271 | |
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272 | // miss > excep > spr/sync |
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273 | uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); |
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274 | uint8_t priority1 = 2; // miss |
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275 | |
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276 | // is_valid = can modify local information |
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277 | // if context_state_ok : yes |
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278 | // if context_state_ko : test the depth, and the priority of envent |
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279 | |
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280 | bool is_valid = ((state == CONTEXT_STATE_OK) or |
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281 | (depth1< depth0) or |
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282 | ((depth1==depth0) and (priority1>priority0))); |
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283 | |
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284 | if (is_valid) |
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285 | { |
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286 | // commit |
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287 | Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); |
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288 | reg_STATE [context] = CONTEXT_STATE_KO_MISS; |
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289 | reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT |
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290 | reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); |
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291 | reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence |
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292 | //reg_EVENT_ADDRESS_EEAR [context]; |
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293 | reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; |
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294 | reg_EVENT_IS_DELAY_SLOT [context] = take; |
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295 | reg_EVENT_IS_DS_TAKE [context] = take; |
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296 | reg_EVENT_DEPTH [context] = depth; |
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297 | } |
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298 | } |
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299 | } |
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300 | |
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301 | // ------------------------------------------------------------------- |
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302 | // -----[ EVENT ]----------------------------------------------------- |
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303 | // ------------------------------------------------------------------- |
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304 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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305 | if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) |
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306 | { |
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307 | // Write pc |
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308 | context_state_t state = reg_STATE [i]; |
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309 | |
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310 | switch (state) |
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311 | { |
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312 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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313 | { |
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314 | reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; |
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315 | break; |
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316 | } |
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317 | case CONTEXT_STATE_KO_MISS_ADDR : |
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318 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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319 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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320 | { |
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321 | reg_STATE [i] = CONTEXT_STATE_OK; |
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322 | break; |
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323 | } |
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324 | default : |
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325 | { |
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326 | #ifdef DEBUG_TEST |
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327 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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328 | #endif |
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329 | break; |
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330 | } |
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331 | } |
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332 | } |
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333 | |
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334 | // ------------------------------------------------------------------- |
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335 | // -----[ SPR_EVENT ]------------------------------------------------- |
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336 | // ------------------------------------------------------------------- |
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337 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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338 | if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) |
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339 | { |
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340 | // Write spr |
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341 | #ifdef DEBUG_TEST |
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342 | context_state_t state = reg_STATE [i]; |
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343 | |
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344 | if (state != CONTEXT_STATE_KO_EXCEP_SPR) |
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345 | throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); |
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346 | #endif |
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347 | |
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348 | reg_STATE [i] = CONTEXT_STATE_OK; |
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349 | } |
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350 | |
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351 | // ------------------------------------------------------------------- |
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352 | // -----[ next state ]------------------------------------------------ |
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353 | // ------------------------------------------------------------------- |
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354 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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355 | { |
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356 | // uint32_t x = _param->_link_context_to_decod_unit [i]; |
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357 | |
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358 | Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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359 | Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); |
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360 | |
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361 | context_state_t state = reg_STATE [i]; |
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362 | |
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363 | switch (state) |
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364 | { |
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365 | case CONTEXT_STATE_OK : |
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366 | { |
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367 | // nothing, wait an event |
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368 | break; |
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369 | } |
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370 | case CONTEXT_STATE_KO_EXCEP : |
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371 | { |
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372 | // Wait end of all instruction |
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373 | if (inst_all == 0) |
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374 | state = CONTEXT_STATE_KO_EXCEP_ADDR; |
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375 | break; |
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376 | } |
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377 | case CONTEXT_STATE_KO_MISS : |
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378 | { |
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379 | // Wait end of all instruction |
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380 | if (inst_all == 0) |
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381 | state = CONTEXT_STATE_KO_MISS_ADDR; |
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382 | break; |
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383 | } |
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384 | case CONTEXT_STATE_KO_EXCEP_ADDR : |
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385 | { |
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386 | // nothing, wait the update of internal register (pc) |
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387 | break; |
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388 | } |
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389 | case CONTEXT_STATE_KO_EXCEP_SPR : |
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390 | { |
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391 | // nothing, wait the update of internal register (epcr, eear, sr, esr) |
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392 | break; |
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393 | } |
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394 | case CONTEXT_STATE_KO_MISS_ADDR : |
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395 | { |
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396 | // nothing, wait the update of internal register (pc) |
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397 | break; |
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398 | } |
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399 | case CONTEXT_STATE_KO_PSYNC : |
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400 | { |
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401 | // Wait end of all instruction |
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402 | if (inst_all == 0) |
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403 | // state = CONTEXT_STATE_KO_PSYNC_FLUSH; |
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404 | state = CONTEXT_STATE_KO_PSYNC_ADDR ; |
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405 | break; |
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406 | } |
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407 | // case CONTEXT_STATE_KO_PSYNC_FLUSH : |
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408 | // { |
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409 | // // nothing, wait end of flush (ifetch) |
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410 | // break; |
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411 | // } |
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412 | case CONTEXT_STATE_KO_PSYNC_ADDR : |
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413 | { |
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414 | // nothing, wait the pc write |
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415 | break; |
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416 | } |
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417 | case CONTEXT_STATE_KO_CSYNC : |
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418 | { |
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419 | // Wait end of all instruction |
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420 | if (inst_all == 0) |
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421 | state = CONTEXT_STATE_KO_CSYNC_ADDR ; |
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422 | // state = CONTEXT_STATE_KO_CSYNC_FLUSH; |
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423 | break; |
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424 | } |
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425 | // case CONTEXT_STATE_KO_CSYNC_FLUSH : |
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426 | // { |
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427 | // // nothing, wait end of flush (all internal structure) |
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428 | // break; |
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429 | // } |
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430 | case CONTEXT_STATE_KO_CSYNC_ADDR : |
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431 | { |
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432 | // nothing, wait the pc write |
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433 | break; |
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434 | } |
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435 | case CONTEXT_STATE_KO_MSYNC : |
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436 | { |
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437 | // Wait end of memory instruction |
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438 | if (inst_mem == 0) |
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439 | state = CONTEXT_STATE_KO_MSYNC_ISSUE; |
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440 | break; |
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441 | } |
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442 | case CONTEXT_STATE_KO_MSYNC_ISSUE : |
---|
443 | { |
---|
444 | // Wait the msync issue |
---|
445 | if (inst_mem != 0) |
---|
446 | state = CONTEXT_STATE_KO_MSYNC_EXEC; |
---|
447 | break; |
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448 | } |
---|
449 | case CONTEXT_STATE_KO_MSYNC_EXEC : |
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450 | { |
---|
451 | // Wait the end of msync |
---|
452 | if (inst_mem == 0) |
---|
453 | state = CONTEXT_STATE_OK; |
---|
454 | break; |
---|
455 | } |
---|
456 | case CONTEXT_STATE_KO_SPR : |
---|
457 | { |
---|
458 | // Wait end of all instruction |
---|
459 | if (inst_all == 0) |
---|
460 | state = CONTEXT_STATE_KO_SPR_ISSUE; |
---|
461 | break; |
---|
462 | } |
---|
463 | case CONTEXT_STATE_KO_SPR_ISSUE : |
---|
464 | { |
---|
465 | // Wait the spr_access issue |
---|
466 | if (inst_all != 0) |
---|
467 | state = CONTEXT_STATE_KO_SPR_EXEC; |
---|
468 | break; |
---|
469 | } |
---|
470 | case CONTEXT_STATE_KO_SPR_EXEC : |
---|
471 | { |
---|
472 | // Wait the spr_access execution |
---|
473 | if (inst_all == 0) |
---|
474 | state = CONTEXT_STATE_OK; |
---|
475 | break; |
---|
476 | } |
---|
477 | |
---|
478 | default : |
---|
479 | { |
---|
480 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); |
---|
481 | } |
---|
482 | } |
---|
483 | reg_STATE [i] = state; |
---|
484 | } |
---|
485 | |
---|
486 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
487 | { |
---|
488 | reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); |
---|
489 | |
---|
490 | if (reg_INTERRUPT_ENABLE [i]) |
---|
491 | throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); |
---|
492 | } |
---|
493 | } |
---|
494 | |
---|
495 | #if DEBUG >= DEBUG_TRACE |
---|
496 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
497 | { |
---|
498 | log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); |
---|
499 | log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); |
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500 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); |
---|
501 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); |
---|
502 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); |
---|
503 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); |
---|
504 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); |
---|
505 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); |
---|
506 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); |
---|
507 | log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
508 | } |
---|
509 | #endif |
---|
510 | |
---|
511 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
512 | end_cycle (); |
---|
513 | #endif |
---|
514 | |
---|
515 | log_end(Context_State,FUNCTION); |
---|
516 | }; |
---|
517 | |
---|
518 | }; // end namespace context_state |
---|
519 | }; // end namespace front_end |
---|
520 | }; // end namespace multi_front_end |
---|
521 | }; // end namespace core |
---|
522 | |
---|
523 | }; // end namespace behavioural |
---|
524 | }; // end namespace morpheo |
---|
525 | #endif |
---|