Ignore:
Timestamp:
Dec 16, 2008, 5:24:26 PM (16 years ago)
Author:
rosiere
Message:

1) Update Prediction Table - New architecture (systemC) done (and tested) -> need change interface in top level
2) Change documentation on VHDL generation
3) Change VHDL constant (case std_logic and std_logic_vector)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

    r88 r95  
    6969              if (is_valid)
    7070                {
     71                  Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
    7172                  reg_STATE                  [i] =  CONTEXT_STATE_KO_MISS;
    72                   reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
    73                   reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST[i]);   // address_next
    74                   reg_EVENT_ADDRESS_EPCR_VAL [i] =  1; // address_dest is valid
     73                  reg_EVENT_ADDRESS          [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC  [i])+1; // address delay slot
     74                  reg_EVENT_ADDRESS_EPCR     [i] =  PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]);   // address_next
     75                  reg_EVENT_ADDRESS_EPCR_VAL [i] =  dest_val;
    7576                //reg_EVENT_ADDRESS_EEAR     [i] =  0;
    7677                  reg_EVENT_ADDRESS_EEAR_VAL [i] =  0;
    77                   reg_EVENT_IS_DELAY_SLOT    [i] =  1;
    78                   reg_EVENT_IS_DS_TAKE       [i] =  0;// ??
     78                  reg_EVENT_IS_DELAY_SLOT    [i] =  dest_val;
     79                  reg_EVENT_IS_DS_TAKE       [i] =  dest_val;
    7980                  reg_EVENT_DEPTH            [i] =  depth;
    8081                }
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