Changeset 108 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

Timestamp:

Feb 12, 2009, 12:55:06 PM (15 years ago)

Author:

rosiere

Message:

1) decod_queue : add reg_LAST_SLOT.
2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not)
3) Context State / UPT : Branch miss and Load miss in same cycle.
4) Free List : Bank is on LSB not MSB.
5) Platforms : move data

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (modified) (8 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp

@@ -82 +82 @@
                   break;
                 }
+              case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND :
+                {
+                  // Wait end of all instruction
+                  if (inst_all == 0)
+                    
+//                  state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
+                    state = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR;
+                  break;
+                }
               case CONTEXT_STATE_KO_EXCEP_SPR    :
                 {
@@ -93 +102 @@
                 }
               case CONTEXT_STATE_KO_MISS_LOAD_ADDR    :
+                {
+                  // nothing, wait the update of internal register (pc)
+                  break;
+                }
+              case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR    :
                 {
                   // nothing, wait the update of internal register (pc)
@@ -209 +223 @@
 
               // priority : miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR     ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND  ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);
               uint8_t    priority1  = 2; // miss
 
@@ -272 +288 @@
               
               // miss > excep > spr/sync
-              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR   ) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR     ) or
-                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
-                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND  ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
               uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:0;
 
@@ -405 +423 @@
             
             // miss > excep > spr/sync
-            uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR   ) or
-                                     (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR     ) or
-                                     (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or
-                                     (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND  ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
+              uint8_t    priority0  = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR              ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                                       (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND           ) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
             uint8_t    priority1  = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
 
@@ -437 +457 @@
                   {
                   case EVENT_TYPE_EXCEPTION               : {state_next = CONTEXT_STATE_KO_EXCEP;             break;}
-                  case EVENT_TYPE_LOAD_MISS_SPECULATION   : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;}
+                  case EVENT_TYPE_LOAD_MISS_SPECULATION   : 
+                    {
+                      // Test if previous branch occure
+                      if ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR            ) or
+                          (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND         ) or
+                          (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR   ) or
+                          (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND))
+                        state_next = CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_WAITEND;
+                      else
+                        state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
+                      break;
+                    }
                   case EVENT_TYPE_BRANCH_MISS_SPECULATION :
                   case EVENT_TYPE_SPR_ACCESS              :
@@ -480 +511 @@
                   }
                 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
+
 //                   {
 //                     reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
@@ -489 +521 @@
                   {
                     reg_STATE [i] = CONTEXT_STATE_OK;
+                    break;
+                  }
+                case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR:
+                  {
+                    reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
                     break;
                   }