[78] | 1 | /* |
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| 2 | * $Id: Instruction.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * instruction MAC_UNIT (l.mac, l.maci, l.macrc, l.msb) throw a context event. Also is sequential. |
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| 7 | * If your program need intensive mac_unit, you can change the implementation of this unit : |
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| 8 | * 1) "decod" : inst->_event_type = EVENT_TYPE_NONE; |
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| 9 | * 2) "rename" : add component as load_store_unit pointer management |
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| 10 | * 3) "functionnal_unit" : test type instruction, if type=MAC_UNIT, insert in queue, the localisation is the ptr give by rename stage. Retire in this queue in sequence (as the store queue). |
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| 11 | * |
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| 12 | */ |
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| 13 | |
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| 14 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h" |
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[86] | 15 | #include "Behavioural/include/Constants.h" |
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[88] | 16 | #include "Behavioural/include/Operation.h" |
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[78] | 17 | |
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| 18 | namespace morpheo { |
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| 19 | namespace behavioural { |
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| 20 | namespace core { |
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| 21 | namespace multi_front_end { |
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| 22 | namespace front_end { |
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| 23 | namespace decod_unit { |
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| 24 | namespace decod { |
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| 25 | |
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| 26 | #define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>(32, x,true ,nb_bits) |
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| 27 | #define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>(32, x,false,nb_bits) |
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| 28 | |
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| 29 | void instruction_decod (decod_instruction_t * inst, decod_param_t * param) |
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| 30 | { |
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| 31 | // instruction_decod_type_0 (inst,param); |
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| 32 | |
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| 33 | uint32_t opcod = range<uint32_t>(inst->_instruction,31,26); |
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| 34 | (* param->_function_decod[ 0][opcod]) (inst,param); |
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| 35 | } |
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| 36 | |
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| 37 | // void instruction_decod_type_0 (decod_instruction_t * inst, decod_param_t * param) |
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| 38 | // { |
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| 39 | // uint32_t opcod = range<uint32_t>(inst->_instruction,31,26); |
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| 40 | // (* param->_function_decod[ 0][opcod]) (inst,param); |
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| 41 | // } |
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| 42 | |
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| 43 | void instruction_decod_type_1 (decod_instruction_t * inst, decod_param_t * param) |
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| 44 | { |
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| 45 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); |
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| 46 | (* param->_function_decod[ 1][opcod]) (inst,param); |
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| 47 | } |
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| 48 | |
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| 49 | void instruction_decod_type_2 (decod_instruction_t * inst, decod_param_t * param) |
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| 50 | { |
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| 51 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); |
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| 52 | (* param->_function_decod[ 2][opcod]) (inst,param); |
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| 53 | } |
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| 54 | |
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| 55 | void instruction_decod_type_3 (decod_instruction_t * inst, decod_param_t * param) |
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| 56 | { |
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| 57 | uint32_t opcod = ((range<uint32_t>(inst->_instruction, 9, 8)<<4) | |
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| 58 | (range<uint32_t>(inst->_instruction, 3, 0))); |
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| 59 | (* param->_function_decod[ 3][opcod]) (inst,param); |
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| 60 | } |
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| 61 | |
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| 62 | void instruction_decod_type_4 (decod_instruction_t * inst, decod_param_t * param) |
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| 63 | { |
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| 64 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,21); |
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| 65 | (* param->_function_decod[ 4][opcod]) (inst,param); |
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| 66 | } |
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| 67 | |
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| 68 | void instruction_decod_type_5 (decod_instruction_t * inst, decod_param_t * param) |
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| 69 | { |
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| 70 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,21); |
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| 71 | (* param->_function_decod[ 5][opcod]) (inst,param); |
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| 72 | } |
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| 73 | |
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| 74 | void instruction_decod_type_6 (decod_instruction_t * inst, decod_param_t * param) |
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| 75 | { |
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| 76 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 77 | (* param->_function_decod[ 6][opcod]) (inst,param); |
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| 78 | } |
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| 79 | |
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| 80 | void instruction_decod_type_7 (decod_instruction_t * inst, decod_param_t * param) |
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| 81 | { |
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| 82 | uint32_t opcod = range<uint32_t>(inst->_instruction, 3, 0); |
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| 83 | (* param->_function_decod[ 7][opcod]) (inst,param); |
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| 84 | } |
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| 85 | |
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| 86 | void instruction_decod_type_8 (decod_instruction_t * inst, decod_param_t * param) |
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| 87 | { |
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| 88 | uint32_t opcod = range<uint32_t>(inst->_instruction,16,16); |
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| 89 | (* param->_function_decod[ 8][opcod]) (inst,param); |
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| 90 | } |
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| 91 | |
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| 92 | void instruction_decod_type_9 (decod_instruction_t * inst, decod_param_t * param) |
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| 93 | { |
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| 94 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,23); |
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| 95 | (* param->_function_decod[ 9][opcod]) (inst,param); |
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| 96 | } |
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| 97 | |
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| 98 | void instruction_decod_type_10 (decod_instruction_t * inst, decod_param_t * param) |
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| 99 | { |
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| 100 | uint32_t opcod = range<uint32_t>(inst->_instruction,25,24); |
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| 101 | (* param->_function_decod[10][opcod]) (inst,param); |
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| 102 | } |
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| 103 | |
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| 104 | void instruction_decod_type_11 (decod_instruction_t * inst, decod_param_t * param) |
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| 105 | { |
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| 106 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 107 | (* param->_function_decod[11][opcod]) (inst,param); |
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| 108 | } |
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| 109 | |
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| 110 | void instruction_decod_type_12 (decod_instruction_t * inst, decod_param_t * param) |
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| 111 | { |
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| 112 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 113 | (* param->_function_decod[12][opcod]) (inst,param); |
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| 114 | } |
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| 115 | |
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| 116 | void instruction_decod_type_13 (decod_instruction_t * inst, decod_param_t * param) |
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| 117 | { |
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| 118 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6); |
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| 119 | (* param->_function_decod[13][opcod]) (inst,param); |
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| 120 | } |
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| 121 | |
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| 122 | void instruction_illegal (decod_instruction_t * inst, decod_param_t * param) |
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| 123 | { |
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| 124 | log_printf(TRACE,Decod,"instruction_illegal","instruction_illegal"); |
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| 125 | |
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| 126 | inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION; |
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[88] | 127 | inst->_exception = EXCEPTION_ILLEGAL_INSTRUCTION; |
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[78] | 128 | |
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| 129 | if (inst->_is_delay_slot) |
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| 130 | inst->_address_next = inst->_address_previous; |
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| 131 | else |
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| 132 | inst->_address_next = inst->_address; |
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| 133 | |
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| 134 | inst->_event_type = EVENT_TYPE_EXCEPTION; |
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| 135 | } |
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[86] | 136 | |
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| 137 | void instruction_l_custom (decod_instruction_t * inst, decod_param_t * param) |
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| 138 | { |
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| 139 | log_printf(TRACE,Decod,"instruction_l_custom"," * instruction : custom"); |
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| 140 | |
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| 141 | uint32_t opcod = range<uint32_t>(inst->_instruction,31,26); |
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[88] | 142 | |
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[86] | 143 | switch (opcod) |
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| 144 | { |
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[88] | 145 | case OPCOD_L_CUST1 : {inst->_type = instruction_information(INSTRUCTION_L_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST1)._operation; break;} |
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| 146 | case OPCOD_L_CUST2 : {inst->_type = instruction_information(INSTRUCTION_L_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST2)._operation; break;} |
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| 147 | case OPCOD_L_CUST3 : {inst->_type = instruction_information(INSTRUCTION_L_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST3)._operation; break;} |
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| 148 | case OPCOD_L_CUST4 : {inst->_type = instruction_information(INSTRUCTION_L_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST4)._operation; break;} |
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| 149 | case OPCOD_L_CUST5 : {inst->_type = instruction_information(INSTRUCTION_L_CUST5)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST5)._operation; break;} |
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| 150 | case OPCOD_L_CUST6 : {inst->_type = instruction_information(INSTRUCTION_L_CUST6)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST6)._operation; break;} |
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| 151 | case OPCOD_L_CUST7 : {inst->_type = instruction_information(INSTRUCTION_L_CUST7)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST7)._operation; break;} |
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| 152 | case OPCOD_L_CUST8 : {inst->_type = instruction_information(INSTRUCTION_L_CUST8)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST8)._operation; break;} |
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| 153 | |
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[86] | 154 | default : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));} |
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| 155 | } |
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| 156 | |
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| 157 | (* param->_function_custom[ 0][opcod]) (inst,param); |
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| 158 | |
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| 159 | instruction_custom(inst,param); |
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| 160 | } |
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| 161 | |
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| 162 | void instruction_lf_custom (decod_instruction_t * inst, decod_param_t * param) |
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| 163 | { |
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| 164 | log_printf(TRACE,Decod,"instruction_lf_custom"," * instruction : custom"); |
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| 165 | |
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| 166 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); |
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| 167 | |
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| 168 | switch (opcod) |
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| 169 | { |
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[88] | 170 | // case OPCOD_LF_CUST1_D : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_D)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_D)._operation; break;} |
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| 171 | // case OPCOD_LF_CUST1_S : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_S)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_S)._operation; break;} |
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[86] | 172 | default : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));} |
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| 173 | } |
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| 174 | |
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| 175 | (* param->_function_custom[ 1][opcod]) (inst,param); |
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| 176 | |
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| 177 | instruction_custom(inst,param); |
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| 178 | } |
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| 179 | |
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| 180 | void instruction_lv_custom (decod_instruction_t * inst, decod_param_t * param) |
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| 181 | { |
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| 182 | log_printf(TRACE,Decod,"instruction_lv_custom"," * instruction : custom"); |
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| 183 | |
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| 184 | uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); |
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| 185 | |
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| 186 | switch (opcod) |
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| 187 | { |
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[88] | 188 | // case OPCOD_LV_CUST1 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST1)._operation; break;} |
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| 189 | // case OPCOD_LV_CUST2 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST2)._operation; break;} |
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| 190 | // case OPCOD_LV_CUST3 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST3)._operation; break;} |
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| 191 | // case OPCOD_LV_CUST4 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST4)._operation; break;} |
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[86] | 192 | default : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));} |
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| 193 | } |
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| 194 | |
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| 195 | (* param->_function_custom[ 2][opcod]) (inst,param); |
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| 196 | |
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| 197 | instruction_custom(inst,param); |
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| 198 | } |
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| 199 | |
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| 200 | void instruction_custom (decod_instruction_t * inst, decod_param_t * param) |
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| 201 | { |
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| 202 | // Test custom operation |
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| 203 | |
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| 204 | std::string msg = ""; |
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| 205 | |
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| 206 | if (inst->_exception_use != EXCEPTION_USE_ILLEGAL_INSTRUCTION) |
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| 207 | { |
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| 208 | if (inst->_type != TYPE_CUSTOM) |
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| 209 | msg += _("Invalid Type.\n"); |
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| 210 | |
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| 211 | if ((inst->_operation != OPERATION_CUSTOM_L_1 ) and |
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| 212 | (inst->_operation != OPERATION_CUSTOM_L_2 ) and |
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| 213 | (inst->_operation != OPERATION_CUSTOM_L_3 ) and |
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| 214 | (inst->_operation != OPERATION_CUSTOM_L_4 ) and |
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| 215 | (inst->_operation != OPERATION_CUSTOM_L_5 ) and |
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| 216 | (inst->_operation != OPERATION_CUSTOM_L_6 ) and |
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| 217 | (inst->_operation != OPERATION_CUSTOM_L_7 ) and |
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| 218 | (inst->_operation != OPERATION_CUSTOM_L_8 ) and |
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| 219 | (inst->_operation != OPERATION_CUSTOM_LF_1_D) and |
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| 220 | (inst->_operation != OPERATION_CUSTOM_LF_1_S) and |
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| 221 | (inst->_operation != OPERATION_CUSTOM_LV_1 ) and |
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| 222 | (inst->_operation != OPERATION_CUSTOM_LV_2 ) and |
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| 223 | (inst->_operation != OPERATION_CUSTOM_LV_3 ) and |
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| 224 | (inst->_operation != OPERATION_CUSTOM_LV_4 )) |
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| 225 | msg += _("Invalid Operation.\n"); |
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| 226 | |
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| 227 | if ((inst->_exception_use != EXCEPTION_USE_NONE ) and |
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| 228 | (inst->_exception_use != EXCEPTION_USE_RANGE ) and |
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| 229 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_0 ) and |
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| 230 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_1 ) and |
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| 231 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_2 ) and |
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| 232 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_3 ) and |
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| 233 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_4 ) and |
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| 234 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_5 ) and |
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| 235 | (inst->_exception_use != EXCEPTION_USE_CUSTOM_6 )) |
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| 236 | msg += _("Invalid Exception.\n"); |
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| 237 | |
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| 238 | if ((inst->_event_type != EVENT_TYPE_NONE ) and |
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| 239 | (inst->_event_type != EVENT_TYPE_SPR_ACCESS)) |
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| 240 | msg += _("Invalid Event_type.\n"); |
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| 241 | |
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| 242 | if (inst->_address_next != (inst->_address+1)) |
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| 243 | msg += _("Address must be in sequence.\n"); |
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| 244 | |
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| 245 | if (msg != "") |
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| 246 | throw ERRORMORPHEO("instruction_custom","Invalid decod : "+msg); |
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| 247 | } |
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| 248 | } |
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[78] | 249 | |
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| 250 | // ORBIS |
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| 251 | void instruction_l_add (decod_instruction_t * inst, decod_param_t * param) |
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| 252 | { |
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| 253 | log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add"); |
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[88] | 254 | inst->_type = instruction_information(INSTRUCTION_L_ADD)._type ; //TYPE_ALU; |
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| 255 | inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; |
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[78] | 256 | inst->_has_immediat = 0; |
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| 257 | // inst->_immediat = ; |
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| 258 | inst->_read_ra = 1; |
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| 259 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 260 | inst->_read_rb = 1; |
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| 261 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
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| 262 | inst->_read_rc = 0; |
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| 263 | // inst->_num_reg_rc = ; |
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| 264 | inst->_write_rd = 1; |
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| 265 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 266 | inst->_write_re = 1; |
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| 267 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 268 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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[88] | 269 | inst->_exception = EXCEPTION_DECOD_NONE; |
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[78] | 270 | // inst->_branch_condition = ; |
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| 271 | // inst->_branch_stack_write = ; |
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| 272 | // inst->_branch_direction = ; |
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| 273 | // inst->_address_next = ; |
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[88] | 274 | inst->_no_execute = 0; |
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[78] | 275 | inst->_event_type = EVENT_TYPE_NONE; |
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| 276 | } |
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| 277 | |
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| 278 | void instruction_l_addc (decod_instruction_t * inst, decod_param_t * param) |
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| 279 | { |
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| 280 | log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc"); |
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| 281 | |
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[88] | 282 | inst->_type = instruction_information(INSTRUCTION_L_ADDC)._type ; //TYPE_ALU; |
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| 283 | inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; |
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[78] | 284 | inst->_has_immediat = 0; |
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| 285 | // inst->_immediat = ; |
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| 286 | inst->_read_ra = 1; |
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| 287 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 288 | inst->_read_rb = 1; |
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| 289 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
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| 290 | inst->_read_rc = 1; |
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| 291 | inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; |
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| 292 | inst->_write_rd = 1; |
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| 293 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 294 | inst->_write_re = 1; |
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| 295 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 296 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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[88] | 297 | inst->_exception = EXCEPTION_DECOD_NONE; |
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[78] | 298 | // inst->_branch_condition = ; |
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| 299 | // inst->_branch_stack_write = ; |
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| 300 | // inst->_branch_direction = ; |
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| 301 | // inst->_address_next = ; |
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[88] | 302 | inst->_no_execute = 0; |
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[78] | 303 | inst->_event_type = EVENT_TYPE_NONE; |
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| 304 | } |
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| 305 | |
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| 306 | void instruction_l_addi (decod_instruction_t * inst, decod_param_t * param) |
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| 307 | { |
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| 308 | log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi"); |
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| 309 | |
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[88] | 310 | inst->_type = instruction_information(INSTRUCTION_L_ADDI)._type ; //TYPE_ALU; |
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| 311 | inst->_operation = instruction_information(INSTRUCTION_L_ADDI)._operation; //OPERATION_ALU_L_ADD; |
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[78] | 312 | inst->_has_immediat = 1; |
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| 313 | inst->_immediat = EXTENDS(inst->_instruction,16); |
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| 314 | inst->_read_ra = 1; |
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| 315 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 316 | inst->_read_rb = 0; |
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| 317 | // inst->_num_reg_rb = ; |
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| 318 | inst->_read_rc = 0; |
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| 319 | // inst->_num_reg_rc = ; |
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| 320 | inst->_write_rd = 1; |
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| 321 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 322 | inst->_write_re = 1; |
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| 323 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 324 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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[88] | 325 | inst->_exception = EXCEPTION_DECOD_NONE; |
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[78] | 326 | // inst->_branch_condition = ; |
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| 327 | // inst->_branch_stack_write = ; |
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| 328 | // inst->_branch_direction = ; |
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| 329 | // inst->_address_next = ; |
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[88] | 330 | inst->_no_execute = 0; |
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[78] | 331 | inst->_event_type = EVENT_TYPE_NONE; |
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| 332 | } |
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| 333 | |
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| 334 | void instruction_l_addic (decod_instruction_t * inst, decod_param_t * param) |
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| 335 | { |
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| 336 | log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic"); |
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| 337 | |
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[88] | 338 | inst->_type = instruction_information(INSTRUCTION_L_ADDIC)._type ; //TYPE_ALU; |
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| 339 | inst->_operation = instruction_information(INSTRUCTION_L_ADDIC)._operation; //OPERATION_ALU_L_ADD; |
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[78] | 340 | inst->_has_immediat = 1; |
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| 341 | inst->_immediat = EXTENDS(inst->_instruction,16); |
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| 342 | inst->_read_ra = 1; |
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| 343 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
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| 344 | inst->_read_rb = 0; |
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| 345 | // inst->_num_reg_rb = ; |
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| 346 | inst->_read_rc = 1; |
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| 347 | inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; |
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| 348 | inst->_write_rd = 1; |
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| 349 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
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| 350 | inst->_write_re = 1; |
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| 351 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
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| 352 | inst->_exception_use = EXCEPTION_USE_RANGE; |
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[88] | 353 | inst->_exception = EXCEPTION_DECOD_NONE; |
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[78] | 354 | // inst->_branch_condition = ; |
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| 355 | // inst->_branch_stack_write = ; |
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| 356 | // inst->_branch_direction = ; |
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| 357 | // inst->_address_next = ; |
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[88] | 358 | inst->_no_execute = 0; |
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[78] | 359 | inst->_event_type = EVENT_TYPE_NONE; |
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| 360 | } |
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| 361 | |
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| 362 | void instruction_l_and (decod_instruction_t * inst, decod_param_t * param) |
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| 363 | { |
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| 364 | log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and"); |
---|
| 365 | |
---|
[88] | 366 | inst->_type = instruction_information(INSTRUCTION_L_AND)._type ; //TYPE_ALU; |
---|
| 367 | inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; |
---|
[78] | 368 | inst->_has_immediat = 0; |
---|
| 369 | // inst->_immediat = ; |
---|
| 370 | inst->_read_ra = 1; |
---|
| 371 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 372 | inst->_read_rb = 1; |
---|
| 373 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 374 | inst->_read_rc = 0; |
---|
| 375 | // inst->_num_reg_rc = ; |
---|
| 376 | inst->_write_rd = 1; |
---|
| 377 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 378 | inst->_write_re = 0; |
---|
| 379 | // inst->_num_reg_re = ; |
---|
| 380 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 381 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 382 | // inst->_branch_condition = ; |
---|
| 383 | // inst->_branch_stack_write = ; |
---|
| 384 | // inst->_branch_direction = ; |
---|
| 385 | // inst->_address_next = ; |
---|
[88] | 386 | inst->_no_execute = 0; |
---|
[78] | 387 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 388 | } |
---|
| 389 | |
---|
| 390 | void instruction_l_andi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 391 | { |
---|
| 392 | log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi"); |
---|
| 393 | |
---|
[88] | 394 | inst->_type = instruction_information(INSTRUCTION_L_ANDI)._type ; //TYPE_ALU; |
---|
| 395 | inst->_operation = instruction_information(INSTRUCTION_L_ANDI)._operation; //OPERATION_ALU_L_AND; |
---|
[78] | 396 | inst->_has_immediat = 1; |
---|
| 397 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 398 | inst->_read_ra = 1; |
---|
| 399 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 400 | inst->_read_rb = 0; |
---|
| 401 | // inst->_num_reg_rb = ; |
---|
| 402 | inst->_read_rc = 0; |
---|
| 403 | // inst->_num_reg_rc = ; |
---|
| 404 | inst->_write_rd = 1; |
---|
| 405 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 406 | inst->_write_re = 0; |
---|
| 407 | // inst->_num_reg_re = ; |
---|
| 408 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 409 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 410 | // inst->_branch_condition = ; |
---|
| 411 | // inst->_branch_stack_write = ; |
---|
| 412 | // inst->_branch_direction = ; |
---|
| 413 | // inst->_address_next = ; |
---|
[88] | 414 | inst->_no_execute = 0; |
---|
[78] | 415 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 416 | } |
---|
| 417 | |
---|
| 418 | void instruction_l_bf (decod_instruction_t * inst, decod_param_t * param) |
---|
| 419 | { |
---|
| 420 | log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf"); |
---|
| 421 | |
---|
[88] | 422 | Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 |
---|
| 423 | ); |
---|
[78] | 424 | |
---|
[88] | 425 | inst->_type = instruction_information(INSTRUCTION_L_BF)._type ; //TYPE_BRANCH; |
---|
| 426 | inst->_operation = instruction_information(INSTRUCTION_L_BF)._operation; //OPERATION_BRANCH_L_TEST_F; |
---|
[78] | 427 | inst->_has_immediat = 1; |
---|
| 428 | inst->_immediat = address_next; |
---|
| 429 | inst->_read_ra = 0; |
---|
| 430 | // inst->_num_reg_ra = ; |
---|
| 431 | inst->_read_rb = 0; |
---|
| 432 | // inst->_num_reg_rb = ; |
---|
| 433 | inst->_read_rc = 1; |
---|
| 434 | inst->_num_reg_rc = SPR_LOGIC_SR_F; |
---|
| 435 | inst->_write_rd = 0; |
---|
| 436 | // inst->_num_reg_rd = ; |
---|
| 437 | inst->_write_re = 0; |
---|
| 438 | // inst->_num_reg_re = ; |
---|
| 439 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 440 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 441 | inst->_branch_condition = BRANCH_CONDITION_FLAG_SET; |
---|
| 442 | // inst->_branch_stack_write = 0; |
---|
| 443 | |
---|
| 444 | inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25); |
---|
| 445 | inst->_address_next = address_next; |
---|
[88] | 446 | inst->_no_execute = 0; |
---|
[78] | 447 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 448 | } |
---|
| 449 | |
---|
| 450 | void instruction_l_bnf (decod_instruction_t * inst, decod_param_t * param) |
---|
| 451 | { |
---|
| 452 | log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf"); |
---|
| 453 | |
---|
[88] | 454 | Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 |
---|
| 455 | ); |
---|
[78] | 456 | |
---|
[88] | 457 | inst->_type = instruction_information(INSTRUCTION_L_BNF)._type ; //TYPE_BRANCH; |
---|
| 458 | inst->_operation = instruction_information(INSTRUCTION_L_BNF)._operation; //OPERATION_BRANCH_L_TEST_NF; |
---|
[78] | 459 | inst->_has_immediat = 1; |
---|
| 460 | inst->_immediat = address_next; |
---|
| 461 | inst->_read_ra = 0; |
---|
| 462 | // inst->_num_reg_ra = ; |
---|
| 463 | inst->_read_rb = 0; |
---|
| 464 | // inst->_num_reg_rb = ; |
---|
| 465 | inst->_read_rc = 1; |
---|
| 466 | inst->_num_reg_rc = SPR_LOGIC_SR_F; |
---|
| 467 | inst->_write_rd = 0; |
---|
| 468 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 469 | inst->_write_re = 0; |
---|
| 470 | // inst->_num_reg_re = ; |
---|
| 471 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 472 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 473 | inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET; |
---|
| 474 | // inst->_branch_stack_write = 0; |
---|
| 475 | inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25); |
---|
| 476 | inst->_address_next = address_next; |
---|
[88] | 477 | inst->_no_execute = 0; |
---|
[78] | 478 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 479 | } |
---|
| 480 | |
---|
| 481 | void instruction_l_cmov (decod_instruction_t * inst, decod_param_t * param) |
---|
| 482 | { |
---|
| 483 | log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov"); |
---|
| 484 | |
---|
[88] | 485 | inst->_type = instruction_information(INSTRUCTION_L_CMOV)._type ; //TYPE_MOVE; |
---|
| 486 | inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; |
---|
[78] | 487 | inst->_has_immediat = 0; |
---|
| 488 | // inst->_immediat = ; |
---|
| 489 | inst->_read_ra = 1; |
---|
| 490 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 491 | inst->_read_rb = 1; |
---|
| 492 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 493 | inst->_read_rc = 1; |
---|
| 494 | inst->_num_reg_rc = SPR_LOGIC_SR_F; |
---|
| 495 | inst->_write_rd = 1; |
---|
| 496 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 497 | inst->_write_re = 0; |
---|
| 498 | // inst->_num_reg_re = ; |
---|
| 499 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 500 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 501 | // inst->_branch_condition = ; |
---|
| 502 | // inst->_branch_stack_write = ; |
---|
| 503 | // inst->_branch_direction = ; |
---|
| 504 | // inst->_address_next = ; |
---|
[88] | 505 | inst->_no_execute = 0; |
---|
[78] | 506 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 507 | } |
---|
| 508 | |
---|
| 509 | void instruction_l_csync (decod_instruction_t * inst, decod_param_t * param) |
---|
| 510 | { |
---|
| 511 | log_printf(TRACE,Decod,"instruction_l_csync"," * instruction : l.csync"); |
---|
| 512 | |
---|
| 513 | if (range<Tinstruction_t>(inst->_instruction,23) != 0) |
---|
| 514 | { |
---|
| 515 | instruction_illegal (inst, param); |
---|
| 516 | } |
---|
| 517 | else |
---|
| 518 | { |
---|
[88] | 519 | inst->_type = instruction_information(INSTRUCTION_L_CSYNC)._type ; //TYPE_SPECIAL; |
---|
| 520 | inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; |
---|
[78] | 521 | inst->_has_immediat = 0; |
---|
| 522 | // inst->_immediat = ; |
---|
| 523 | inst->_read_ra = 0; |
---|
| 524 | // inst->_num_reg_ra = ; |
---|
| 525 | inst->_read_rb = 0; |
---|
| 526 | // inst->_num_reg_rb = ; |
---|
| 527 | inst->_read_rc = 0; |
---|
| 528 | // inst->_num_reg_rc = ; |
---|
| 529 | inst->_write_rd = 0; |
---|
| 530 | // inst->_num_reg_rd = ; |
---|
| 531 | inst->_write_re = 0; |
---|
| 532 | // inst->_num_reg_re = ; |
---|
| 533 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 534 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 535 | // inst->_branch_condition = ; |
---|
| 536 | // inst->_branch_stack_write = ; |
---|
| 537 | // inst->_branch_direction = ; |
---|
| 538 | // inst->_address_next = ; // don't change |
---|
[88] | 539 | inst->_no_execute = 0; |
---|
[78] | 540 | inst->_event_type = EVENT_TYPE_CSYNC; |
---|
| 541 | } |
---|
| 542 | } |
---|
| 543 | |
---|
| 544 | // void instruction_l_cust1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 545 | // void instruction_l_cust2 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 546 | // void instruction_l_cust3 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 547 | // void instruction_l_cust4 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 548 | // void instruction_l_cust5 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 549 | // void instruction_l_cust6 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 550 | // void instruction_l_cust7 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 551 | // void instruction_l_cust8 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 552 | |
---|
| 553 | void instruction_l_div (decod_instruction_t * inst, decod_param_t * param) |
---|
| 554 | { |
---|
| 555 | log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div"); |
---|
| 556 | |
---|
[88] | 557 | inst->_type = instruction_information(INSTRUCTION_L_DIV)._type ; //TYPE_DIV; |
---|
| 558 | inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; |
---|
[78] | 559 | inst->_has_immediat = 0; |
---|
| 560 | // inst->_immediat = ; |
---|
| 561 | inst->_read_ra = 1; |
---|
| 562 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 563 | inst->_read_rb = 1; |
---|
| 564 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 565 | inst->_read_rc = 0; |
---|
| 566 | // inst->_num_reg_rc = ; |
---|
| 567 | inst->_write_rd = 1; |
---|
| 568 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 569 | inst->_write_re = 1; |
---|
| 570 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 571 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
[88] | 572 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 573 | // inst->_branch_condition = ; |
---|
| 574 | // inst->_branch_stack_write = ; |
---|
| 575 | // inst->_branch_direction = ; |
---|
| 576 | // inst->_address_next = ; |
---|
[88] | 577 | inst->_no_execute = 0; |
---|
[78] | 578 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 579 | } |
---|
| 580 | |
---|
| 581 | void instruction_l_divu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 582 | { |
---|
| 583 | log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu"); |
---|
| 584 | |
---|
[88] | 585 | inst->_type = instruction_information(INSTRUCTION_L_DIVU)._type ; //TYPE_DIV; |
---|
| 586 | inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; |
---|
[78] | 587 | inst->_has_immediat = 0; |
---|
| 588 | // inst->_immediat = ; |
---|
| 589 | inst->_read_ra = 1; |
---|
| 590 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 591 | inst->_read_rb = 1; |
---|
| 592 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 593 | inst->_read_rc = 0; |
---|
| 594 | // inst->_num_reg_rc = ; |
---|
| 595 | inst->_write_rd = 1; |
---|
| 596 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 597 | inst->_write_re = 1; |
---|
| 598 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 599 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
[88] | 600 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 601 | // inst->_branch_condition = ; |
---|
| 602 | // inst->_branch_stack_write = ; |
---|
| 603 | // inst->_branch_direction = ; |
---|
| 604 | // inst->_address_next = ; |
---|
[88] | 605 | inst->_no_execute = 0; |
---|
[78] | 606 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 607 | } |
---|
| 608 | |
---|
| 609 | void instruction_l_extbs (decod_instruction_t * inst, decod_param_t * param) |
---|
| 610 | { |
---|
| 611 | log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs"); |
---|
| 612 | |
---|
[88] | 613 | inst->_type = instruction_information(INSTRUCTION_L_EXTBS)._type ; //TYPE_EXTEND; |
---|
| 614 | inst->_operation = instruction_information(INSTRUCTION_L_EXTBS)._operation; //OPERATION_EXTEND_L_EXTEND_S; |
---|
[78] | 615 | inst->_has_immediat = 1; |
---|
| 616 | inst->_immediat = 8; |
---|
| 617 | inst->_read_ra = 1; |
---|
| 618 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 619 | inst->_read_rb = 0; |
---|
| 620 | // inst->_num_reg_rb = ; |
---|
| 621 | inst->_read_rc = 0; |
---|
| 622 | // inst->_num_reg_rc = ; |
---|
| 623 | inst->_write_rd = 1; |
---|
| 624 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 625 | inst->_write_re = 0; |
---|
| 626 | // inst->_num_reg_re = ; |
---|
| 627 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 628 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 629 | // inst->_branch_condition = ; |
---|
| 630 | // inst->_branch_stack_write = ; |
---|
| 631 | // inst->_branch_direction = ; |
---|
| 632 | // inst->_address_next = ; |
---|
[88] | 633 | inst->_no_execute = 0; |
---|
[78] | 634 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 635 | } |
---|
| 636 | |
---|
| 637 | void instruction_l_extbz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 638 | { |
---|
| 639 | log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz"); |
---|
| 640 | |
---|
[88] | 641 | inst->_type = instruction_information(INSTRUCTION_L_EXTBZ)._type ; //TYPE_EXTEND; |
---|
| 642 | inst->_operation = instruction_information(INSTRUCTION_L_EXTBZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; |
---|
[78] | 643 | inst->_has_immediat = 1; |
---|
| 644 | inst->_immediat = 8; |
---|
| 645 | inst->_read_ra = 1; |
---|
| 646 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 647 | inst->_read_rb = 0; |
---|
| 648 | // inst->_num_reg_rb = ; |
---|
| 649 | inst->_read_rc = 0; |
---|
| 650 | // inst->_num_reg_rc = ; |
---|
| 651 | inst->_write_rd = 1; |
---|
| 652 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 653 | inst->_write_re = 0; |
---|
| 654 | // inst->_num_reg_re = ; |
---|
| 655 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 656 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 657 | // inst->_branch_condition = ; |
---|
| 658 | // inst->_branch_stack_write = ; |
---|
| 659 | // inst->_branch_direction = ; |
---|
| 660 | // inst->_address_next = ; |
---|
[88] | 661 | inst->_no_execute = 0; |
---|
[78] | 662 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 663 | } |
---|
| 664 | |
---|
| 665 | void instruction_l_exths (decod_instruction_t * inst, decod_param_t * param) |
---|
| 666 | { |
---|
| 667 | log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths"); |
---|
| 668 | |
---|
[88] | 669 | inst->_type = instruction_information(INSTRUCTION_L_EXTHS)._type ; //TYPE_EXTEND; |
---|
| 670 | inst->_operation = instruction_information(INSTRUCTION_L_EXTHS)._operation; //OPERATION_EXTEND_L_EXTEND_S; |
---|
[78] | 671 | inst->_has_immediat = 1; |
---|
| 672 | inst->_immediat = 16; |
---|
| 673 | inst->_read_ra = 1; |
---|
| 674 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 675 | inst->_read_rb = 0; |
---|
| 676 | // inst->_num_reg_rb = ; |
---|
| 677 | inst->_read_rc = 0; |
---|
| 678 | // inst->_num_reg_rc = ; |
---|
| 679 | inst->_write_rd = 1; |
---|
| 680 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 681 | inst->_write_re = 0; |
---|
| 682 | // inst->_num_reg_re = ; |
---|
| 683 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 684 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 685 | // inst->_branch_condition = ; |
---|
| 686 | // inst->_branch_stack_write = ; |
---|
| 687 | // inst->_branch_direction = ; |
---|
| 688 | // inst->_address_next = ; |
---|
[88] | 689 | inst->_no_execute = 0; |
---|
[78] | 690 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 691 | } |
---|
| 692 | |
---|
| 693 | void instruction_l_exthz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 694 | { |
---|
| 695 | log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz"); |
---|
| 696 | |
---|
[88] | 697 | inst->_type = instruction_information(INSTRUCTION_L_EXTHZ)._type ; //TYPE_EXTEND; |
---|
| 698 | inst->_operation = instruction_information(INSTRUCTION_L_EXTHZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; |
---|
[78] | 699 | inst->_has_immediat = 1; |
---|
| 700 | inst->_immediat = 16; |
---|
| 701 | inst->_read_ra = 1; |
---|
| 702 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 703 | inst->_read_rb = 0; |
---|
| 704 | // inst->_num_reg_rb = ; |
---|
| 705 | inst->_read_rc = 0; |
---|
| 706 | // inst->_num_reg_rc = ; |
---|
| 707 | inst->_write_rd = 1; |
---|
| 708 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 709 | inst->_write_re = 0; |
---|
| 710 | // inst->_num_reg_re = ; |
---|
| 711 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 712 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 713 | // inst->_branch_condition = ; |
---|
| 714 | // inst->_branch_stack_write = ; |
---|
| 715 | // inst->_branch_direction = ; |
---|
| 716 | // inst->_address_next = ; |
---|
[88] | 717 | inst->_no_execute = 0; |
---|
[78] | 718 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 719 | } |
---|
| 720 | |
---|
| 721 | void instruction_l_extws (decod_instruction_t * inst, decod_param_t * param) |
---|
| 722 | { |
---|
| 723 | log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws"); |
---|
| 724 | |
---|
[88] | 725 | inst->_type = instruction_information(INSTRUCTION_L_EXTWS)._type ; //TYPE_EXTEND; |
---|
| 726 | inst->_operation = instruction_information(INSTRUCTION_L_EXTWS)._operation; //OPERATION_EXTEND_L_EXTEND_S; |
---|
[78] | 727 | inst->_has_immediat = 1; |
---|
| 728 | inst->_immediat = 32; |
---|
| 729 | inst->_read_ra = 1; |
---|
| 730 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 731 | inst->_read_rb = 0; |
---|
| 732 | // inst->_num_reg_rb = ; |
---|
| 733 | inst->_read_rc = 0; |
---|
| 734 | // inst->_num_reg_rc = ; |
---|
| 735 | inst->_write_rd = 1; |
---|
| 736 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 737 | inst->_write_re = 0; |
---|
| 738 | // inst->_num_reg_re = ; |
---|
| 739 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 740 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 741 | // inst->_branch_condition = ; |
---|
| 742 | // inst->_branch_stack_write = ; |
---|
| 743 | // inst->_branch_direction = ; |
---|
| 744 | // inst->_address_next = ; |
---|
[88] | 745 | inst->_no_execute = 0; |
---|
[78] | 746 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 747 | } |
---|
| 748 | |
---|
| 749 | void instruction_l_extwz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 750 | { |
---|
| 751 | log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz"); |
---|
| 752 | |
---|
[88] | 753 | inst->_type = instruction_information(INSTRUCTION_L_EXTWZ)._type ; //TYPE_EXTEND; |
---|
| 754 | inst->_operation = instruction_information(INSTRUCTION_L_EXTWZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; |
---|
[78] | 755 | inst->_has_immediat = 1; |
---|
| 756 | inst->_immediat = 32; |
---|
| 757 | inst->_read_ra = 1; |
---|
| 758 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 759 | inst->_read_rb = 0; |
---|
| 760 | // inst->_num_reg_rb = ; |
---|
| 761 | inst->_read_rc = 0; |
---|
| 762 | // inst->_num_reg_rc = ; |
---|
| 763 | inst->_write_rd = 1; |
---|
| 764 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 765 | inst->_write_re = 0; |
---|
| 766 | // inst->_num_reg_re = ; |
---|
| 767 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 768 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 769 | // inst->_branch_condition = ; |
---|
| 770 | // inst->_branch_stack_write = ; |
---|
| 771 | // inst->_branch_direction = ; |
---|
| 772 | // inst->_address_next = ; |
---|
[88] | 773 | inst->_no_execute = 0; |
---|
[78] | 774 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 775 | } |
---|
| 776 | |
---|
| 777 | void instruction_l_ff1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 778 | { |
---|
| 779 | log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1"); |
---|
| 780 | |
---|
[88] | 781 | inst->_type = instruction_information(INSTRUCTION_L_FF1)._type ; //TYPE_FIND; |
---|
| 782 | inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; |
---|
[78] | 783 | inst->_has_immediat = 0; |
---|
| 784 | // inst->_immediat = ; |
---|
| 785 | inst->_read_ra = 1; |
---|
| 786 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 787 | inst->_read_rb = 0; |
---|
| 788 | // inst->_num_reg_rb = ; |
---|
| 789 | inst->_read_rc = 0; |
---|
| 790 | // inst->_num_reg_rc = ; |
---|
| 791 | inst->_write_rd = 1; |
---|
| 792 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 793 | inst->_write_re = 0; |
---|
| 794 | // inst->_num_reg_re = ; |
---|
| 795 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 796 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 797 | // inst->_branch_condition = ; |
---|
| 798 | // inst->_branch_stack_write = ; |
---|
| 799 | // inst->_branch_direction = ; |
---|
| 800 | // inst->_address_next = ; |
---|
[88] | 801 | inst->_no_execute = 0; |
---|
[78] | 802 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 803 | } |
---|
| 804 | |
---|
| 805 | void instruction_l_fl1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 806 | { |
---|
| 807 | log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1"); |
---|
| 808 | |
---|
[88] | 809 | inst->_type = instruction_information(INSTRUCTION_L_FL1)._type ; //TYPE_FIND; |
---|
| 810 | inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; |
---|
[78] | 811 | inst->_has_immediat = 0; |
---|
| 812 | // inst->_immediat = ; |
---|
| 813 | inst->_read_ra = 1; |
---|
| 814 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 815 | inst->_read_rb = 0; |
---|
| 816 | // inst->_num_reg_rb = ; |
---|
| 817 | inst->_read_rc = 0; |
---|
| 818 | // inst->_num_reg_rc = ; |
---|
| 819 | inst->_write_rd = 1; |
---|
| 820 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 821 | inst->_write_re = 0; |
---|
| 822 | // inst->_num_reg_re = ; |
---|
| 823 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 824 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 825 | // inst->_branch_condition = ; |
---|
| 826 | // inst->_branch_stack_write = ; |
---|
| 827 | // inst->_branch_direction = ; |
---|
| 828 | // inst->_address_next = ; |
---|
[88] | 829 | inst->_no_execute = 0; |
---|
[78] | 830 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 831 | } |
---|
| 832 | |
---|
| 833 | void instruction_l_j (decod_instruction_t * inst, decod_param_t * param) |
---|
| 834 | { |
---|
| 835 | log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j"); |
---|
| 836 | |
---|
[88] | 837 | inst->_type = instruction_information(INSTRUCTION_L_J)._type ; //TYPE_BRANCH; |
---|
| 838 | inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; |
---|
[78] | 839 | inst->_has_immediat = 0; |
---|
| 840 | // inst->_immediat = ; |
---|
| 841 | inst->_read_ra = 0; |
---|
| 842 | // inst->_num_reg_ra = ; |
---|
| 843 | inst->_read_rb = 0; |
---|
| 844 | // inst->_num_reg_rb = ; |
---|
| 845 | inst->_read_rc = 0; |
---|
| 846 | // inst->_num_reg_rc = ; |
---|
| 847 | inst->_write_rd = 0; |
---|
| 848 | // inst->_num_reg_rd = ; |
---|
| 849 | inst->_write_re = 0; |
---|
| 850 | // inst->_num_reg_re = ; |
---|
| 851 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 852 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 853 | inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK; |
---|
| 854 | // inst->_branch_stack_write = 0; |
---|
| 855 | inst->_branch_direction = 1; |
---|
[88] | 856 | inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 |
---|
| 857 | ); |
---|
| 858 | inst->_no_execute = 1; |
---|
[78] | 859 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 860 | } |
---|
| 861 | |
---|
| 862 | void instruction_l_jal (decod_instruction_t * inst, decod_param_t * param) |
---|
| 863 | { |
---|
| 864 | log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal"); |
---|
| 865 | |
---|
[88] | 866 | inst->_type = instruction_information(INSTRUCTION_L_JAL)._type ; //TYPE_BRANCH; |
---|
| 867 | inst->_operation = instruction_information(INSTRUCTION_L_JAL)._operation; //OPERATION_BRANCH_L_JALR; |
---|
[78] | 868 | inst->_has_immediat = 1; |
---|
[86] | 869 | inst->_immediat = inst->_address_next+1; |
---|
[78] | 870 | inst->_read_ra = 0; |
---|
| 871 | // inst->_num_reg_ra = ; |
---|
| 872 | inst->_read_rb = 0; |
---|
| 873 | // inst->_num_reg_rb = ; |
---|
| 874 | inst->_read_rc = 0; |
---|
| 875 | // inst->_num_reg_rc = ; |
---|
| 876 | inst->_write_rd = 1; |
---|
| 877 | inst->_num_reg_rd = 9; // Link register |
---|
| 878 | inst->_write_re = 0; |
---|
| 879 | // inst->_num_reg_re = ; |
---|
| 880 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 881 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 882 | inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump |
---|
| 883 | // inst->_branch_stack_write = 1; |
---|
| 884 | inst->_branch_direction = 1; |
---|
[88] | 885 | inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 |
---|
| 886 | ); |
---|
| 887 | inst->_no_execute = 0; |
---|
[78] | 888 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 889 | } |
---|
| 890 | |
---|
| 891 | void instruction_l_jalr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 892 | { |
---|
| 893 | log_printf(TRACE,Decod,"instruction_l_jalr"," * instruction : l.jalr"); |
---|
| 894 | |
---|
| 895 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 896 | |
---|
| 897 | if (inst->_num_reg_rb == 9) |
---|
| 898 | { |
---|
| 899 | instruction_illegal (inst, param); |
---|
| 900 | } |
---|
| 901 | else |
---|
| 902 | { |
---|
[88] | 903 | inst->_type = instruction_information(INSTRUCTION_L_JALR)._type ; //TYPE_BRANCH; |
---|
| 904 | inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; |
---|
[78] | 905 | inst->_has_immediat = 0; |
---|
| 906 | // inst->_immediat = ; |
---|
| 907 | inst->_read_ra = 0; |
---|
| 908 | // inst->_num_reg_ra = ; |
---|
| 909 | inst->_read_rb = 1; |
---|
| 910 | // inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 911 | inst->_read_rc = 0; |
---|
| 912 | // inst->_num_reg_rc = ; |
---|
| 913 | inst->_write_rd = 1; |
---|
| 914 | inst->_num_reg_rd = 9; // Link register |
---|
| 915 | inst->_write_re = 0; |
---|
| 916 | // inst->_num_reg_re = ; |
---|
| 917 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 918 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 919 | // inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER; |
---|
| 920 | inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK; |
---|
| 921 | // inst->_branch_stack_write = 1; |
---|
| 922 | inst->_branch_direction = 1; |
---|
| 923 | // inst->_address_next = ; |
---|
[88] | 924 | inst->_no_execute = 0; |
---|
[78] | 925 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 926 | } |
---|
| 927 | } |
---|
| 928 | |
---|
| 929 | void instruction_l_jr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 930 | { |
---|
| 931 | log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr"); |
---|
| 932 | |
---|
[88] | 933 | inst->_type = instruction_information(INSTRUCTION_L_JR)._type ; //TYPE_BRANCH; |
---|
| 934 | inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; |
---|
[78] | 935 | inst->_has_immediat = 0; |
---|
| 936 | // inst->_immediat = ; |
---|
| 937 | inst->_read_ra = 0; |
---|
| 938 | // inst->_num_reg_ra = ; |
---|
| 939 | inst->_read_rb = 1; |
---|
| 940 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 941 | inst->_read_rc = 0; |
---|
| 942 | // inst->_num_reg_rc = ; |
---|
| 943 | inst->_write_rd = 0; |
---|
| 944 | // inst->_num_reg_rd = ; |
---|
| 945 | inst->_write_re = 0; |
---|
| 946 | // inst->_num_reg_re = ; |
---|
| 947 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 948 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 949 | inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK; |
---|
| 950 | // inst->_branch_stack_write = 0; |
---|
| 951 | inst->_branch_direction = 1; |
---|
| 952 | // inst->_address_next = ; |
---|
[88] | 953 | inst->_no_execute = 0; |
---|
[78] | 954 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 955 | } |
---|
| 956 | |
---|
| 957 | void instruction_l_lbs (decod_instruction_t * inst, decod_param_t * param) |
---|
| 958 | { |
---|
| 959 | log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs"); |
---|
| 960 | |
---|
[88] | 961 | inst->_type = instruction_information(INSTRUCTION_L_LBS)._type ; //TYPE_MEMORY; |
---|
| 962 | inst->_operation = instruction_information(INSTRUCTION_L_LBS)._operation; //OPERATION_MEMORY_LOAD_8_S; |
---|
[78] | 963 | inst->_has_immediat = 1; |
---|
| 964 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 965 | inst->_read_ra = 1; |
---|
| 966 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 967 | inst->_read_rb = 0; |
---|
| 968 | // inst->_num_reg_rb = ; |
---|
| 969 | inst->_read_rc = 0; |
---|
| 970 | // inst->_num_reg_rc = ; |
---|
| 971 | inst->_write_rd = 1; |
---|
| 972 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 973 | inst->_write_re = 0; |
---|
| 974 | // inst->_num_reg_re = ; |
---|
| 975 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; |
---|
[88] | 976 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 977 | // inst->_branch_condition = ; |
---|
| 978 | // inst->_branch_stack_write = ; |
---|
| 979 | // inst->_branch_direction = ; |
---|
| 980 | // inst->_address_next = ; |
---|
[88] | 981 | inst->_no_execute = 0; |
---|
[78] | 982 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 983 | } |
---|
| 984 | |
---|
| 985 | void instruction_l_lbz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 986 | { |
---|
| 987 | log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz"); |
---|
| 988 | |
---|
[88] | 989 | inst->_type = instruction_information(INSTRUCTION_L_LBZ)._type ; //TYPE_MEMORY; |
---|
| 990 | inst->_operation = instruction_information(INSTRUCTION_L_LBZ)._operation; //OPERATION_MEMORY_LOAD_8_Z; |
---|
[78] | 991 | inst->_has_immediat = 1; |
---|
| 992 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 993 | inst->_read_ra = 1; |
---|
| 994 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 995 | inst->_read_rb = 0; |
---|
| 996 | // inst->_num_reg_rb = ; |
---|
| 997 | inst->_read_rc = 0; |
---|
| 998 | // inst->_num_reg_rc = ; |
---|
| 999 | inst->_write_rd = 1; |
---|
| 1000 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1001 | inst->_write_re = 0; |
---|
| 1002 | // inst->_num_reg_re = ; |
---|
| 1003 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; |
---|
[88] | 1004 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1005 | // inst->_branch_condition = ; |
---|
| 1006 | // inst->_branch_stack_write = ; |
---|
| 1007 | // inst->_branch_direction = ; |
---|
| 1008 | // inst->_address_next = ; |
---|
[88] | 1009 | inst->_no_execute = 0; |
---|
[78] | 1010 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1011 | } |
---|
| 1012 | |
---|
| 1013 | void instruction_l_ld (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1014 | { |
---|
| 1015 | log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld"); |
---|
| 1016 | |
---|
[88] | 1017 | inst->_type = instruction_information(INSTRUCTION_L_LD)._type ; //TYPE_MEMORY; |
---|
| 1018 | inst->_operation = instruction_information(INSTRUCTION_L_LD)._operation; //OPERATION_MEMORY_LOAD_64_S; |
---|
[78] | 1019 | inst->_has_immediat = 1; |
---|
| 1020 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1021 | inst->_read_ra = 1; |
---|
| 1022 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1023 | inst->_read_rb = 0; |
---|
| 1024 | // inst->_num_reg_rb = ; |
---|
| 1025 | inst->_read_rc = 0; |
---|
| 1026 | // inst->_num_reg_rc = ; |
---|
| 1027 | inst->_write_rd = 1; |
---|
| 1028 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1029 | inst->_write_re = 0; |
---|
| 1030 | // inst->_num_reg_re = ; |
---|
| 1031 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 1032 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1033 | // inst->_branch_condition = ; |
---|
| 1034 | // inst->_branch_stack_write = ; |
---|
| 1035 | // inst->_branch_direction = ; |
---|
| 1036 | // inst->_address_next = ; |
---|
[88] | 1037 | inst->_no_execute = 0; |
---|
[78] | 1038 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1039 | } |
---|
| 1040 | |
---|
| 1041 | void instruction_l_lhs (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1042 | { |
---|
| 1043 | log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs"); |
---|
| 1044 | |
---|
[88] | 1045 | inst->_type = instruction_information(INSTRUCTION_L_LHS)._type ; //TYPE_MEMORY; |
---|
| 1046 | inst->_operation = instruction_information(INSTRUCTION_L_LHS)._operation; //OPERATION_MEMORY_LOAD_16_S; |
---|
[78] | 1047 | inst->_has_immediat = 1; |
---|
| 1048 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1049 | inst->_read_ra = 1; |
---|
| 1050 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1051 | inst->_read_rb = 0; |
---|
| 1052 | // inst->_num_reg_rb = ; |
---|
| 1053 | inst->_read_rc = 0; |
---|
| 1054 | // inst->_num_reg_rc = ; |
---|
| 1055 | inst->_write_rd = 1; |
---|
| 1056 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1057 | inst->_write_re = 0; |
---|
| 1058 | // inst->_num_reg_re = ; |
---|
| 1059 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 1060 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1061 | // inst->_branch_condition = ; |
---|
| 1062 | // inst->_branch_stack_write = ; |
---|
| 1063 | // inst->_branch_direction = ; |
---|
| 1064 | // inst->_address_next = ; |
---|
[88] | 1065 | inst->_no_execute = 0; |
---|
[78] | 1066 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1067 | } |
---|
| 1068 | |
---|
| 1069 | void instruction_l_lhz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1070 | { |
---|
| 1071 | log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz"); |
---|
| 1072 | |
---|
[88] | 1073 | inst->_type = instruction_information(INSTRUCTION_L_LHZ)._type ; //TYPE_MEMORY; |
---|
| 1074 | inst->_operation = instruction_information(INSTRUCTION_L_LHZ)._operation; //OPERATION_MEMORY_LOAD_16_Z; |
---|
[78] | 1075 | inst->_has_immediat = 1; |
---|
| 1076 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1077 | inst->_read_ra = 1; |
---|
| 1078 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1079 | inst->_read_rb = 0; |
---|
| 1080 | // inst->_num_reg_rb = ; |
---|
| 1081 | inst->_read_rc = 0; |
---|
| 1082 | // inst->_num_reg_rc = ; |
---|
| 1083 | inst->_write_rd = 1; |
---|
| 1084 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1085 | inst->_write_re = 0; |
---|
| 1086 | // inst->_num_reg_re = ; |
---|
| 1087 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 1088 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1089 | // inst->_branch_condition = ; |
---|
| 1090 | // inst->_branch_stack_write = ; |
---|
| 1091 | // inst->_branch_direction = ; |
---|
| 1092 | // inst->_address_next = ; |
---|
[88] | 1093 | inst->_no_execute = 0; |
---|
[78] | 1094 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1095 | } |
---|
| 1096 | |
---|
| 1097 | void instruction_l_lws (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1098 | { |
---|
| 1099 | log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws"); |
---|
| 1100 | |
---|
[88] | 1101 | inst->_type = instruction_information(INSTRUCTION_L_LWS)._type ; //TYPE_MEMORY; |
---|
| 1102 | inst->_operation = instruction_information(INSTRUCTION_L_LWS)._operation; //OPERATION_MEMORY_LOAD_32_S; |
---|
[78] | 1103 | inst->_has_immediat = 1; |
---|
| 1104 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1105 | inst->_read_ra = 1; |
---|
| 1106 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1107 | inst->_read_rb = 0; |
---|
| 1108 | // inst->_num_reg_rb = ; |
---|
| 1109 | inst->_read_rc = 0; |
---|
| 1110 | // inst->_num_reg_rc = ; |
---|
| 1111 | inst->_write_rd = 1; |
---|
| 1112 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1113 | inst->_write_re = 0; |
---|
| 1114 | // inst->_num_reg_re = ; |
---|
| 1115 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 1116 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1117 | // inst->_branch_condition = ; |
---|
| 1118 | // inst->_branch_stack_write = ; |
---|
| 1119 | // inst->_branch_direction = ; |
---|
| 1120 | // inst->_address_next = ; |
---|
[88] | 1121 | inst->_no_execute = 0; |
---|
[78] | 1122 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1123 | } |
---|
| 1124 | |
---|
| 1125 | void instruction_l_lwz (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1126 | { |
---|
| 1127 | log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz"); |
---|
| 1128 | |
---|
[88] | 1129 | inst->_type = instruction_information(INSTRUCTION_L_LWZ)._type ; //TYPE_MEMORY; |
---|
| 1130 | inst->_operation = instruction_information(INSTRUCTION_L_LWZ)._operation; //OPERATION_MEMORY_LOAD_32_Z; |
---|
[78] | 1131 | inst->_has_immediat = 1; |
---|
| 1132 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1133 | inst->_read_ra = 1; |
---|
| 1134 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1135 | inst->_read_rb = 0; |
---|
| 1136 | // inst->_num_reg_rb = ; |
---|
| 1137 | inst->_read_rc = 0; |
---|
| 1138 | // inst->_num_reg_rc = ; |
---|
| 1139 | inst->_write_rd = 1; |
---|
| 1140 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1141 | inst->_write_re = 0; |
---|
| 1142 | // inst->_num_reg_re = ; |
---|
| 1143 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 1144 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1145 | // inst->_branch_condition = ; |
---|
| 1146 | // inst->_branch_stack_write = ; |
---|
| 1147 | // inst->_branch_direction = ; |
---|
| 1148 | // inst->_address_next = ; |
---|
[88] | 1149 | inst->_no_execute = 0; |
---|
[78] | 1150 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1151 | } |
---|
| 1152 | |
---|
| 1153 | void instruction_l_mac (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1154 | { |
---|
| 1155 | log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac"); |
---|
| 1156 | |
---|
[88] | 1157 | inst->_type = instruction_information(INSTRUCTION_L_MAC)._type ; //TYPE_SPECIAL; |
---|
| 1158 | inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; |
---|
[78] | 1159 | inst->_has_immediat = 0; |
---|
| 1160 | // inst->_immediat = ; |
---|
| 1161 | inst->_read_ra = 1; |
---|
| 1162 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1163 | inst->_read_rb = 1; |
---|
| 1164 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1165 | inst->_read_rc = 0; |
---|
| 1166 | // inst->_num_reg_rc = ; |
---|
| 1167 | inst->_write_rd = 0; |
---|
| 1168 | // inst->_num_reg_rd = ; |
---|
| 1169 | inst->_write_re = 0; |
---|
| 1170 | // inst->_num_reg_re = ; |
---|
| 1171 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1172 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1173 | // inst->_branch_condition = ; |
---|
| 1174 | // inst->_branch_stack_write = ; |
---|
| 1175 | // inst->_branch_direction = ; |
---|
| 1176 | // inst->_address_next = ; // don't change |
---|
[88] | 1177 | inst->_no_execute = 0; |
---|
[78] | 1178 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1179 | } |
---|
| 1180 | |
---|
| 1181 | void instruction_l_maci (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1182 | { |
---|
| 1183 | log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci"); |
---|
| 1184 | |
---|
[88] | 1185 | inst->_type = instruction_information(INSTRUCTION_L_MACI)._type ; //TYPE_SPECIAL; |
---|
| 1186 | inst->_operation = instruction_information(INSTRUCTION_L_MACI)._operation; //OPERATION_SPECIAL_L_MAC; |
---|
[78] | 1187 | inst->_has_immediat = 1; |
---|
| 1188 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1189 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1190 | inst->_read_ra = 1; |
---|
| 1191 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1192 | inst->_read_rb = 0; |
---|
| 1193 | // inst->_num_reg_rb = ; |
---|
| 1194 | inst->_read_rc = 0; |
---|
| 1195 | // inst->_num_reg_rc = ; |
---|
| 1196 | inst->_write_rd = 0; |
---|
| 1197 | // inst->_num_reg_rd = ; |
---|
| 1198 | inst->_write_re = 0; |
---|
| 1199 | // inst->_num_reg_re = ; |
---|
| 1200 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1201 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1202 | // inst->_branch_condition = ; |
---|
| 1203 | // inst->_branch_stack_write = ; |
---|
| 1204 | // inst->_branch_direction = ; |
---|
| 1205 | // inst->_address_next = ; // don't change |
---|
[88] | 1206 | inst->_no_execute = 0; |
---|
[78] | 1207 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1208 | } |
---|
| 1209 | |
---|
| 1210 | void instruction_l_macrc (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1211 | { |
---|
| 1212 | log_printf(TRACE,Decod,"instruction_l_macrc"," * instruction : l.macrc"); |
---|
| 1213 | |
---|
| 1214 | if (range<uint32_t>(inst->_instruction,15, 0) != 0) |
---|
| 1215 | { |
---|
| 1216 | instruction_illegal (inst, param); |
---|
| 1217 | } |
---|
| 1218 | else |
---|
| 1219 | { |
---|
[88] | 1220 | inst->_type = instruction_information(INSTRUCTION_L_MACRC)._type ; //TYPE_SPECIAL; |
---|
| 1221 | inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; |
---|
[78] | 1222 | inst->_has_immediat = 0; |
---|
| 1223 | // inst->_immediat = ; |
---|
| 1224 | inst->_read_ra = 0; |
---|
| 1225 | // inst->_num_reg_ra = ; |
---|
| 1226 | inst->_read_rb = 0; |
---|
| 1227 | // inst->_num_reg_rb = ; |
---|
| 1228 | inst->_read_rc = 0; |
---|
| 1229 | // inst->_num_reg_rc = ; |
---|
| 1230 | inst->_write_rd = 1; |
---|
| 1231 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1232 | inst->_write_re = 0; |
---|
| 1233 | // inst->_num_reg_re = ; |
---|
| 1234 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1235 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1236 | // inst->_branch_condition = ; |
---|
| 1237 | // inst->_branch_stack_write = ; |
---|
| 1238 | // inst->_branch_direction = ; |
---|
| 1239 | // inst->_address_next = ; // don't change |
---|
[88] | 1240 | inst->_no_execute = 0; |
---|
[78] | 1241 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1242 | } |
---|
| 1243 | } |
---|
| 1244 | |
---|
| 1245 | void instruction_l_mfspr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1246 | { |
---|
| 1247 | log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr"); |
---|
| 1248 | |
---|
[88] | 1249 | inst->_type = instruction_information(INSTRUCTION_L_MFSPR)._type ; //TYPE_SPECIAL; |
---|
| 1250 | inst->_operation = instruction_information(INSTRUCTION_L_MFSPR)._operation; //OPERATION_SPECIAL_L_MFSPR; |
---|
[78] | 1251 | inst->_has_immediat = 1; |
---|
| 1252 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1253 | inst->_read_ra = 1; |
---|
| 1254 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1255 | inst->_read_rb = 0; |
---|
| 1256 | // inst->_num_reg_rb = ; |
---|
| 1257 | inst->_read_rc = 0; |
---|
| 1258 | // inst->_num_reg_rc = ; |
---|
| 1259 | inst->_write_rd = 1; |
---|
| 1260 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1261 | inst->_write_re = 0; |
---|
| 1262 | // inst->_num_reg_re = ; |
---|
| 1263 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1264 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1265 | // inst->_branch_condition = ; |
---|
| 1266 | // inst->_branch_stack_write = ; |
---|
| 1267 | // inst->_branch_direction = ; |
---|
| 1268 | // inst->_address_next = ; // don't change |
---|
[88] | 1269 | inst->_no_execute = 0; |
---|
[78] | 1270 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1271 | } |
---|
| 1272 | |
---|
| 1273 | void instruction_l_movhi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1274 | { |
---|
| 1275 | log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi"); |
---|
| 1276 | |
---|
[88] | 1277 | inst->_type = instruction_information(INSTRUCTION_L_MOVHI)._type ; //TYPE_MOVE; |
---|
| 1278 | inst->_operation = instruction_information(INSTRUCTION_L_MOVHI)._operation; //OPERATION_MOVE_L_MOVHI; |
---|
[78] | 1279 | inst->_has_immediat = 1; |
---|
| 1280 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1281 | inst->_read_ra = 0; |
---|
| 1282 | // inst->_num_reg_ra = ; |
---|
| 1283 | inst->_read_rb = 0; |
---|
| 1284 | // inst->_num_reg_rb = ; |
---|
| 1285 | inst->_read_rc = 0; |
---|
| 1286 | // inst->_num_reg_rc = ; |
---|
| 1287 | inst->_write_rd = 1; |
---|
| 1288 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1289 | inst->_write_re = 0; |
---|
| 1290 | // inst->_num_reg_re = ; |
---|
| 1291 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1292 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1293 | // inst->_branch_condition = ; |
---|
| 1294 | // inst->_branch_stack_write = ; |
---|
| 1295 | // inst->_branch_direction = ; |
---|
| 1296 | // inst->_address_next = ; |
---|
[88] | 1297 | inst->_no_execute = 0; |
---|
[78] | 1298 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1299 | } |
---|
| 1300 | |
---|
| 1301 | void instruction_l_msb (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1302 | { |
---|
| 1303 | log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb"); |
---|
| 1304 | |
---|
[88] | 1305 | inst->_type = instruction_information(INSTRUCTION_L_MSB)._type ; //TYPE_SPECIAL; |
---|
| 1306 | inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; |
---|
[78] | 1307 | inst->_has_immediat = 0; |
---|
| 1308 | // inst->_immediat = ; |
---|
| 1309 | inst->_read_ra = 1; |
---|
| 1310 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1311 | inst->_read_rb = 1; |
---|
| 1312 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1313 | inst->_read_rc = 0; |
---|
| 1314 | // inst->_num_reg_rc = ; |
---|
| 1315 | inst->_write_rd = 0; |
---|
| 1316 | // inst->_num_reg_rd = ; |
---|
| 1317 | inst->_write_re = 0; |
---|
| 1318 | // inst->_num_reg_re = ; |
---|
| 1319 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1320 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1321 | // inst->_branch_condition = ; |
---|
| 1322 | // inst->_branch_stack_write = ; |
---|
| 1323 | // inst->_branch_direction = ; |
---|
| 1324 | // inst->_address_next = ; // don't change |
---|
[88] | 1325 | inst->_no_execute = 0; |
---|
[78] | 1326 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1327 | } |
---|
| 1328 | |
---|
| 1329 | void instruction_l_msync (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1330 | { |
---|
| 1331 | log_printf(TRACE,Decod,"instruction_l_msync"," * instruction : l.msync"); |
---|
| 1332 | |
---|
| 1333 | if (range<uint32_t>(inst->_instruction,22, 0) != 0) |
---|
| 1334 | { |
---|
| 1335 | instruction_illegal (inst, param); |
---|
| 1336 | } |
---|
| 1337 | else |
---|
| 1338 | { |
---|
[88] | 1339 | inst->_type = instruction_information(INSTRUCTION_L_MSYNC)._type ; //TYPE_SPECIAL; |
---|
| 1340 | inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; |
---|
[78] | 1341 | inst->_has_immediat = 0; |
---|
| 1342 | // inst->_immediat = ; |
---|
| 1343 | inst->_read_ra = 0; |
---|
| 1344 | // inst->_num_reg_ra = ; |
---|
| 1345 | inst->_read_rb = 0; |
---|
| 1346 | // inst->_num_reg_rb = ; |
---|
| 1347 | inst->_read_rc = 0; |
---|
| 1348 | // inst->_num_reg_rc = ; |
---|
| 1349 | inst->_write_rd = 0; |
---|
| 1350 | // inst->_num_reg_rd = ; |
---|
| 1351 | inst->_write_re = 0; |
---|
| 1352 | // inst->_num_reg_re = ; |
---|
| 1353 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1354 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1355 | // inst->_branch_condition = ; |
---|
| 1356 | // inst->_branch_stack_write = ; |
---|
| 1357 | // inst->_branch_direction = ; |
---|
| 1358 | // inst->_address_next = ; // don't change |
---|
[88] | 1359 | inst->_no_execute = 0; |
---|
[78] | 1360 | inst->_event_type = EVENT_TYPE_MSYNC; |
---|
| 1361 | } |
---|
| 1362 | } |
---|
| 1363 | |
---|
| 1364 | void instruction_l_mtspr (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1365 | { |
---|
| 1366 | log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr"); |
---|
| 1367 | |
---|
[88] | 1368 | inst->_type = instruction_information(INSTRUCTION_L_MTSPR)._type ; //TYPE_SPECIAL; |
---|
| 1369 | inst->_operation = instruction_information(INSTRUCTION_L_MTSPR)._operation; //OPERATION_SPECIAL_L_MTSPR; |
---|
[78] | 1370 | inst->_has_immediat = 1; |
---|
| 1371 | inst->_immediat = EXTENDZ(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1372 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1373 | inst->_read_ra = 1; |
---|
| 1374 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1375 | inst->_read_rb = 1; |
---|
| 1376 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1377 | inst->_read_rc = 0; |
---|
| 1378 | // inst->_num_reg_rc = ; |
---|
| 1379 | inst->_write_rd = 0; |
---|
| 1380 | // inst->_num_reg_rd = ; |
---|
| 1381 | inst->_write_re = 0; |
---|
| 1382 | // inst->_num_reg_re = ; |
---|
| 1383 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1384 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1385 | // inst->_branch_condition = ; |
---|
| 1386 | // inst->_branch_stack_write = ; |
---|
| 1387 | // inst->_branch_direction = ; |
---|
| 1388 | // inst->_address_next = ; // don't change |
---|
[88] | 1389 | inst->_no_execute = 0; |
---|
[78] | 1390 | inst->_event_type = EVENT_TYPE_SPR_ACCESS; |
---|
| 1391 | } |
---|
| 1392 | |
---|
| 1393 | void instruction_l_mul (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1394 | { |
---|
| 1395 | log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul"); |
---|
| 1396 | |
---|
[88] | 1397 | inst->_type = instruction_information(INSTRUCTION_L_MUL)._type ; //TYPE_MUL; |
---|
| 1398 | inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; |
---|
[78] | 1399 | inst->_has_immediat = 0; |
---|
| 1400 | // inst->_immediat = ; |
---|
| 1401 | inst->_read_ra = 1; |
---|
| 1402 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1403 | inst->_read_rb = 1; |
---|
| 1404 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1405 | inst->_read_rc = 0; |
---|
| 1406 | // inst->_num_reg_rc = ; |
---|
| 1407 | inst->_write_rd = 1; |
---|
| 1408 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1409 | inst->_write_re = 1; |
---|
| 1410 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 1411 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
[88] | 1412 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1413 | // inst->_branch_condition = ; |
---|
| 1414 | // inst->_branch_stack_write = ; |
---|
| 1415 | // inst->_branch_direction = ; |
---|
| 1416 | // inst->_address_next = ; |
---|
[88] | 1417 | inst->_no_execute = 0; |
---|
[78] | 1418 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1419 | } |
---|
| 1420 | |
---|
| 1421 | void instruction_l_muli (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1422 | { |
---|
| 1423 | log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli"); |
---|
| 1424 | |
---|
[88] | 1425 | inst->_type = instruction_information(INSTRUCTION_L_MULI)._type ; //TYPE_MUL; |
---|
| 1426 | inst->_operation = instruction_information(INSTRUCTION_L_MULI)._operation; //OPERATION_MUL_L_MUL; |
---|
[78] | 1427 | inst->_has_immediat = 1; |
---|
| 1428 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1429 | inst->_read_ra = 1; |
---|
| 1430 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1431 | inst->_read_rb = 0; |
---|
| 1432 | // inst->_num_reg_rb = ; |
---|
| 1433 | inst->_read_rc = 0; |
---|
| 1434 | // inst->_num_reg_rc = ; |
---|
| 1435 | inst->_write_rd = 1; |
---|
| 1436 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1437 | inst->_write_re = 1; |
---|
| 1438 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 1439 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
[88] | 1440 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1441 | // inst->_branch_condition = ; |
---|
| 1442 | // inst->_branch_stack_write = ; |
---|
| 1443 | // inst->_branch_direction = ; |
---|
| 1444 | // inst->_address_next = ; |
---|
[88] | 1445 | inst->_no_execute = 0; |
---|
[78] | 1446 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1447 | } |
---|
| 1448 | |
---|
| 1449 | void instruction_l_mulu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1450 | { |
---|
| 1451 | log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu"); |
---|
| 1452 | |
---|
[88] | 1453 | inst->_type = instruction_information(INSTRUCTION_L_MULU)._type ; //TYPE_MUL; |
---|
| 1454 | inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; |
---|
[78] | 1455 | inst->_has_immediat = 0; |
---|
| 1456 | // inst->_immediat = ; |
---|
| 1457 | inst->_read_ra = 1; |
---|
| 1458 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1459 | inst->_read_rb = 1; |
---|
| 1460 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1461 | inst->_read_rc = 0; |
---|
| 1462 | // inst->_num_reg_rc = ; |
---|
| 1463 | inst->_write_rd = 1; |
---|
| 1464 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1465 | inst->_write_re = 1; |
---|
| 1466 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 1467 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
[88] | 1468 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1469 | // inst->_branch_condition = ; |
---|
| 1470 | // inst->_branch_stack_write = ; |
---|
| 1471 | // inst->_branch_direction = ; |
---|
| 1472 | // inst->_address_next = ; |
---|
[88] | 1473 | inst->_no_execute = 0; |
---|
[78] | 1474 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1475 | } |
---|
| 1476 | |
---|
| 1477 | void instruction_l_nop (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1478 | { |
---|
| 1479 | log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop"); |
---|
| 1480 | |
---|
[88] | 1481 | inst->_type = instruction_information(INSTRUCTION_L_NOP)._type ; //TYPE_SPECIAL; |
---|
| 1482 | inst->_operation = instruction_information(INSTRUCTION_L_NOP)._operation; //OPERATION_SPECIAL_L_NOP; |
---|
[78] | 1483 | // inst->_has_immediat = 1; |
---|
| 1484 | // inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1485 | inst->_has_immediat = 0; |
---|
| 1486 | // inst->_immediat = ; |
---|
| 1487 | inst->_read_ra = 0; |
---|
| 1488 | // inst->_num_reg_ra = ; |
---|
| 1489 | inst->_read_rb = 0; |
---|
| 1490 | // inst->_num_reg_rb = ; |
---|
| 1491 | inst->_read_rc = 0; |
---|
| 1492 | // inst->_num_reg_rc = ; |
---|
| 1493 | inst->_write_rd = 0; |
---|
| 1494 | // inst->_num_reg_rd = ; |
---|
| 1495 | inst->_write_re = 0; |
---|
| 1496 | // inst->_num_reg_re = ; |
---|
| 1497 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1498 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1499 | // inst->_branch_condition = ; |
---|
| 1500 | // inst->_branch_stack_write = ; |
---|
| 1501 | // inst->_branch_direction = ; |
---|
| 1502 | // inst->_address_next = ; |
---|
[88] | 1503 | inst->_no_execute = 1; |
---|
[78] | 1504 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1505 | } |
---|
| 1506 | |
---|
| 1507 | void instruction_l_or (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1508 | { |
---|
| 1509 | log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or"); |
---|
| 1510 | |
---|
[88] | 1511 | inst->_type = instruction_information(INSTRUCTION_L_OR)._type ; //TYPE_ALU; |
---|
| 1512 | inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; |
---|
[78] | 1513 | inst->_has_immediat = 0; |
---|
| 1514 | // inst->_immediat = ; |
---|
| 1515 | inst->_read_ra = 1; |
---|
| 1516 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1517 | inst->_read_rb = 1; |
---|
| 1518 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1519 | inst->_read_rc = 0; |
---|
| 1520 | // inst->_num_reg_rc = ; |
---|
| 1521 | inst->_write_rd = 1; |
---|
| 1522 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1523 | inst->_write_re = 0; |
---|
| 1524 | // inst->_num_reg_re = ; |
---|
| 1525 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1526 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1527 | // inst->_branch_condition = ; |
---|
| 1528 | // inst->_branch_stack_write = ; |
---|
| 1529 | // inst->_branch_direction = ; |
---|
| 1530 | // inst->_address_next = ; |
---|
[88] | 1531 | inst->_no_execute = 0; |
---|
[78] | 1532 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1533 | } |
---|
| 1534 | |
---|
| 1535 | void instruction_l_ori (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1536 | { |
---|
| 1537 | log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori"); |
---|
| 1538 | |
---|
[88] | 1539 | inst->_type = instruction_information(INSTRUCTION_L_ORI)._type ; //TYPE_ALU; |
---|
| 1540 | inst->_operation = instruction_information(INSTRUCTION_L_ORI)._operation; //OPERATION_ALU_L_OR; |
---|
[78] | 1541 | inst->_has_immediat = 1; |
---|
| 1542 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 1543 | inst->_read_ra = 1; |
---|
| 1544 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1545 | inst->_read_rb = 0; |
---|
| 1546 | // inst->_num_reg_rb = ; |
---|
| 1547 | inst->_read_rc = 0; |
---|
| 1548 | // inst->_num_reg_rc = ; |
---|
| 1549 | inst->_write_rd = 1; |
---|
| 1550 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1551 | inst->_write_re = 0; |
---|
| 1552 | // inst->_num_reg_re = ; |
---|
| 1553 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1554 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1555 | // inst->_branch_condition = ; |
---|
| 1556 | // inst->_branch_stack_write = ; |
---|
| 1557 | // inst->_branch_direction = ; |
---|
| 1558 | // inst->_address_next = ; |
---|
[88] | 1559 | inst->_no_execute = 0; |
---|
[78] | 1560 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1561 | } |
---|
| 1562 | |
---|
| 1563 | void instruction_l_psync (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1564 | { |
---|
| 1565 | log_printf(TRACE,Decod,"instruction_l_psync"," * instruction : l.psync"); |
---|
| 1566 | |
---|
| 1567 | if (range<uint32_t>(inst->_instruction,22, 0) != 0) |
---|
| 1568 | { |
---|
| 1569 | instruction_illegal (inst, param); |
---|
| 1570 | } |
---|
| 1571 | else |
---|
| 1572 | { |
---|
[88] | 1573 | inst->_type = instruction_information(INSTRUCTION_L_PSYNC)._type ; //TYPE_SPECIAL; |
---|
| 1574 | inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; |
---|
[78] | 1575 | inst->_has_immediat = 0; |
---|
| 1576 | // inst->_immediat = ; |
---|
| 1577 | inst->_read_ra = 0; |
---|
| 1578 | // inst->_num_reg_ra = ; |
---|
| 1579 | inst->_read_rb = 0; |
---|
| 1580 | // inst->_num_reg_rb = ; |
---|
| 1581 | inst->_read_rc = 0; |
---|
| 1582 | // inst->_num_reg_rc = ; |
---|
| 1583 | inst->_write_rd = 0; |
---|
| 1584 | // inst->_num_reg_rd = ; |
---|
| 1585 | inst->_write_re = 0; |
---|
| 1586 | // inst->_num_reg_re = ; |
---|
| 1587 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1588 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1589 | // inst->_branch_condition = ; |
---|
| 1590 | // inst->_branch_stack_write = ; |
---|
| 1591 | // inst->_branch_direction = ; |
---|
| 1592 | // inst->_address_next = ; // don't change |
---|
[88] | 1593 | inst->_no_execute = 0; |
---|
[78] | 1594 | inst->_event_type = EVENT_TYPE_PSYNC; |
---|
| 1595 | } |
---|
| 1596 | } |
---|
| 1597 | |
---|
| 1598 | void instruction_l_rfe (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1599 | { |
---|
| 1600 | log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe"); |
---|
| 1601 | |
---|
[88] | 1602 | inst->_type = instruction_information(INSTRUCTION_L_RFE)._type ; //TYPE_SPECIAL; |
---|
| 1603 | inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; |
---|
[78] | 1604 | inst->_has_immediat = 0; |
---|
| 1605 | // inst->_immediat = ; |
---|
| 1606 | inst->_read_ra = 0; |
---|
| 1607 | // inst->_num_reg_ra = ; |
---|
| 1608 | inst->_read_rb = 0; |
---|
| 1609 | // inst->_num_reg_rb = ; |
---|
| 1610 | inst->_read_rc = 0; |
---|
| 1611 | // inst->_num_reg_rc = ; |
---|
| 1612 | inst->_write_rd = 0; |
---|
| 1613 | // inst->_num_reg_rd = ; |
---|
| 1614 | inst->_write_re = 0; |
---|
| 1615 | // inst->_num_reg_re = ; |
---|
| 1616 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1617 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1618 | // inst->_branch_condition = ; |
---|
| 1619 | // inst->_branch_stack_write = ; |
---|
| 1620 | // inst->_branch_direction = ; |
---|
| 1621 | // inst->_address_next = ; // don't change |
---|
[88] | 1622 | inst->_no_execute = 1; |
---|
[78] | 1623 | inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage |
---|
| 1624 | } |
---|
| 1625 | |
---|
| 1626 | void instruction_l_ror (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1627 | { |
---|
| 1628 | log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror"); |
---|
| 1629 | |
---|
[88] | 1630 | inst->_type = instruction_information(INSTRUCTION_L_ROR)._type ; //TYPE_SHIFT; |
---|
| 1631 | inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; |
---|
[78] | 1632 | inst->_has_immediat = 0; |
---|
| 1633 | // inst->_immediat = ; |
---|
| 1634 | inst->_read_ra = 1; |
---|
| 1635 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1636 | inst->_read_rb = 1; |
---|
| 1637 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1638 | inst->_read_rc = 0; |
---|
| 1639 | // inst->_num_reg_rc = ; |
---|
| 1640 | inst->_write_rd = 1; |
---|
| 1641 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1642 | inst->_write_re = 0; |
---|
| 1643 | // inst->_num_reg_re = ; |
---|
| 1644 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1645 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1646 | // inst->_branch_condition = ; |
---|
| 1647 | // inst->_branch_stack_write = ; |
---|
| 1648 | // inst->_branch_direction = ; |
---|
| 1649 | // inst->_address_next = ; |
---|
[88] | 1650 | inst->_no_execute = 0; |
---|
[78] | 1651 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1652 | } |
---|
| 1653 | |
---|
| 1654 | void instruction_l_rori (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1655 | { |
---|
| 1656 | log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori"); |
---|
| 1657 | |
---|
[88] | 1658 | inst->_type = instruction_information(INSTRUCTION_L_RORI)._type ; //TYPE_SHIFT; |
---|
| 1659 | inst->_operation = instruction_information(INSTRUCTION_L_RORI)._operation; //OPERATION_SHIFT_L_ROR; |
---|
[78] | 1660 | inst->_has_immediat = 1; |
---|
| 1661 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 1662 | inst->_read_ra = 1; |
---|
| 1663 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1664 | inst->_read_rb = 0; |
---|
| 1665 | // inst->_num_reg_rb = ; |
---|
| 1666 | inst->_read_rc = 0; |
---|
| 1667 | // inst->_num_reg_rc = ; |
---|
| 1668 | inst->_write_rd = 1; |
---|
| 1669 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 1670 | inst->_write_re = 0; |
---|
| 1671 | // inst->_num_reg_re = ; |
---|
| 1672 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1673 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1674 | // inst->_branch_condition = ; |
---|
| 1675 | // inst->_branch_stack_write = ; |
---|
| 1676 | // inst->_branch_direction = ; |
---|
| 1677 | // inst->_address_next = ; |
---|
[88] | 1678 | inst->_no_execute = 0; |
---|
[78] | 1679 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1680 | } |
---|
| 1681 | |
---|
| 1682 | void instruction_l_sb (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1683 | { |
---|
| 1684 | log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); |
---|
| 1685 | |
---|
[88] | 1686 | inst->_type = instruction_information(INSTRUCTION_L_SB)._type ; //TYPE_MEMORY; |
---|
| 1687 | inst->_operation = instruction_information(INSTRUCTION_L_SB)._operation; //OPERATION_MEMORY_STORE_8; |
---|
[78] | 1688 | inst->_has_immediat = 1; |
---|
| 1689 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1690 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1691 | inst->_read_ra = 1; |
---|
| 1692 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1693 | inst->_read_rb = 1; |
---|
| 1694 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1695 | inst->_read_rc = 0; |
---|
| 1696 | // inst->_num_reg_rc = ; |
---|
| 1697 | inst->_write_rd = 0; |
---|
| 1698 | // inst->_num_reg_rd = ; |
---|
| 1699 | inst->_write_re = 0; |
---|
| 1700 | // inst->_num_reg_re = ; |
---|
| 1701 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; |
---|
[88] | 1702 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1703 | // inst->_branch_condition = ; |
---|
| 1704 | // inst->_branch_stack_write = ; |
---|
| 1705 | // inst->_branch_direction = ; |
---|
| 1706 | // inst->_address_next = ; |
---|
[88] | 1707 | inst->_no_execute = 0; |
---|
[78] | 1708 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1709 | } |
---|
| 1710 | |
---|
| 1711 | void instruction_l_sd (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1712 | { |
---|
| 1713 | log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); |
---|
| 1714 | |
---|
[88] | 1715 | inst->_type = instruction_information(INSTRUCTION_L_SD)._type ; //TYPE_MEMORY; |
---|
| 1716 | inst->_operation = instruction_information(INSTRUCTION_L_SD)._operation; //OPERATION_MEMORY_STORE_64; |
---|
[78] | 1717 | inst->_has_immediat = 1; |
---|
| 1718 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 1719 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 1720 | inst->_read_ra = 1; |
---|
| 1721 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1722 | inst->_read_rb = 1; |
---|
| 1723 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1724 | inst->_read_rc = 0; |
---|
| 1725 | // inst->_num_reg_rc = ; |
---|
| 1726 | inst->_write_rd = 0; |
---|
| 1727 | // inst->_num_reg_rd = ; |
---|
| 1728 | inst->_write_re = 0; |
---|
| 1729 | // inst->_num_reg_re = ; |
---|
| 1730 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 1731 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1732 | // inst->_branch_condition = ; |
---|
| 1733 | // inst->_branch_stack_write = ; |
---|
| 1734 | // inst->_branch_direction = ; |
---|
| 1735 | // inst->_address_next = ; |
---|
[88] | 1736 | inst->_no_execute = 0; |
---|
[78] | 1737 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1738 | } |
---|
| 1739 | |
---|
| 1740 | void instruction_l_sfeq (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1741 | { |
---|
| 1742 | log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq"); |
---|
| 1743 | |
---|
[88] | 1744 | inst->_type = instruction_information(INSTRUCTION_L_SFEQ)._type ; //TYPE_TEST; |
---|
| 1745 | inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; |
---|
[78] | 1746 | inst->_has_immediat = 0; |
---|
| 1747 | // inst->_immediat = ; |
---|
| 1748 | inst->_read_ra = 1; |
---|
| 1749 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1750 | inst->_read_rb = 1; |
---|
| 1751 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1752 | inst->_read_rc = 0; |
---|
| 1753 | // inst->_num_reg_rc = ; |
---|
| 1754 | inst->_write_rd = 0; |
---|
| 1755 | // inst->_num_reg_rd = ; |
---|
| 1756 | inst->_write_re = 1; |
---|
| 1757 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1758 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1759 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1760 | // inst->_branch_condition = ; |
---|
| 1761 | // inst->_branch_stack_write = ; |
---|
| 1762 | // inst->_branch_direction = ; |
---|
| 1763 | // inst->_address_next = ; |
---|
[88] | 1764 | inst->_no_execute = 0; |
---|
[78] | 1765 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1766 | } |
---|
| 1767 | |
---|
| 1768 | void instruction_l_sfeqi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1769 | { |
---|
| 1770 | log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi"); |
---|
| 1771 | |
---|
[88] | 1772 | inst->_type = instruction_information(INSTRUCTION_L_SFEQI)._type ; //TYPE_TEST; |
---|
| 1773 | inst->_operation = instruction_information(INSTRUCTION_L_SFEQI)._operation; //OPERATION_TEST_L_SFEQ; |
---|
[78] | 1774 | inst->_has_immediat = 1; |
---|
| 1775 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1776 | inst->_read_ra = 1; |
---|
| 1777 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1778 | inst->_read_rb = 0; |
---|
| 1779 | // inst->_num_reg_rb = ; |
---|
| 1780 | inst->_read_rc = 0; |
---|
| 1781 | // inst->_num_reg_rc = ; |
---|
| 1782 | inst->_write_rd = 0; |
---|
| 1783 | // inst->_num_reg_rd = ; |
---|
| 1784 | inst->_write_re = 1; |
---|
| 1785 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1786 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1787 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1788 | // inst->_branch_condition = ; |
---|
| 1789 | // inst->_branch_stack_write = ; |
---|
| 1790 | // inst->_branch_direction = ; |
---|
| 1791 | // inst->_address_next = ; |
---|
[88] | 1792 | inst->_no_execute = 0; |
---|
[78] | 1793 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1794 | } |
---|
| 1795 | |
---|
| 1796 | void instruction_l_sfges (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1797 | { |
---|
| 1798 | log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges"); |
---|
| 1799 | |
---|
[88] | 1800 | inst->_type = instruction_information(INSTRUCTION_L_SFGES)._type ; //TYPE_TEST; |
---|
| 1801 | inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; |
---|
[78] | 1802 | inst->_has_immediat = 0; |
---|
| 1803 | // inst->_immediat = ; |
---|
| 1804 | inst->_read_ra = 1; |
---|
| 1805 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1806 | inst->_read_rb = 1; |
---|
| 1807 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1808 | inst->_read_rc = 0; |
---|
| 1809 | // inst->_num_reg_rc = ; |
---|
| 1810 | inst->_write_rd = 0; |
---|
| 1811 | // inst->_num_reg_rd = ; |
---|
| 1812 | inst->_write_re = 1; |
---|
| 1813 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1814 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1815 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1816 | // inst->_branch_condition = ; |
---|
| 1817 | // inst->_branch_stack_write = ; |
---|
| 1818 | // inst->_branch_direction = ; |
---|
| 1819 | // inst->_address_next = ; |
---|
[88] | 1820 | inst->_no_execute = 0; |
---|
[78] | 1821 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1822 | } |
---|
| 1823 | |
---|
| 1824 | void instruction_l_sfgesi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1825 | { |
---|
| 1826 | log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi"); |
---|
| 1827 | |
---|
[88] | 1828 | inst->_type = instruction_information(INSTRUCTION_L_SFGESI)._type ; //TYPE_TEST; |
---|
| 1829 | inst->_operation = instruction_information(INSTRUCTION_L_SFGESI)._operation; //OPERATION_TEST_L_SFGES; |
---|
[78] | 1830 | inst->_has_immediat = 1; |
---|
| 1831 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1832 | inst->_read_ra = 1; |
---|
| 1833 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1834 | inst->_read_rb = 0; |
---|
| 1835 | // inst->_num_reg_rb = ; |
---|
| 1836 | inst->_read_rc = 0; |
---|
| 1837 | // inst->_num_reg_rc = ; |
---|
| 1838 | inst->_write_rd = 0; |
---|
| 1839 | // inst->_num_reg_rd = ; |
---|
| 1840 | inst->_write_re = 1; |
---|
| 1841 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1842 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1843 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1844 | // inst->_branch_condition = ; |
---|
| 1845 | // inst->_branch_stack_write = ; |
---|
| 1846 | // inst->_branch_direction = ; |
---|
| 1847 | // inst->_address_next = ; |
---|
[88] | 1848 | inst->_no_execute = 0; |
---|
[78] | 1849 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1850 | } |
---|
| 1851 | |
---|
| 1852 | void instruction_l_sfgeu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1853 | { |
---|
| 1854 | log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu"); |
---|
| 1855 | |
---|
[88] | 1856 | inst->_type = instruction_information(INSTRUCTION_L_SFGEU)._type ; //TYPE_TEST; |
---|
| 1857 | inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; |
---|
[78] | 1858 | inst->_has_immediat = 0; |
---|
| 1859 | // inst->_immediat = ; |
---|
| 1860 | inst->_read_ra = 1; |
---|
| 1861 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1862 | inst->_read_rb = 1; |
---|
| 1863 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1864 | inst->_read_rc = 0; |
---|
| 1865 | // inst->_num_reg_rc = ; |
---|
| 1866 | inst->_write_rd = 0; |
---|
| 1867 | // inst->_num_reg_rd = ; |
---|
| 1868 | inst->_write_re = 1; |
---|
| 1869 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1870 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1871 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1872 | // inst->_branch_condition = ; |
---|
| 1873 | // inst->_branch_stack_write = ; |
---|
| 1874 | // inst->_branch_direction = ; |
---|
| 1875 | // inst->_address_next = ; |
---|
[88] | 1876 | inst->_no_execute = 0; |
---|
[78] | 1877 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1878 | } |
---|
| 1879 | |
---|
| 1880 | void instruction_l_sfgeui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1881 | { |
---|
| 1882 | log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui"); |
---|
| 1883 | |
---|
[88] | 1884 | inst->_type = instruction_information(INSTRUCTION_L_SFGEUI)._type ; //TYPE_TEST; |
---|
| 1885 | inst->_operation = instruction_information(INSTRUCTION_L_SFGEUI)._operation; //OPERATION_TEST_L_SFGEU; |
---|
[78] | 1886 | inst->_has_immediat = 1; |
---|
| 1887 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1888 | inst->_read_ra = 1; |
---|
| 1889 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1890 | inst->_read_rb = 0; |
---|
| 1891 | // inst->_num_reg_rb = ; |
---|
| 1892 | inst->_read_rc = 0; |
---|
| 1893 | // inst->_num_reg_rc = ; |
---|
| 1894 | inst->_write_rd = 0; |
---|
| 1895 | // inst->_num_reg_rd = ; |
---|
| 1896 | inst->_write_re = 1; |
---|
| 1897 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1898 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1899 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1900 | // inst->_branch_condition = ; |
---|
| 1901 | // inst->_branch_stack_write = ; |
---|
| 1902 | // inst->_branch_direction = ; |
---|
| 1903 | // inst->_address_next = ; |
---|
[88] | 1904 | inst->_no_execute = 0; |
---|
[78] | 1905 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1906 | } |
---|
| 1907 | |
---|
| 1908 | void instruction_l_sfgts (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1909 | { |
---|
| 1910 | log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts"); |
---|
| 1911 | |
---|
[88] | 1912 | inst->_type = instruction_information(INSTRUCTION_L_SFGTS)._type ; //TYPE_TEST; |
---|
| 1913 | inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; |
---|
[78] | 1914 | inst->_has_immediat = 0; |
---|
| 1915 | // inst->_immediat = ; |
---|
| 1916 | inst->_read_ra = 1; |
---|
| 1917 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1918 | inst->_read_rb = 1; |
---|
| 1919 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1920 | inst->_read_rc = 0; |
---|
| 1921 | // inst->_num_reg_rc = ; |
---|
| 1922 | inst->_write_rd = 0; |
---|
| 1923 | // inst->_num_reg_rd = ; |
---|
| 1924 | inst->_write_re = 1; |
---|
| 1925 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1926 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1927 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1928 | // inst->_branch_condition = ; |
---|
| 1929 | // inst->_branch_stack_write = ; |
---|
| 1930 | // inst->_branch_direction = ; |
---|
| 1931 | // inst->_address_next = ; |
---|
[88] | 1932 | inst->_no_execute = 0; |
---|
[78] | 1933 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1934 | } |
---|
| 1935 | |
---|
| 1936 | void instruction_l_sfgtsi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1937 | { |
---|
| 1938 | log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi"); |
---|
| 1939 | |
---|
[88] | 1940 | inst->_type = instruction_information(INSTRUCTION_L_SFGTSI)._type ; //TYPE_TEST; |
---|
| 1941 | inst->_operation = instruction_information(INSTRUCTION_L_SFGTSI)._operation; //OPERATION_TEST_L_SFGTS; |
---|
[78] | 1942 | inst->_has_immediat = 1; |
---|
| 1943 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 1944 | inst->_read_ra = 1; |
---|
| 1945 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1946 | inst->_read_rb = 0; |
---|
| 1947 | // inst->_num_reg_rb = ; |
---|
| 1948 | inst->_read_rc = 0; |
---|
| 1949 | // inst->_num_reg_rc = ; |
---|
| 1950 | inst->_write_rd = 0; |
---|
| 1951 | // inst->_num_reg_rd = ; |
---|
| 1952 | inst->_write_re = 1; |
---|
| 1953 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1954 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1955 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1956 | // inst->_branch_condition = ; |
---|
| 1957 | // inst->_branch_stack_write = ; |
---|
| 1958 | // inst->_branch_direction = ; |
---|
| 1959 | // inst->_address_next = ; |
---|
[88] | 1960 | inst->_no_execute = 0; |
---|
[78] | 1961 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1962 | } |
---|
| 1963 | |
---|
| 1964 | void instruction_l_sfgtu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1965 | { |
---|
| 1966 | log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu"); |
---|
| 1967 | |
---|
[88] | 1968 | inst->_type = instruction_information(INSTRUCTION_L_SFGTU)._type ; //TYPE_TEST; |
---|
| 1969 | inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; |
---|
[78] | 1970 | inst->_has_immediat = 0; |
---|
| 1971 | // inst->_immediat = ; |
---|
| 1972 | inst->_read_ra = 1; |
---|
| 1973 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 1974 | inst->_read_rb = 1; |
---|
| 1975 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 1976 | inst->_read_rc = 0; |
---|
| 1977 | // inst->_num_reg_rc = ; |
---|
| 1978 | inst->_write_rd = 0; |
---|
| 1979 | // inst->_num_reg_rd = ; |
---|
| 1980 | inst->_write_re = 1; |
---|
| 1981 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 1982 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 1983 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 1984 | // inst->_branch_condition = ; |
---|
| 1985 | // inst->_branch_stack_write = ; |
---|
| 1986 | // inst->_branch_direction = ; |
---|
| 1987 | // inst->_address_next = ; |
---|
[88] | 1988 | inst->_no_execute = 0; |
---|
[78] | 1989 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 1990 | } |
---|
| 1991 | |
---|
| 1992 | void instruction_l_sfgtui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 1993 | { |
---|
| 1994 | log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui"); |
---|
| 1995 | |
---|
[88] | 1996 | inst->_type = instruction_information(INSTRUCTION_L_SFGTUI)._type ; //TYPE_TEST; |
---|
| 1997 | inst->_operation = instruction_information(INSTRUCTION_L_SFGTUI)._operation; //OPERATION_TEST_L_SFGTU; |
---|
[78] | 1998 | inst->_has_immediat = 1; |
---|
| 1999 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2000 | inst->_read_ra = 1; |
---|
| 2001 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2002 | inst->_read_rb = 0; |
---|
| 2003 | // inst->_num_reg_rb = ; |
---|
| 2004 | inst->_read_rc = 0; |
---|
| 2005 | // inst->_num_reg_rc = ; |
---|
| 2006 | inst->_write_rd = 0; |
---|
| 2007 | // inst->_num_reg_rd = ; |
---|
| 2008 | inst->_write_re = 1; |
---|
| 2009 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2010 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2011 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2012 | // inst->_branch_condition = ; |
---|
| 2013 | // inst->_branch_stack_write = ; |
---|
| 2014 | // inst->_branch_direction = ; |
---|
| 2015 | // inst->_address_next = ; |
---|
[88] | 2016 | inst->_no_execute = 0; |
---|
[78] | 2017 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2018 | } |
---|
| 2019 | |
---|
| 2020 | void instruction_l_sfles (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2021 | { |
---|
| 2022 | log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles"); |
---|
| 2023 | |
---|
[88] | 2024 | inst->_type = instruction_information(INSTRUCTION_L_SFLES)._type ; //TYPE_TEST; |
---|
| 2025 | inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; |
---|
[78] | 2026 | inst->_has_immediat = 0; |
---|
| 2027 | // inst->_immediat = ; |
---|
| 2028 | inst->_read_ra = 1; |
---|
| 2029 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2030 | inst->_read_rb = 1; |
---|
| 2031 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2032 | inst->_read_rc = 0; |
---|
| 2033 | // inst->_num_reg_rc = ; |
---|
| 2034 | inst->_write_rd = 0; |
---|
| 2035 | // inst->_num_reg_rd = ; |
---|
| 2036 | inst->_write_re = 1; |
---|
| 2037 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2038 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2039 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2040 | // inst->_branch_condition = ; |
---|
| 2041 | // inst->_branch_stack_write = ; |
---|
| 2042 | // inst->_branch_direction = ; |
---|
| 2043 | // inst->_address_next = ; |
---|
[88] | 2044 | inst->_no_execute = 0; |
---|
[78] | 2045 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2046 | } |
---|
| 2047 | |
---|
| 2048 | void instruction_l_sflesi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2049 | { |
---|
| 2050 | log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi"); |
---|
| 2051 | |
---|
[88] | 2052 | inst->_type = instruction_information(INSTRUCTION_L_SFLESI)._type ; //TYPE_TEST; |
---|
| 2053 | inst->_operation = instruction_information(INSTRUCTION_L_SFLESI)._operation; //OPERATION_TEST_L_SFLES; |
---|
[78] | 2054 | inst->_has_immediat = 1; |
---|
| 2055 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2056 | inst->_read_ra = 1; |
---|
| 2057 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2058 | inst->_read_rb = 0; |
---|
| 2059 | // inst->_num_reg_rb = ; |
---|
| 2060 | inst->_read_rc = 0; |
---|
| 2061 | // inst->_num_reg_rc = ; |
---|
| 2062 | inst->_write_rd = 0; |
---|
| 2063 | // inst->_num_reg_rd = ; |
---|
| 2064 | inst->_write_re = 1; |
---|
| 2065 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2066 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2067 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2068 | // inst->_branch_condition = ; |
---|
| 2069 | // inst->_branch_stack_write = ; |
---|
| 2070 | // inst->_branch_direction = ; |
---|
| 2071 | // inst->_address_next = ; |
---|
[88] | 2072 | inst->_no_execute = 0; |
---|
[78] | 2073 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2074 | } |
---|
| 2075 | |
---|
| 2076 | void instruction_l_sfleu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2077 | { |
---|
| 2078 | log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu"); |
---|
| 2079 | |
---|
[88] | 2080 | inst->_type = instruction_information(INSTRUCTION_L_SFLEU)._type ; //TYPE_TEST; |
---|
| 2081 | inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; |
---|
[78] | 2082 | inst->_has_immediat = 0; |
---|
| 2083 | // inst->_immediat = ; |
---|
| 2084 | inst->_read_ra = 1; |
---|
| 2085 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2086 | inst->_read_rb = 1; |
---|
| 2087 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2088 | inst->_read_rc = 0; |
---|
| 2089 | // inst->_num_reg_rc = ; |
---|
| 2090 | inst->_write_rd = 0; |
---|
| 2091 | // inst->_num_reg_rd = ; |
---|
| 2092 | inst->_write_re = 1; |
---|
| 2093 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2094 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2095 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2096 | // inst->_branch_condition = ; |
---|
| 2097 | // inst->_branch_stack_write = ; |
---|
| 2098 | // inst->_branch_direction = ; |
---|
| 2099 | // inst->_address_next = ; |
---|
[88] | 2100 | inst->_no_execute = 0; |
---|
[78] | 2101 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2102 | } |
---|
| 2103 | |
---|
| 2104 | void instruction_l_sfleui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2105 | { |
---|
| 2106 | log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui"); |
---|
| 2107 | |
---|
[88] | 2108 | inst->_type = instruction_information(INSTRUCTION_L_SFLEUI)._type ; //TYPE_TEST; |
---|
| 2109 | inst->_operation = instruction_information(INSTRUCTION_L_SFLEUI)._operation; //OPERATION_TEST_L_SFLEU; |
---|
[78] | 2110 | inst->_has_immediat = 1; |
---|
| 2111 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2112 | inst->_read_ra = 1; |
---|
| 2113 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2114 | inst->_read_rb = 0; |
---|
| 2115 | // inst->_num_reg_rb = ; |
---|
| 2116 | inst->_read_rc = 0; |
---|
| 2117 | // inst->_num_reg_rc = ; |
---|
| 2118 | inst->_write_rd = 0; |
---|
| 2119 | // inst->_num_reg_rd = ; |
---|
| 2120 | inst->_write_re = 1; |
---|
| 2121 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2122 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2123 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2124 | // inst->_branch_condition = ; |
---|
| 2125 | // inst->_branch_stack_write = ; |
---|
| 2126 | // inst->_branch_direction = ; |
---|
| 2127 | // inst->_address_next = ; |
---|
[88] | 2128 | inst->_no_execute = 0; |
---|
[78] | 2129 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2130 | } |
---|
| 2131 | |
---|
| 2132 | void instruction_l_sflts (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2133 | { |
---|
| 2134 | log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts"); |
---|
| 2135 | |
---|
[88] | 2136 | inst->_type = instruction_information(INSTRUCTION_L_SFLTS)._type ; //TYPE_TEST; |
---|
| 2137 | inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; |
---|
[78] | 2138 | inst->_has_immediat = 0; |
---|
| 2139 | // inst->_immediat = ; |
---|
| 2140 | inst->_read_ra = 1; |
---|
| 2141 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2142 | inst->_read_rb = 1; |
---|
| 2143 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2144 | inst->_read_rc = 0; |
---|
| 2145 | // inst->_num_reg_rc = ; |
---|
| 2146 | inst->_write_rd = 0; |
---|
| 2147 | // inst->_num_reg_rd = ; |
---|
| 2148 | inst->_write_re = 1; |
---|
| 2149 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2150 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2151 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2152 | // inst->_branch_condition = ; |
---|
| 2153 | // inst->_branch_stack_write = ; |
---|
| 2154 | // inst->_branch_direction = ; |
---|
| 2155 | // inst->_address_next = ; |
---|
[88] | 2156 | inst->_no_execute = 0; |
---|
[78] | 2157 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2158 | } |
---|
| 2159 | |
---|
| 2160 | void instruction_l_sfltsi (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2161 | { |
---|
| 2162 | log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi"); |
---|
| 2163 | |
---|
[88] | 2164 | inst->_type = instruction_information(INSTRUCTION_L_SFLTSI)._type ; //TYPE_TEST; |
---|
| 2165 | inst->_operation = instruction_information(INSTRUCTION_L_SFLTSI)._operation; //OPERATION_TEST_L_SFLTS; |
---|
[78] | 2166 | inst->_has_immediat = 1; |
---|
| 2167 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2168 | inst->_read_ra = 1; |
---|
| 2169 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2170 | inst->_read_rb = 0; |
---|
| 2171 | // inst->_num_reg_rb = ; |
---|
| 2172 | inst->_read_rc = 0; |
---|
| 2173 | // inst->_num_reg_rc = ; |
---|
| 2174 | inst->_write_rd = 0; |
---|
| 2175 | // inst->_num_reg_rd = ; |
---|
| 2176 | inst->_write_re = 1; |
---|
| 2177 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2178 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2179 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2180 | // inst->_branch_condition = ; |
---|
| 2181 | // inst->_branch_stack_write = ; |
---|
| 2182 | // inst->_branch_direction = ; |
---|
| 2183 | // inst->_address_next = ; |
---|
[88] | 2184 | inst->_no_execute = 0; |
---|
[78] | 2185 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2186 | } |
---|
| 2187 | |
---|
| 2188 | void instruction_l_sfltu (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2189 | { |
---|
| 2190 | log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu"); |
---|
| 2191 | |
---|
[88] | 2192 | inst->_type = instruction_information(INSTRUCTION_L_SFLTU)._type ; //TYPE_TEST; |
---|
| 2193 | inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; |
---|
[78] | 2194 | inst->_has_immediat = 0; |
---|
| 2195 | // inst->_immediat = ; |
---|
| 2196 | inst->_read_ra = 1; |
---|
| 2197 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2198 | inst->_read_rb = 1; |
---|
| 2199 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2200 | inst->_read_rc = 0; |
---|
| 2201 | // inst->_num_reg_rc = ; |
---|
| 2202 | inst->_write_rd = 0; |
---|
| 2203 | // inst->_num_reg_rd = ; |
---|
| 2204 | inst->_write_re = 1; |
---|
| 2205 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2206 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2207 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2208 | // inst->_branch_condition = ; |
---|
| 2209 | // inst->_branch_stack_write = ; |
---|
| 2210 | // inst->_branch_direction = ; |
---|
| 2211 | // inst->_address_next = ; |
---|
[88] | 2212 | inst->_no_execute = 0; |
---|
[78] | 2213 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2214 | } |
---|
| 2215 | |
---|
| 2216 | void instruction_l_sfltui (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2217 | { |
---|
| 2218 | log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui"); |
---|
| 2219 | |
---|
[88] | 2220 | inst->_type = instruction_information(INSTRUCTION_L_SFLTUI)._type ; //TYPE_TEST; |
---|
| 2221 | inst->_operation = instruction_information(INSTRUCTION_L_SFLTUI)._operation; //OPERATION_TEST_L_SFLTU; |
---|
[78] | 2222 | inst->_has_immediat = 1; |
---|
| 2223 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2224 | inst->_read_ra = 1; |
---|
| 2225 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2226 | inst->_read_rb = 0; |
---|
| 2227 | // inst->_num_reg_rb = ; |
---|
| 2228 | inst->_read_rc = 0; |
---|
| 2229 | // inst->_num_reg_rc = ; |
---|
| 2230 | inst->_write_rd = 0; |
---|
| 2231 | // inst->_num_reg_rd = ; |
---|
| 2232 | inst->_write_re = 1; |
---|
| 2233 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2234 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2235 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2236 | // inst->_branch_condition = ; |
---|
| 2237 | // inst->_branch_stack_write = ; |
---|
| 2238 | // inst->_branch_direction = ; |
---|
| 2239 | // inst->_address_next = ; |
---|
[88] | 2240 | inst->_no_execute = 0; |
---|
[78] | 2241 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2242 | } |
---|
| 2243 | |
---|
| 2244 | void instruction_l_sfne (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2245 | { |
---|
| 2246 | log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne"); |
---|
| 2247 | |
---|
[88] | 2248 | inst->_type = instruction_information(INSTRUCTION_L_SFNE)._type ; //TYPE_TEST; |
---|
| 2249 | inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; |
---|
[78] | 2250 | inst->_has_immediat = 0; |
---|
| 2251 | // inst->_immediat = ; |
---|
| 2252 | inst->_read_ra = 1; |
---|
| 2253 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2254 | inst->_read_rb = 1; |
---|
| 2255 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2256 | inst->_read_rc = 0; |
---|
| 2257 | // inst->_num_reg_rc = ; |
---|
| 2258 | inst->_write_rd = 0; |
---|
| 2259 | // inst->_num_reg_rd = ; |
---|
| 2260 | inst->_write_re = 1; |
---|
| 2261 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2262 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2263 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2264 | // inst->_branch_condition = ; |
---|
| 2265 | // inst->_branch_stack_write = ; |
---|
| 2266 | // inst->_branch_direction = ; |
---|
| 2267 | // inst->_address_next = ; |
---|
[88] | 2268 | inst->_no_execute = 0; |
---|
[78] | 2269 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2270 | } |
---|
| 2271 | |
---|
| 2272 | void instruction_l_sfnei (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2273 | { |
---|
| 2274 | log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei"); |
---|
| 2275 | |
---|
[88] | 2276 | inst->_type = instruction_information(INSTRUCTION_L_SFNEI)._type ; //TYPE_TEST; |
---|
| 2277 | inst->_operation = instruction_information(INSTRUCTION_L_SFNEI)._operation; //OPERATION_TEST_L_SFNE; |
---|
[78] | 2278 | inst->_has_immediat = 1; |
---|
| 2279 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2280 | inst->_read_ra = 1; |
---|
| 2281 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2282 | inst->_read_rb = 0; |
---|
| 2283 | // inst->_num_reg_rb = ; |
---|
| 2284 | inst->_read_rc = 0; |
---|
| 2285 | // inst->_num_reg_rc = ; |
---|
| 2286 | inst->_write_rd = 0; |
---|
| 2287 | // inst->_num_reg_rd = ; |
---|
| 2288 | inst->_write_re = 1; |
---|
| 2289 | inst->_num_reg_re = SPR_LOGIC_SR_F; |
---|
| 2290 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2291 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2292 | // inst->_branch_condition = ; |
---|
| 2293 | // inst->_branch_stack_write = ; |
---|
| 2294 | // inst->_branch_direction = ; |
---|
| 2295 | // inst->_address_next = ; |
---|
[88] | 2296 | inst->_no_execute = 0; |
---|
[78] | 2297 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2298 | } |
---|
| 2299 | |
---|
| 2300 | void instruction_l_sh (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2301 | { |
---|
| 2302 | log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh"); |
---|
| 2303 | |
---|
[88] | 2304 | inst->_type = instruction_information(INSTRUCTION_L_SH)._type ; //TYPE_MEMORY; |
---|
| 2305 | inst->_operation = instruction_information(INSTRUCTION_L_SH)._operation; //OPERATION_MEMORY_STORE_16; |
---|
[78] | 2306 | inst->_has_immediat = 1; |
---|
| 2307 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 2308 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 2309 | inst->_read_ra = 1; |
---|
| 2310 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2311 | inst->_read_rb = 1; |
---|
| 2312 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2313 | inst->_read_rc = 0; |
---|
| 2314 | // inst->_num_reg_rc = ; |
---|
| 2315 | inst->_write_rd = 0; |
---|
| 2316 | // inst->_num_reg_rd = ; |
---|
| 2317 | inst->_write_re = 0; |
---|
| 2318 | // inst->_num_reg_re = ; |
---|
| 2319 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 2320 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2321 | // inst->_branch_condition = ; |
---|
| 2322 | // inst->_branch_stack_write = ; |
---|
| 2323 | // inst->_branch_direction = ; |
---|
| 2324 | // inst->_address_next = ; |
---|
[88] | 2325 | inst->_no_execute = 0; |
---|
[78] | 2326 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2327 | } |
---|
| 2328 | |
---|
| 2329 | void instruction_l_sll (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2330 | { |
---|
| 2331 | log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll"); |
---|
| 2332 | |
---|
[88] | 2333 | inst->_type = instruction_information(INSTRUCTION_L_SLL)._type ; //TYPE_SHIFT; |
---|
| 2334 | inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; |
---|
[78] | 2335 | inst->_has_immediat = 0; |
---|
| 2336 | // inst->_immediat = ; |
---|
| 2337 | inst->_read_ra = 1; |
---|
| 2338 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2339 | inst->_read_rb = 1; |
---|
| 2340 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2341 | inst->_read_rc = 0; |
---|
| 2342 | // inst->_num_reg_rc = ; |
---|
| 2343 | inst->_write_rd = 1; |
---|
| 2344 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2345 | inst->_write_re = 0; |
---|
| 2346 | // inst->_num_reg_re = ; |
---|
| 2347 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2348 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2349 | // inst->_branch_condition = ; |
---|
| 2350 | // inst->_branch_stack_write = ; |
---|
| 2351 | // inst->_branch_direction = ; |
---|
| 2352 | // inst->_address_next = ; |
---|
[88] | 2353 | inst->_no_execute = 0; |
---|
[78] | 2354 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2355 | } |
---|
| 2356 | |
---|
| 2357 | void instruction_l_slli (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2358 | { |
---|
| 2359 | log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli"); |
---|
| 2360 | |
---|
[88] | 2361 | inst->_type = instruction_information(INSTRUCTION_L_SLLI)._type ; //TYPE_SHIFT; |
---|
| 2362 | inst->_operation = instruction_information(INSTRUCTION_L_SLLI)._operation; //OPERATION_SHIFT_L_SLL; |
---|
[78] | 2363 | inst->_has_immediat = 1; |
---|
| 2364 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 2365 | inst->_read_ra = 1; |
---|
| 2366 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2367 | inst->_read_rb = 0; |
---|
| 2368 | // inst->_num_reg_rb = ; |
---|
| 2369 | inst->_read_rc = 0; |
---|
| 2370 | // inst->_num_reg_rc = ; |
---|
| 2371 | inst->_write_rd = 1; |
---|
| 2372 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2373 | inst->_write_re = 0; |
---|
| 2374 | // inst->_num_reg_re = ; |
---|
| 2375 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2376 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2377 | // inst->_branch_condition = ; |
---|
| 2378 | // inst->_branch_stack_write = ; |
---|
| 2379 | // inst->_branch_direction = ; |
---|
| 2380 | // inst->_address_next = ; |
---|
[88] | 2381 | inst->_no_execute = 0; |
---|
[78] | 2382 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2383 | } |
---|
| 2384 | |
---|
| 2385 | void instruction_l_sra (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2386 | { |
---|
| 2387 | log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra"); |
---|
| 2388 | |
---|
[88] | 2389 | inst->_type = instruction_information(INSTRUCTION_L_SRA)._type ; //TYPE_SHIFT; |
---|
| 2390 | inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; |
---|
[78] | 2391 | inst->_has_immediat = 0; |
---|
| 2392 | // inst->_immediat = ; |
---|
| 2393 | inst->_read_ra = 1; |
---|
| 2394 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2395 | inst->_read_rb = 1; |
---|
| 2396 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2397 | inst->_read_rc = 0; |
---|
| 2398 | // inst->_num_reg_rc = ; |
---|
| 2399 | inst->_write_rd = 1; |
---|
| 2400 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2401 | inst->_write_re = 0; |
---|
| 2402 | // inst->_num_reg_re = ; |
---|
| 2403 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2404 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2405 | // inst->_branch_condition = ; |
---|
| 2406 | // inst->_branch_stack_write = ; |
---|
| 2407 | // inst->_branch_direction = ; |
---|
| 2408 | // inst->_address_next = ; |
---|
[88] | 2409 | inst->_no_execute = 0; |
---|
[78] | 2410 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2411 | } |
---|
| 2412 | |
---|
| 2413 | void instruction_l_srai (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2414 | { |
---|
| 2415 | log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai"); |
---|
| 2416 | |
---|
[88] | 2417 | inst->_type = instruction_information(INSTRUCTION_L_SRAI)._type ; //TYPE_SHIFT; |
---|
| 2418 | inst->_operation = instruction_information(INSTRUCTION_L_SRAI)._operation; //OPERATION_SHIFT_L_SRA; |
---|
[78] | 2419 | inst->_has_immediat = 1; |
---|
| 2420 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 2421 | inst->_read_ra = 1; |
---|
| 2422 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2423 | inst->_read_rb = 0; |
---|
| 2424 | // inst->_num_reg_rb = ; |
---|
| 2425 | inst->_read_rc = 0; |
---|
| 2426 | // inst->_num_reg_rc = ; |
---|
| 2427 | inst->_write_rd = 1; |
---|
| 2428 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2429 | inst->_write_re = 0; |
---|
| 2430 | // inst->_num_reg_re = ; |
---|
| 2431 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2432 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2433 | // inst->_branch_condition = ; |
---|
| 2434 | // inst->_branch_stack_write = ; |
---|
| 2435 | // inst->_branch_direction = ; |
---|
| 2436 | // inst->_address_next = ; |
---|
[88] | 2437 | inst->_no_execute = 0; |
---|
[78] | 2438 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2439 | } |
---|
| 2440 | |
---|
| 2441 | void instruction_l_srl (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2442 | { |
---|
| 2443 | log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl"); |
---|
| 2444 | |
---|
[88] | 2445 | inst->_type = instruction_information(INSTRUCTION_L_SRL)._type ; //TYPE_SHIFT; |
---|
| 2446 | inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; |
---|
[78] | 2447 | inst->_has_immediat = 0; |
---|
| 2448 | // inst->_immediat = ; |
---|
| 2449 | inst->_read_ra = 1; |
---|
| 2450 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2451 | inst->_read_rb = 1; |
---|
| 2452 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2453 | inst->_read_rc = 0; |
---|
| 2454 | // inst->_num_reg_rc = ; |
---|
| 2455 | inst->_write_rd = 1; |
---|
| 2456 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2457 | inst->_write_re = 0; |
---|
| 2458 | // inst->_num_reg_re = ; |
---|
| 2459 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2460 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2461 | // inst->_branch_condition = ; |
---|
| 2462 | // inst->_branch_stack_write = ; |
---|
| 2463 | // inst->_branch_direction = ; |
---|
| 2464 | // inst->_address_next = ; |
---|
[88] | 2465 | inst->_no_execute = 0; |
---|
[78] | 2466 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2467 | } |
---|
| 2468 | |
---|
| 2469 | void instruction_l_srli (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2470 | { |
---|
| 2471 | log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli"); |
---|
| 2472 | |
---|
[88] | 2473 | inst->_type = instruction_information(INSTRUCTION_L_SRLI)._type ; //TYPE_SHIFT; |
---|
| 2474 | inst->_operation = instruction_information(INSTRUCTION_L_SRLI)._operation; //OPERATION_SHIFT_L_SRL; |
---|
[78] | 2475 | inst->_has_immediat = 1; |
---|
| 2476 | inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); |
---|
| 2477 | inst->_read_ra = 1; |
---|
| 2478 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2479 | inst->_read_rb = 0; |
---|
| 2480 | // inst->_num_reg_rb = ; |
---|
| 2481 | inst->_read_rc = 0; |
---|
| 2482 | // inst->_num_reg_rc = ; |
---|
| 2483 | inst->_write_rd = 1; |
---|
| 2484 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2485 | inst->_write_re = 0; |
---|
| 2486 | // inst->_num_reg_re = ; |
---|
| 2487 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2488 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2489 | // inst->_branch_condition = ; |
---|
| 2490 | // inst->_branch_stack_write = ; |
---|
| 2491 | // inst->_branch_direction = ; |
---|
| 2492 | // inst->_address_next = ; |
---|
[88] | 2493 | inst->_no_execute = 0; |
---|
[78] | 2494 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2495 | } |
---|
| 2496 | |
---|
| 2497 | void instruction_l_sub (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2498 | { |
---|
| 2499 | log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub"); |
---|
| 2500 | |
---|
[88] | 2501 | inst->_type = instruction_information(INSTRUCTION_L_SUB)._type ; //TYPE_ALU; |
---|
| 2502 | inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; |
---|
[78] | 2503 | inst->_has_immediat = 0; |
---|
| 2504 | // inst->_immediat = ; |
---|
| 2505 | inst->_read_ra = 1; |
---|
| 2506 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2507 | inst->_read_rb = 1; |
---|
| 2508 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2509 | inst->_read_rc = 0; |
---|
| 2510 | // inst->_num_reg_rc = ; |
---|
| 2511 | inst->_write_rd = 1; |
---|
| 2512 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2513 | inst->_write_re = 1; |
---|
| 2514 | inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; |
---|
| 2515 | inst->_exception_use = EXCEPTION_USE_RANGE; |
---|
[88] | 2516 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2517 | // inst->_branch_condition = ; |
---|
| 2518 | // inst->_branch_stack_write = ; |
---|
| 2519 | // inst->_branch_direction = ; |
---|
| 2520 | // inst->_address_next = ; |
---|
[88] | 2521 | inst->_no_execute = 0; |
---|
[78] | 2522 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2523 | } |
---|
| 2524 | |
---|
| 2525 | void instruction_l_sw (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2526 | { |
---|
| 2527 | log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw"); |
---|
| 2528 | |
---|
[88] | 2529 | inst->_type = instruction_information(INSTRUCTION_L_SW)._type ; //TYPE_MEMORY; |
---|
| 2530 | inst->_operation = instruction_information(INSTRUCTION_L_SW)._operation; //OPERATION_MEMORY_STORE_32; |
---|
[78] | 2531 | inst->_has_immediat = 1; |
---|
| 2532 | inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| |
---|
| 2533 | (range<Tgeneral_data_t >(inst->_instruction,10, 0))),16); |
---|
| 2534 | inst->_read_ra = 1; |
---|
| 2535 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2536 | inst->_read_rb = 1; |
---|
| 2537 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2538 | inst->_read_rc = 0; |
---|
| 2539 | // inst->_num_reg_rc = ; |
---|
| 2540 | inst->_write_rd = 0; |
---|
| 2541 | // inst->_num_reg_rd = ; |
---|
| 2542 | inst->_write_re = 0; |
---|
| 2543 | // inst->_num_reg_re = ; |
---|
| 2544 | inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; |
---|
[88] | 2545 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2546 | // inst->_branch_condition = ; |
---|
| 2547 | // inst->_branch_stack_write = ; |
---|
| 2548 | // inst->_branch_direction = ; |
---|
| 2549 | // inst->_address_next = ; |
---|
[88] | 2550 | inst->_no_execute = 0; |
---|
[78] | 2551 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2552 | } |
---|
| 2553 | |
---|
| 2554 | void instruction_l_sys (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2555 | { |
---|
| 2556 | log_printf(TRACE,Decod,"instruction_l_sys"," * instruction : l.sys"); |
---|
| 2557 | |
---|
| 2558 | if (range<uint32_t>(inst->_instruction,22,16) != 0) |
---|
| 2559 | { |
---|
| 2560 | instruction_illegal (inst, param); |
---|
| 2561 | } |
---|
| 2562 | else |
---|
| 2563 | { |
---|
[88] | 2564 | inst->_type = instruction_information(INSTRUCTION_L_SYS)._type ; //TYPE_SPECIAL; |
---|
| 2565 | inst->_operation = instruction_information(INSTRUCTION_L_SYS)._operation; //OPERATION_SPECIAL_L_SYS; |
---|
[78] | 2566 | // inst->_has_immediat = 1; |
---|
| 2567 | // inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 2568 | inst->_has_immediat = 0; |
---|
| 2569 | // inst->_immediat = ; |
---|
| 2570 | inst->_read_ra = 0; |
---|
| 2571 | // inst->_num_reg_ra = ; |
---|
| 2572 | inst->_read_rb = 0; |
---|
| 2573 | // inst->_num_reg_rb = ; |
---|
| 2574 | inst->_read_rc = 0; |
---|
| 2575 | // inst->_num_reg_rc = ; |
---|
| 2576 | inst->_write_rd = 0; |
---|
| 2577 | // inst->_num_reg_rd = ; |
---|
| 2578 | inst->_write_re = 0; |
---|
| 2579 | // inst->_num_reg_re = ; |
---|
| 2580 | inst->_exception_use = EXCEPTION_USE_SYSCALL; |
---|
[88] | 2581 | inst->_exception = EXCEPTION_SYSCALL; |
---|
[78] | 2582 | // inst->_branch_condition = ; |
---|
| 2583 | // inst->_branch_stack_write = ; |
---|
| 2584 | // inst->_branch_direction = ; |
---|
| 2585 | |
---|
| 2586 | // if (inst->_is_delay_slot) |
---|
| 2587 | // inst->_address_next = inst->_address_previous; |
---|
| 2588 | // else |
---|
| 2589 | // inst->_address_next = inst->_address; |
---|
| 2590 | |
---|
| 2591 | |
---|
| 2592 | // inst->_address_next = ; // don't change |
---|
[88] | 2593 | inst->_no_execute = 1; |
---|
[78] | 2594 | inst->_event_type = EVENT_TYPE_EXCEPTION; |
---|
| 2595 | } |
---|
| 2596 | } |
---|
| 2597 | |
---|
| 2598 | void instruction_l_trap (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2599 | { |
---|
| 2600 | log_printf(TRACE,Decod,"instruction_l_trap"," * instruction : l.trap"); |
---|
| 2601 | |
---|
| 2602 | if (range<uint32_t>(inst->_instruction,22,16) != 0) |
---|
| 2603 | { |
---|
| 2604 | instruction_illegal (inst, param); |
---|
| 2605 | } |
---|
| 2606 | else |
---|
| 2607 | { |
---|
[88] | 2608 | inst->_type = instruction_information(INSTRUCTION_L_TRAP)._type ; //TYPE_SPECIAL; |
---|
| 2609 | inst->_operation = instruction_information(INSTRUCTION_L_TRAP)._operation; //OPERATION_SPECIAL_L_TRAP; |
---|
[78] | 2610 | inst->_has_immediat = 1; |
---|
| 2611 | inst->_immediat = EXTENDZ(inst->_instruction,16); |
---|
| 2612 | inst->_read_ra = 0; |
---|
| 2613 | // inst->_num_reg_ra = ; |
---|
| 2614 | inst->_read_rb = 0; |
---|
| 2615 | // inst->_num_reg_rb = ; |
---|
| 2616 | inst->_read_rc = 0; // read all SR |
---|
| 2617 | // inst->_num_reg_rc = ; |
---|
| 2618 | inst->_write_rd = 0; |
---|
| 2619 | // inst->_num_reg_rd = ; |
---|
| 2620 | inst->_write_re = 0; |
---|
| 2621 | // inst->_num_reg_re = ; |
---|
| 2622 | inst->_exception_use = EXCEPTION_USE_TRAP; |
---|
[88] | 2623 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2624 | // inst->_branch_condition = ; |
---|
| 2625 | // inst->_branch_stack_write = ; |
---|
| 2626 | // inst->_branch_direction = ; |
---|
| 2627 | // inst->_address_next = ; |
---|
[88] | 2628 | inst->_no_execute = 1; |
---|
[78] | 2629 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2630 | } |
---|
| 2631 | } |
---|
| 2632 | |
---|
| 2633 | void instruction_l_xor (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2634 | { |
---|
| 2635 | log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor"); |
---|
| 2636 | |
---|
[88] | 2637 | inst->_type = instruction_information(INSTRUCTION_L_XOR)._type ; //TYPE_ALU; |
---|
| 2638 | inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; |
---|
[78] | 2639 | inst->_has_immediat = 0; |
---|
| 2640 | // inst->_immediat = ; |
---|
| 2641 | inst->_read_ra = 1; |
---|
| 2642 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2643 | inst->_read_rb = 1; |
---|
| 2644 | inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); |
---|
| 2645 | inst->_read_rc = 0; |
---|
| 2646 | // inst->_num_reg_rc = ; |
---|
| 2647 | inst->_write_rd = 1; |
---|
| 2648 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2649 | inst->_write_re = 0; |
---|
| 2650 | // inst->_num_reg_re = ; |
---|
| 2651 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2652 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2653 | // inst->_branch_condition = ; |
---|
| 2654 | // inst->_branch_stack_write = ; |
---|
| 2655 | // inst->_branch_direction = ; |
---|
| 2656 | // inst->_address_next = ; |
---|
[88] | 2657 | inst->_no_execute = 0; |
---|
[78] | 2658 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2659 | } |
---|
| 2660 | |
---|
| 2661 | void instruction_l_xori (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2662 | { |
---|
| 2663 | log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori"); |
---|
| 2664 | |
---|
[88] | 2665 | inst->_type = instruction_information(INSTRUCTION_L_XORI)._type ; //TYPE_ALU; |
---|
| 2666 | inst->_operation = instruction_information(INSTRUCTION_L_XORI)._operation; //OPERATION_ALU_L_XOR; |
---|
[78] | 2667 | inst->_has_immediat = 1; |
---|
| 2668 | inst->_immediat = EXTENDS(inst->_instruction,16); |
---|
| 2669 | inst->_read_ra = 1; |
---|
| 2670 | inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); |
---|
| 2671 | inst->_read_rb = 0; |
---|
| 2672 | // inst->_num_reg_rb = ; |
---|
| 2673 | inst->_read_rc = 0; |
---|
| 2674 | // inst->_num_reg_rc = ; |
---|
| 2675 | inst->_write_rd = 1; |
---|
| 2676 | inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); |
---|
| 2677 | inst->_write_re = 0; |
---|
| 2678 | // inst->_num_reg_re = ; |
---|
| 2679 | inst->_exception_use = EXCEPTION_USE_NONE; |
---|
[88] | 2680 | inst->_exception = EXCEPTION_DECOD_NONE; |
---|
[78] | 2681 | // inst->_branch_condition = ; |
---|
| 2682 | // inst->_branch_stack_write = ; |
---|
| 2683 | // inst->_branch_direction = ; |
---|
| 2684 | // inst->_address_next = ; |
---|
[88] | 2685 | inst->_no_execute = 0; |
---|
[78] | 2686 | inst->_event_type = EVENT_TYPE_NONE; |
---|
| 2687 | } |
---|
| 2688 | |
---|
| 2689 | // // ORFPX |
---|
| 2690 | // void instruction_lf_add_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2691 | // void instruction_lf_add_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2692 | // void instruction_lf_cust1_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2693 | // void instruction_lf_cust1_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2694 | // void instruction_lf_div_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2695 | // void instruction_lf_div_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2696 | // void instruction_lf_ftoi_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2697 | // void instruction_lf_ftoi_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2698 | // void instruction_lf_itof_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2699 | // void instruction_lf_itof_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2700 | // void instruction_lf_madd_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2701 | // void instruction_lf_madd_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2702 | // void instruction_lf_mul_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2703 | // void instruction_lf_mul_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2704 | // void instruction_lf_rem_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2705 | // void instruction_lf_rem_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2706 | // void instruction_lf_sfeq_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2707 | // void instruction_lf_sfeq_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2708 | // void instruction_lf_sfge_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2709 | // void instruction_lf_sfge_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2710 | // void instruction_lf_sfgt_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2711 | // void instruction_lf_sfgt_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2712 | // void instruction_lf_sfle_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2713 | // void instruction_lf_sfle_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2714 | // void instruction_lf_sflt_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2715 | // void instruction_lf_sflt_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2716 | // void instruction_lf_sfne_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2717 | // void instruction_lf_sfne_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2718 | // void instruction_lf_sub_d (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2719 | // void instruction_lf_sub_s (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2720 | |
---|
| 2721 | // // ORVDX |
---|
| 2722 | // void instruction_lv_add_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2723 | // void instruction_lv_add_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2724 | // void instruction_lv_adds_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2725 | // void instruction_lv_adds_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2726 | // void instruction_lv_addu_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2727 | // void instruction_lv_addu_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2728 | // void instruction_lv_addus_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2729 | // void instruction_lv_addus_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2730 | // void instruction_lv_all_eq_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2731 | // void instruction_lv_all_eq_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2732 | // void instruction_lv_all_ge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2733 | // void instruction_lv_all_ge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2734 | // void instruction_lv_all_gt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2735 | // void instruction_lv_all_gt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2736 | // void instruction_lv_all_le_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2737 | // void instruction_lv_all_le_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2738 | // void instruction_lv_all_lt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2739 | // void instruction_lv_all_lt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2740 | // void instruction_lv_all_ne_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2741 | // void instruction_lv_all_ne_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2742 | // void instruction_lv_and (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2743 | // void instruction_lv_any_eq_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2744 | // void instruction_lv_any_eq_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2745 | // void instruction_lv_any_ge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2746 | // void instruction_lv_any_ge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2747 | // void instruction_lv_any_gt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2748 | // void instruction_lv_any_gt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2749 | // void instruction_lv_any_le_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2750 | // void instruction_lv_any_le_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2751 | // void instruction_lv_any_lt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2752 | // void instruction_lv_any_lt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2753 | // void instruction_lv_any_ne_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2754 | // void instruction_lv_any_ne_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2755 | // void instruction_lv_avg_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2756 | // void instruction_lv_avg_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2757 | // void instruction_lv_cmp_eq_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2758 | // void instruction_lv_cmp_eq_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2759 | // void instruction_lv_cmp_ge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2760 | // void instruction_lv_cmp_ge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2761 | // void instruction_lv_cmp_gt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2762 | // void instruction_lv_cmp_gt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2763 | // void instruction_lv_cmp_le_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2764 | // void instruction_lv_cmp_le_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2765 | // void instruction_lv_cmp_lt_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2766 | // void instruction_lv_cmp_lt_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2767 | // void instruction_lv_cmp_ne_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2768 | // void instruction_lv_cmp_ne_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2769 | // void instruction_lv_cust1 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2770 | // void instruction_lv_cust2 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2771 | // void instruction_lv_cust3 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2772 | // void instruction_lv_cust4 (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2773 | // void instruction_lv_madds_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2774 | // void instruction_lv_max_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2775 | // void instruction_lv_max_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2776 | // void instruction_lv_merge_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2777 | // void instruction_lv_merge_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2778 | // void instruction_lv_min_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2779 | // void instruction_lv_min_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2780 | // void instruction_lv_msubs_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2781 | // void instruction_lv_muls_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2782 | // void instruction_lv_nand (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2783 | // void instruction_lv_nor (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2784 | // void instruction_lv_or (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2785 | // void instruction_lv_pack_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2786 | // void instruction_lv_pack_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2787 | // void instruction_lv_packs_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2788 | // void instruction_lv_packs_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2789 | // void instruction_lv_packus_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2790 | // void instruction_lv_packus_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2791 | // void instruction_lv_perm_n (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2792 | // void instruction_lv_rl_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2793 | // void instruction_lv_rl_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2794 | // void instruction_lv_sll (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2795 | // void instruction_lv_sll_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2796 | // void instruction_lv_sll_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2797 | // void instruction_lv_sra_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2798 | // void instruction_lv_sra_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2799 | // void instruction_lv_srl (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2800 | // void instruction_lv_srl_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2801 | // void instruction_lv_srl_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2802 | // void instruction_lv_sub_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2803 | // void instruction_lv_sub_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2804 | // void instruction_lv_subs_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2805 | // void instruction_lv_subs_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2806 | // void instruction_lv_subu_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2807 | // void instruction_lv_subu_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2808 | // void instruction_lv_subus_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2809 | // void instruction_lv_subus_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2810 | // void instruction_lv_unpack_b (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2811 | // void instruction_lv_unpack_h (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2812 | // void instruction_lv_xor (decod_instruction_t * inst, decod_param_t * param) |
---|
| 2813 | |
---|
| 2814 | }; // end namespace decod |
---|
| 2815 | }; // end namespace decod_unit |
---|
| 2816 | }; // end namespace front_end |
---|
| 2817 | }; // end namespace multi_front_end |
---|
| 2818 | }; // end namespace core |
---|
| 2819 | }; // end namespace behavioural |
---|
| 2820 | }; // end namespace morpheo |
---|