[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Decod_genMealy.cpp 145 2010-10-13 18:15:51Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace decod_unit { |
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| 17 | namespace decod { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Decod::genMealy" |
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| 22 | void Decod::genMealy (void) |
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| 23 | { |
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[88] | 24 | log_begin(Decod,FUNCTION); |
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| 25 | log_function(Decod,FUNCTION,_name.c_str()); |
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[78] | 26 | |
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[123] | 27 | if (PORT_READ(in_NRESET)) |
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| 28 | { |
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[78] | 29 | //----------------------------------- |
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| 30 | // Initialization |
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| 31 | //----------------------------------- |
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[86] | 32 | Tcontrol_t context_event_val = false; |
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[78] | 33 | Tcontrol_t ifetch_ack [_param->_nb_context][_param->_max_nb_inst_fetch]; |
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| 34 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 35 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 36 | ifetch_ack [i][j] = false; |
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| 37 | |
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| 38 | Tcontrol_t predict_val [_param->_nb_inst_decod]; |
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| 39 | Tcontrol_t decod_val [_param->_nb_inst_decod]; |
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| 40 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 41 | { |
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| 42 | decod_val [i] = false; |
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[88] | 43 | predict_val [i] = false; |
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[78] | 44 | } |
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| 45 | |
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| 46 | Tcontrol_t can_continue [_param->_nb_context]; |
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[110] | 47 | Tcontrol_t have_decod_branch [_param->_nb_context]; |
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[78] | 48 | |
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[124] | 49 | Tcontext_t CONTEXT_EVENT_CONTEXT_ID = 0; |
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| 50 | Tdepth_t CONTEXT_EVENT_DEPTH = 0; |
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| 51 | Tevent_type_t CONTEXT_EVENT_TYPE = 0; |
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| 52 | Tcontrol_t CONTEXT_EVENT_IS_DELAY_SLOT = 0; |
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| 53 | Tgeneral_data_t CONTEXT_EVENT_ADDRESS = 0; |
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| 54 | Tgeneral_data_t CONTEXT_EVENT_ADDRESS_EPCR = 0; |
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| 55 | |
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[78] | 56 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 57 | { |
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| 58 | internal_CONTEXT_HAVE_TRANSACTION [i] = false; |
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| 59 | internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i]; |
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| 60 | internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i]; |
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[139] | 61 | // internal_CONTEXT_SAVE_RAT [i] = reg_CONTEXT_SAVE_RAT [i]; |
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[87] | 62 | |
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[78] | 63 | can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); |
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[110] | 64 | have_decod_branch [i] = false; |
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[78] | 65 | } |
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| 66 | |
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| 67 | //----------------------------------- |
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| 68 | // Loop of decod |
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| 69 | //----------------------------------- |
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| 70 | // scan all decod "slot_out" |
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[88] | 71 | std::list<generic::priority::select_t> * select = _priority->select(); |
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| 72 | std::list<generic::priority::select_t>::iterator it=select->begin(); |
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[145] | 73 | |
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[78] | 74 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 75 | { |
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[119] | 76 | log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i); |
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| 77 | |
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[124] | 78 | bool ifetch_val = false; |
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[145] | 79 | |
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| 80 | while ((it != select->end()) and // have a no scanned instruction from ifetch_unit ? |
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[124] | 81 | // (decod_val [i] == false) and // have not a previous selected entry? |
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| 82 | (ifetch_val == false) and // not find ifetch instruction valid |
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[145] | 83 | (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) (ONCE CONTEXT PER CYCLE (context state moore easy)) |
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[78] | 84 | { |
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[107] | 85 | // predict_val [i] = false; |
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[78] | 86 | |
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[145] | 87 | Tcontext_t x = it->grp; // num_front_end |
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| 88 | uint32_t y = it->elt; // num_instruction |
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[78] | 89 | |
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[119] | 90 | log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); |
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| 91 | log_printf(TRACE,Decod,FUNCTION," * in_IFETCH_VAL : %d",PORT_READ(in_IFETCH_VAL [x][y])); |
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| 92 | log_printf(TRACE,Decod,FUNCTION," * can_continue : %d",can_continue [x] ); |
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| 93 | |
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[78] | 94 | // Test if this instruction is valid |
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| 95 | if ((PORT_READ(in_IFETCH_VAL [x][y]) == 1) and // entry is valid |
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| 96 | (can_continue [x] == 1)) // context can decod instruction (have not a previous event) |
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| 97 | { |
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[119] | 98 | log_printf(TRACE,Decod,FUNCTION," * decod_ack : %d",PORT_READ(in_DECOD_ACK [i])); |
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[78] | 99 | |
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[124] | 100 | ifetch_val = true; |
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[78] | 101 | decod_val [i] = true; // fetch_val and decod_enable |
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| 102 | ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack |
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| 103 | |
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[136] | 104 | Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x][y]); |
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[78] | 105 | |
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[145] | 106 | // Read instruction and set default value |
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[134] | 107 | _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); |
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| 108 | _decod_instruction->_context_id = x; |
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| 109 | _decod_instruction->_address_previous = internal_CONTEXT_ADDRESS_PREVIOUS [x]; |
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| 110 | _decod_instruction->_address = addr; //Compute the current address |
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| 111 | _decod_instruction->_address_next = addr+1; |
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| 112 | _decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x]; |
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[137] | 113 | #ifdef STATISTICS |
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| 114 | _decod_instruction->_opcod = -1; // not necessary |
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| 115 | #endif |
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[134] | 116 | _decod_instruction->_type = 0; // not necessary |
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| 117 | _decod_instruction->_operation = 0; // not necessary |
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| 118 | _decod_instruction->_no_execute = 0; // not necessary |
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| 119 | _decod_instruction->_has_immediat = 0; // not necessary |
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| 120 | _decod_instruction->_immediat = 0; // not necessary |
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| 121 | _decod_instruction->_read_ra = 0; // not necessary |
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| 122 | _decod_instruction->_num_reg_ra = 0; // not necessary |
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| 123 | _decod_instruction->_read_rb = 0; // not necessary |
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| 124 | _decod_instruction->_num_reg_rb = 0; // not necessary |
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| 125 | _decod_instruction->_read_rc = 0; // not necessary |
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| 126 | _decod_instruction->_num_reg_rc = 0; // not necessary |
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| 127 | _decod_instruction->_write_rd = 0; // not necessary |
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| 128 | _decod_instruction->_num_reg_rd = 0; // not necessary |
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| 129 | _decod_instruction->_write_re = 0; // not necessary |
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| 130 | _decod_instruction->_num_reg_re = 0; // not necessary |
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| 131 | _decod_instruction->_exception_use = EXCEPTION_USE_NONE; // not necessary |
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| 132 | _decod_instruction->_exception = EXCEPTION_DECOD_NONE; // not necessary |
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| 133 | _decod_instruction->_branch_condition = 0; // not necessary |
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| 134 | // _decod_instruction->_branch_stack_write = 0; // not necessary |
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| 135 | _decod_instruction->_branch_direction = 0; // not necessary |
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| 136 | _decod_instruction->_event_type = EVENT_TYPE_NONE; // not necessary |
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[78] | 137 | |
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[145] | 138 | // Test if ifetch_unit have an exception (per example : IBERR) |
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[136] | 139 | Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x][y]); |
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[86] | 140 | |
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[88] | 141 | if (ifetch_exception == EXCEPTION_IFETCH_NONE) |
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| 142 | { |
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[145] | 143 | // No exception, can Decod ! |
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[119] | 144 | log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2)); |
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| 145 | log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); |
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[88] | 146 | |
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| 147 | instruction_decod (_decod_instruction, _decod_param[x]); |
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[107] | 148 | |
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[119] | 149 | log_printf(TRACE,Decod,FUNCTION," * address_next : %.8x (%.8x)",_decod_instruction->_address_next,(_decod_instruction->_address_next<<2)); |
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[88] | 150 | } |
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| 151 | else |
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| 152 | { |
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[145] | 153 | // Exception : transform this instruction in a nop |
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| 154 | // * INSTRUCTION_TLB |
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| 155 | // * INSTRUCTION_PAGE |
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| 156 | // * BUS_ERROR |
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| 157 | |
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| 158 | log_printf(TRACE,Decod,FUNCTION," * exception -> change instruction in a l.nop"); |
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| 159 | |
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[88] | 160 | instruction_l_nop (_decod_instruction, _decod_param[x]); |
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[78] | 161 | |
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[88] | 162 | _decod_instruction->_exception_use = EXCEPTION_USE_NONE; |
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| 163 | _decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception); |
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| 164 | |
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| 165 | if (_decod_instruction->_is_delay_slot) |
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| 166 | _decod_instruction->_address_next = _decod_instruction->_address_previous; |
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| 167 | else |
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| 168 | _decod_instruction->_address_next = _decod_instruction->_address; |
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| 169 | |
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| 170 | _decod_instruction->_event_type = EVENT_TYPE_EXCEPTION; |
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| 171 | } |
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[78] | 172 | |
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[145] | 173 | Ttype_t type = _decod_instruction->_type; |
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| 174 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; |
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| 175 | Tbranch_condition_t branch_condition = _decod_instruction->_branch_condition; |
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| 176 | |
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| 177 | // Save RAT if instruction is a branch and is conditionnal (not l.j and not l.jal) |
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[88] | 178 | |
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[145] | 179 | //Tcontrol_t save_rat = internal_CONTEXT_SAVE_RAT [x]; |
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| 180 | // Tcontrol_t save_rat = ((type == TYPE_BRANCH) and |
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| 181 | // not ((branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK) or |
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| 182 | // (branch_condition==BRANCH_CONDITION_NONE_WITH_WRITE_STACK))); |
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| 183 | |
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| 184 | Tcontrol_t save_rat = ((type == TYPE_BRANCH) and |
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| 185 | not (branch_condition==BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK)); |
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| 186 | |
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| 187 | // FIXME : depth+1 valid ??????? |
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[110] | 188 | if ((_param->_nb_branch_speculated[x] > 0) and have_decod_branch [x]) |
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| 189 | depth = (depth+1)%_param->_nb_branch_speculated[x]; |
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[145] | 190 | |
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| 191 | // Write output |
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[78] | 192 | if (_param->_have_port_context_id) |
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| 193 | PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); |
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| 194 | if (_param->_have_port_depth) |
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[88] | 195 | PORT_WRITE(out_DECOD_DEPTH [i], depth); |
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[137] | 196 | #ifdef STATISTICS |
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| 197 | PORT_WRITE(out_DECOD_INSTRUCTION [i], _decod_instruction->_opcod ); |
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| 198 | #endif |
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[78] | 199 | PORT_WRITE(out_DECOD_TYPE [i], type); |
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| 200 | PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); |
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[145] | 201 | PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); |
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[78] | 202 | PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); |
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[145] | 203 | PORT_WRITE(out_DECOD_SAVE_RAT [i], save_rat); |
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[108] | 204 | #ifdef DEBUG |
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| 205 | PORT_WRITE(out_DECOD_ADDRESS [i], addr); |
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| 206 | #endif |
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[105] | 207 | PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next ); |
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[78] | 208 | PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); |
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| 209 | PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat ); |
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| 210 | PORT_WRITE(out_DECOD_READ_RA [i], _decod_instruction->_read_ra ); |
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| 211 | PORT_WRITE(out_DECOD_NUM_REG_RA [i], _decod_instruction->_num_reg_ra ); |
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| 212 | PORT_WRITE(out_DECOD_READ_RB [i], _decod_instruction->_read_rb ); |
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| 213 | PORT_WRITE(out_DECOD_NUM_REG_RB [i], _decod_instruction->_num_reg_rb ); |
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| 214 | PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); |
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| 215 | PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); |
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[145] | 216 | PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0); // don't write in RD if RD=0 |
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[78] | 217 | PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); |
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| 218 | PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); |
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| 219 | PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re ); |
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| 220 | PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use ); |
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[135] | 221 | PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception ); |
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[78] | 222 | |
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[101] | 223 | // Branch predictor can accept : the depth is valid |
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[119] | 224 | log_printf(TRACE,Decod,FUNCTION," * context_depth_val : %d",PORT_READ(in_CONTEXT_DEPTH_VAL [x])); |
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[134] | 225 | |
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[101] | 226 | decod_val [i] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); |
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| 227 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]); |
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| 228 | |
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[78] | 229 | if (type == TYPE_BRANCH) |
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| 230 | { |
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[119] | 231 | log_printf(TRACE,Decod,FUNCTION," * Instruction is branch"); |
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| 232 | log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]); |
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| 233 | log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); |
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| 234 | log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); |
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| 235 | log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); |
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[107] | 236 | |
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[145] | 237 | // test if have already decod an branch : ONCE BRANCH PER CONTEXT |
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| 238 | predict_val [i] = not have_decod_branch [x] and ifetch_ack [x][y]; // and decod_val [i] |
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[110] | 239 | decod_val [i] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable |
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| 240 | ifetch_ack [x][y] &= not have_decod_branch [x] and PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack |
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[101] | 241 | |
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[110] | 242 | // can continue is set if direction is "not take" (also, continue is sequential order) |
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| 243 | |
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| 244 | // can_continue [x] = false; // one branch per context, the DS don't execute |
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[120] | 245 | can_continue [x]&= PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // one branch per context, the DS don't execute |
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[110] | 246 | have_decod_branch [x] = true; |
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[120] | 247 | |
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| 248 | log_printf(TRACE,Decod,FUNCTION," * predict_can_continue : %d",PORT_READ(in_PREDICT_CAN_CONTINUE [i])); |
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| 249 | } |
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[78] | 250 | |
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[136] | 251 | Tbranch_state_t ifetch_branch_state = PORT_READ(in_IFETCH_BRANCH_STATE [x][y]); |
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[124] | 252 | if (_param->_have_port_context_id) |
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| 253 | PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); |
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[136] | 254 | // PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); |
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| 255 | PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],ifetch_branch_state != BRANCH_STATE_NONE); |
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| 256 | |
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| 257 | PORT_WRITE(out_PREDICT_BRANCH_STATE [i],ifetch_branch_state); |
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[124] | 258 | if (_param->_have_port_depth) |
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[136] | 259 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x][y])); |
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[145] | 260 | PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],branch_condition); |
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[124] | 261 | // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); |
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| 262 | PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); |
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| 263 | PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address ); |
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| 264 | PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next ); |
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| 265 | |
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[78] | 266 | Tevent_type_t event_type = _decod_instruction->_event_type; |
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| 267 | if (event_type != EVENT_TYPE_NONE) |
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| 268 | { |
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[119] | 269 | log_printf(TRACE,Decod,FUNCTION," * Instruction make an EVENT (%s)",toString(event_type).c_str()); |
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| 270 | log_printf(TRACE,Decod,FUNCTION," * context_event_ack : %d",PORT_READ(in_CONTEXT_EVENT_ACK)); |
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| 271 | |
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[78] | 272 | // speculative jump at the exception handler |
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| 273 | // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE |
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[145] | 274 | context_event_val = ifetch_ack [x][y]; // and decod_val [i] |
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[78] | 275 | decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable |
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| 276 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack |
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| 277 | |
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[124] | 278 | CONTEXT_EVENT_CONTEXT_ID = x; |
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| 279 | CONTEXT_EVENT_DEPTH = depth; |
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| 280 | CONTEXT_EVENT_TYPE = _decod_instruction->_event_type; |
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| 281 | CONTEXT_EVENT_IS_DELAY_SLOT = _decod_instruction->_is_delay_slot; |
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| 282 | CONTEXT_EVENT_ADDRESS = _decod_instruction->_address; |
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| 283 | CONTEXT_EVENT_ADDRESS_EPCR = _decod_instruction->_address_next ; |
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[78] | 284 | } |
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| 285 | |
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| 286 | // fetch_ack = |
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| 287 | // ((event_type == EVENT_TYPE_NONE) or ((event_type != EVENT_TYPE_NONE) and context_event_ack)) and |
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| 288 | // ((type == TYPE_BRANCH ) or ((type != TYPE_BRANCH ) and predict_ack )) and |
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| 289 | // fetch_val and decod_ack and decod_enable and true (is decod_val) |
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| 290 | |
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| 291 | // To compute the "next previous" address |
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| 292 | Tcontrol_t have_transaction = ifetch_ack [x][y]; |
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| 293 | |
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| 294 | internal_CONTEXT_HAVE_TRANSACTION [x] |= have_transaction; |
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| 295 | if (have_transaction) |
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| 296 | { |
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| 297 | internal_CONTEXT_ADDRESS_PREVIOUS [x] = addr; |
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| 298 | internal_CONTEXT_IS_DELAY_SLOT [x] = (type == TYPE_BRANCH); // next is a delay slot if current have branch type |
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[139] | 299 | // internal_CONTEXT_SAVE_RAT [x] = ((type == TYPE_BRANCH) and not no_execute); |
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[78] | 300 | } |
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| 301 | |
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| 302 | can_continue [x] &= have_transaction; // to have a in order decod !!! if a previous instruction can decod, also next instruction can't decod. |
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[120] | 303 | |
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| 304 | log_printf(TRACE,Decod,FUNCTION," * have_transaction : %d",have_transaction); |
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| 305 | |
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[78] | 306 | } |
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[87] | 307 | |
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[88] | 308 | log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y); |
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[119] | 309 | log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]); |
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| 310 | log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val ); |
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| 311 | log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] ); |
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| 312 | log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] ); |
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[78] | 313 | |
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| 314 | it ++; |
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| 315 | } |
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| 316 | } |
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[124] | 317 | |
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[78] | 318 | //----------------------------------- |
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| 319 | // Write output |
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| 320 | //----------------------------------- |
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| 321 | |
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| 322 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 323 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 324 | PORT_WRITE(out_IFETCH_ACK [i][j], ifetch_ack [i][j]); |
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| 325 | |
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| 326 | PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val); |
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[124] | 327 | if (_param->_have_port_context_id) |
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| 328 | PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , CONTEXT_EVENT_CONTEXT_ID ); |
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| 329 | if (_param->_have_port_depth) |
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| 330 | PORT_WRITE(out_CONTEXT_EVENT_DEPTH , CONTEXT_EVENT_DEPTH ); |
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| 331 | PORT_WRITE(out_CONTEXT_EVENT_TYPE , CONTEXT_EVENT_TYPE ); |
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| 332 | PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, CONTEXT_EVENT_IS_DELAY_SLOT); |
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| 333 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , CONTEXT_EVENT_ADDRESS ); |
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| 334 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , CONTEXT_EVENT_ADDRESS_EPCR ); |
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[78] | 335 | |
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| 336 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 337 | { |
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| 338 | PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]); |
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| 339 | PORT_WRITE(out_DECOD_VAL [i], decod_val [i]); |
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[88] | 340 | |
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| 341 | #ifdef STATISTICS |
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| 342 | internal_DECOD_VAL [i] = decod_val [i]; |
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| 343 | #endif |
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[78] | 344 | } |
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[123] | 345 | } |
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| 346 | else |
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| 347 | { |
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| 348 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 349 | { |
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| 350 | internal_CONTEXT_HAVE_TRANSACTION [i] = false; |
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| 351 | // internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i]; |
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| 352 | // internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i]; |
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| 353 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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| 354 | PORT_WRITE(out_IFETCH_ACK [i][j], 0); |
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| 355 | } |
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[78] | 356 | |
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[123] | 357 | PORT_WRITE(out_CONTEXT_EVENT_VAL, 0); |
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| 358 | |
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| 359 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 360 | { |
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| 361 | PORT_WRITE(out_PREDICT_VAL [i], 0); |
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| 362 | PORT_WRITE(out_DECOD_VAL [i], 0); |
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| 363 | |
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| 364 | #ifdef STATISTICS |
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| 365 | internal_DECOD_VAL [i] = 0; |
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| 366 | #endif |
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| 367 | } |
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| 368 | } |
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| 369 | |
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[88] | 370 | log_end(Decod,FUNCTION); |
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[78] | 371 | }; |
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| 372 | |
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| 373 | }; // end namespace decod |
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| 374 | }; // end namespace decod_unit |
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| 375 | }; // end namespace front_end |
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| 376 | }; // end namespace multi_front_end |
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| 377 | }; // end namespace core |
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| 378 | |
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| 379 | }; // end namespace behavioural |
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| 380 | }; // end namespace morpheo |
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| 381 | #endif |
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