1 | /* |
---|
2 | * $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $ |
---|
3 | * |
---|
4 | * [ Description ] |
---|
5 | * |
---|
6 | * Test |
---|
7 | */ |
---|
8 | |
---|
9 | |
---|
10 | #define NB_ITERATION 1024 |
---|
11 | #define CYCLE_MAX (128*NB_ITERATION) |
---|
12 | |
---|
13 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h" |
---|
14 | #include "Common/include/Test.h" |
---|
15 | #include "Behavioural/include/Allocation.h" |
---|
16 | |
---|
17 | void test (string name, |
---|
18 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param) |
---|
19 | { |
---|
20 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
---|
21 | |
---|
22 | #ifdef STATISTICS |
---|
23 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
---|
24 | #endif |
---|
25 | |
---|
26 | Tusage_t _usage = USE_ALL; |
---|
27 | |
---|
28 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
---|
29 | // _usage = usage_unset(_usage,USE_VHDL ); |
---|
30 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
---|
31 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
---|
32 | // _usage = usage_unset(_usage,USE_POSITION ); |
---|
33 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
---|
34 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
---|
35 | |
---|
36 | Address_management * _Address_management = new Address_management |
---|
37 | (name.c_str(), |
---|
38 | #ifdef STATISTICS |
---|
39 | _parameters_statistics, |
---|
40 | #endif |
---|
41 | _param, |
---|
42 | _usage); |
---|
43 | |
---|
44 | #ifdef SYSTEMC |
---|
45 | /********************************************************************* |
---|
46 | * Déclarations des signaux |
---|
47 | *********************************************************************/ |
---|
48 | string rename; |
---|
49 | |
---|
50 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
---|
51 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
---|
52 | |
---|
53 | sc_signal<Tcontrol_t > * out_ADDRESS_VAL ; |
---|
54 | sc_signal<Tcontrol_t > * in_ADDRESS_ACK ; //icache_req_ack and ifetch_queue_ack |
---|
55 | sc_signal<Tgeneral_address_t> * out_ADDRESS_INSTRUCTION_ADDRESS ; |
---|
56 | sc_signal<Tcontrol_t > ** out_ADDRESS_INSTRUCTION_ENABLE ; //[nb_instruction] |
---|
57 | sc_signal<Tinst_ifetch_ptr_t> * out_ADDRESS_INST_IFETCH_PTR ; |
---|
58 | sc_signal<Tbranch_state_t > * out_ADDRESS_BRANCH_STATE ; |
---|
59 | sc_signal<Tprediction_ptr_t > * out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ; |
---|
60 | sc_signal<Tcontrol_t > * out_PREDICT_VAL ; |
---|
61 | sc_signal<Tcontrol_t > * in_PREDICT_ACK ; |
---|
62 | sc_signal<Tgeneral_address_t> * out_PREDICT_PC_PREVIOUS ; |
---|
63 | sc_signal<Tgeneral_address_t> * out_PREDICT_PC_CURRENT ; |
---|
64 | sc_signal<Tcontrol_t > * out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
---|
65 | sc_signal<Tgeneral_address_t> * in_PREDICT_PC_NEXT ; |
---|
66 | sc_signal<Tcontrol_t > * in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
---|
67 | sc_signal<Tcontrol_t > ** in_PREDICT_INSTRUCTION_ENABLE ; //[nb_instruction] |
---|
68 | //sc_signal<Tcontrol_t > * in_PREDICT_BRANCH_IS_CURRENT ; |
---|
69 | sc_signal<Tbranch_state_t > * in_PREDICT_BRANCH_STATE ; |
---|
70 | sc_signal<Tprediction_ptr_t > * in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; |
---|
71 | sc_signal<Tinst_ifetch_ptr_t> * in_PREDICT_INST_IFETCH_PTR ; |
---|
72 | sc_signal<Tcontrol_t > * in_EVENT_VAL ; |
---|
73 | sc_signal<Tcontrol_t > * out_EVENT_ACK ; |
---|
74 | sc_signal<Tgeneral_address_t> * in_EVENT_ADDRESS ; |
---|
75 | sc_signal<Tgeneral_address_t> * in_EVENT_ADDRESS_NEXT ; |
---|
76 | sc_signal<Tcontrol_t > * in_EVENT_ADDRESS_NEXT_VAL ; |
---|
77 | sc_signal<Tcontrol_t > * in_EVENT_IS_DS_TAKE ; |
---|
78 | |
---|
79 | ALLOC0_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); |
---|
80 | ALLOC0_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); |
---|
81 | ALLOC0_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); |
---|
82 | ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
---|
83 | ALLOC0_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
---|
84 | ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); |
---|
85 | ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
---|
86 | ALLOC0_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
---|
87 | ALLOC0_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
---|
88 | ALLOC0_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); |
---|
89 | ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); |
---|
90 | ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
---|
91 | ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); |
---|
92 | ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
---|
93 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
---|
94 | ALLOC0_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
---|
95 | //ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); |
---|
96 | ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
---|
97 | ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
---|
98 | ALLOC0_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
---|
99 | ALLOC0_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
---|
100 | ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); |
---|
101 | ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t); |
---|
102 | ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); |
---|
103 | ALLOC0_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); |
---|
104 | |
---|
105 | /******************************************************** |
---|
106 | * Instanciation |
---|
107 | ********************************************************/ |
---|
108 | |
---|
109 | msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str()); |
---|
110 | |
---|
111 | (*(_Address_management->in_CLOCK)) (*(in_CLOCK)); |
---|
112 | (*(_Address_management->in_NRESET)) (*(in_NRESET)); |
---|
113 | |
---|
114 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); |
---|
115 | INSTANCE0_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); |
---|
116 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); |
---|
117 | INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
---|
118 | if (_param->_have_port_inst_ifetch_ptr) |
---|
119 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); |
---|
120 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); |
---|
121 | if (_param->_have_port_depth) |
---|
122 | INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); |
---|
123 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); |
---|
124 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); |
---|
125 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); |
---|
126 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); |
---|
127 | INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
---|
128 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); |
---|
129 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
---|
130 | INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
---|
131 | if (_param->_have_port_inst_ifetch_ptr) |
---|
132 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); |
---|
133 | //INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); |
---|
134 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); |
---|
135 | if (_param->_have_port_depth) |
---|
136 | INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
---|
137 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_VAL ); |
---|
138 | INSTANCE0_SC_SIGNAL (_Address_management,out_EVENT_ACK ); |
---|
139 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); |
---|
140 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT ); |
---|
141 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL ); |
---|
142 | INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE ); |
---|
143 | |
---|
144 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
---|
145 | |
---|
146 | Time * _time = new Time(); |
---|
147 | |
---|
148 | /******************************************************** |
---|
149 | * Simulation - Begin |
---|
150 | ********************************************************/ |
---|
151 | |
---|
152 | // Initialisation |
---|
153 | |
---|
154 | const uint32_t seed = 0; |
---|
155 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
---|
156 | |
---|
157 | srand(seed); |
---|
158 | |
---|
159 | const int32_t percent_transaction_address = 100; |
---|
160 | const int32_t percent_transaction_predict = 100; |
---|
161 | const int32_t percent_transaction_event = 0; |
---|
162 | |
---|
163 | SC_START(0); |
---|
164 | LABEL("Initialisation"); |
---|
165 | |
---|
166 | LABEL("Reset"); |
---|
167 | |
---|
168 | in_ADDRESS_ACK->write(0); |
---|
169 | out_PREDICT_VAL->write(0); |
---|
170 | in_EVENT_VAL ->write(0); |
---|
171 | |
---|
172 | in_NRESET->write(0); |
---|
173 | SC_START(5); |
---|
174 | in_NRESET->write(1); |
---|
175 | |
---|
176 | LABEL("Test Reset"); |
---|
177 | |
---|
178 | TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false); |
---|
179 | TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction |
---|
180 | TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event |
---|
181 | |
---|
182 | uint32_t jump = 7 ;// packet |
---|
183 | uint32_t nb_packet = 1; |
---|
184 | |
---|
185 | Tcontrol_t a_val = false; |
---|
186 | Tcontrol_t c_val = false; |
---|
187 | Tcontrol_t n_val = true ; |
---|
188 | Tcontrol_t nn_val = false; |
---|
189 | |
---|
190 | Tgeneral_data_t a_addr = 0x100>>2; |
---|
191 | Tgeneral_data_t c_addr = 0x100>>2; |
---|
192 | Tgeneral_data_t n_addr = 0x100>>2; |
---|
193 | Tgeneral_data_t nn_addr = 0x100>>2; |
---|
194 | |
---|
195 | Tcontrol_t a_enable [_param->_nb_instruction]; |
---|
196 | Tcontrol_t c_enable [_param->_nb_instruction]; |
---|
197 | Tcontrol_t n_enable [_param->_nb_instruction]; |
---|
198 | |
---|
199 | Tcontrol_t a_is_ds_take = 0; |
---|
200 | Tcontrol_t c_is_ds_take = 0; |
---|
201 | Tcontrol_t n_is_ds_take = 0; |
---|
202 | Tcontrol_t nn_is_ds_take = 0; |
---|
203 | |
---|
204 | n_enable [0] = 1; |
---|
205 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
---|
206 | n_enable [i] = 0; |
---|
207 | |
---|
208 | LABEL("Send Reset"); |
---|
209 | // do |
---|
210 | // { |
---|
211 | // in_EVENT_VAL ->write(1); |
---|
212 | // in_EVENT_ADDRESS ->write(n_addr); |
---|
213 | // in_EVENT_ADDRESS_NEXT ->write(nn_addr); |
---|
214 | // in_EVENT_ADDRESS_NEXT_VAL->write(0); |
---|
215 | // in_EVENT_IS_DS_TAKE ->write(0); |
---|
216 | // SC_START(1); |
---|
217 | // } while (out_EVENT_ACK->read() == false); |
---|
218 | // in_EVENT_VAL ->write(0); |
---|
219 | |
---|
220 | n_val = 1; |
---|
221 | |
---|
222 | LABEL("Loop of Test"); |
---|
223 | |
---|
224 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
---|
225 | { |
---|
226 | LABEL("Iteration %d",iteration); |
---|
227 | |
---|
228 | // PREDICT |
---|
229 | { |
---|
230 | in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); |
---|
231 | |
---|
232 | SC_START(0); |
---|
233 | |
---|
234 | Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); |
---|
235 | |
---|
236 | uint32_t begin = addr%_param->_nb_instruction; |
---|
237 | uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); |
---|
238 | Tcontrol_t take = (nb_packet%jump)==0; |
---|
239 | |
---|
240 | if (take) |
---|
241 | addr += 0x100; |
---|
242 | else |
---|
243 | addr += end-begin+1; |
---|
244 | |
---|
245 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
246 | in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); |
---|
247 | in_PREDICT_PC_NEXT ->write(addr); |
---|
248 | in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); |
---|
249 | in_PREDICT_INST_IFETCH_PTR ->write(0); |
---|
250 | // in_PREDICT_BRANCH_IS_CURRENT ->write(0); |
---|
251 | in_PREDICT_BRANCH_STATE ->write(0); |
---|
252 | in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); |
---|
253 | } |
---|
254 | |
---|
255 | // ADDRESS |
---|
256 | { |
---|
257 | in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); |
---|
258 | } |
---|
259 | |
---|
260 | in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); |
---|
261 | in_EVENT_ADDRESS ->write(0x77); |
---|
262 | in_EVENT_ADDRESS_NEXT ->write(0x171); |
---|
263 | Tcontrol_t next_val = rand()%2; |
---|
264 | in_EVENT_ADDRESS_NEXT_VAL->write(next_val); |
---|
265 | in_EVENT_IS_DS_TAKE ->write(next_val); |
---|
266 | |
---|
267 | //------------------------------------------------- |
---|
268 | SC_START(0); |
---|
269 | //------------------------------------------------- |
---|
270 | |
---|
271 | if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) |
---|
272 | { |
---|
273 | LABEL("PREDICT : Transaction accepted"); |
---|
274 | |
---|
275 | if (c_val) |
---|
276 | TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); |
---|
277 | TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); |
---|
278 | TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); |
---|
279 | |
---|
280 | nn_val = true; |
---|
281 | nn_addr = in_PREDICT_PC_NEXT ->read(); |
---|
282 | nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); |
---|
283 | |
---|
284 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
285 | n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); |
---|
286 | |
---|
287 | LABEL(" * nn_addr : %.8x",nn_addr); |
---|
288 | } |
---|
289 | |
---|
290 | if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) |
---|
291 | { |
---|
292 | LABEL("ADDRESS : Transaction accepted"); |
---|
293 | LABEL(" * address wait : %.8x",a_addr); |
---|
294 | |
---|
295 | TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr-a_addr%_param->_nb_instruction); |
---|
296 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
297 | TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]); |
---|
298 | if (_param->_have_port_inst_ifetch_ptr) |
---|
299 | TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); |
---|
300 | TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0); |
---|
301 | if (_param->_have_port_depth) |
---|
302 | TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); |
---|
303 | |
---|
304 | a_val = 0; |
---|
305 | nb_packet ++; |
---|
306 | } |
---|
307 | |
---|
308 | { |
---|
309 | string str_a_enable = ""; |
---|
310 | string str_c_enable = ""; |
---|
311 | string str_n_enable = ""; |
---|
312 | |
---|
313 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
314 | { |
---|
315 | str_a_enable += " " + toString(a_enable [i]); |
---|
316 | str_c_enable += " " + toString(c_enable [i]); |
---|
317 | str_n_enable += " " + toString(n_enable [i]); |
---|
318 | } |
---|
319 | |
---|
320 | LABEL("----[ Before ]---------------------"); |
---|
321 | LABEL(" * nb_packet : %d",nb_packet); |
---|
322 | LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); |
---|
323 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); |
---|
324 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); |
---|
325 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); |
---|
326 | LABEL("-----------------------------------"); |
---|
327 | } |
---|
328 | |
---|
329 | if (not a_val) |
---|
330 | { |
---|
331 | if (c_val and n_val and nn_val) |
---|
332 | { |
---|
333 | a_val = 1; |
---|
334 | c_val = 0; |
---|
335 | a_addr = c_addr; |
---|
336 | a_is_ds_take = c_is_ds_take; |
---|
337 | |
---|
338 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
339 | a_enable [i] = c_enable [i]; |
---|
340 | } |
---|
341 | } |
---|
342 | |
---|
343 | if (not c_val) |
---|
344 | { |
---|
345 | c_val = n_val; |
---|
346 | if (n_val) |
---|
347 | { |
---|
348 | c_addr = n_addr; |
---|
349 | c_is_ds_take = n_is_ds_take; |
---|
350 | |
---|
351 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
352 | c_enable [i] = n_enable [i]; |
---|
353 | } |
---|
354 | n_val = 0; |
---|
355 | } |
---|
356 | |
---|
357 | if (not n_val) |
---|
358 | { |
---|
359 | n_val = nn_val; |
---|
360 | if (nn_val) |
---|
361 | { |
---|
362 | n_addr = nn_addr; |
---|
363 | n_is_ds_take = nn_is_ds_take; |
---|
364 | |
---|
365 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
366 | // n_enable [i] = nn_enable [i]; |
---|
367 | } |
---|
368 | nn_val = 0; |
---|
369 | } |
---|
370 | |
---|
371 | if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) |
---|
372 | { |
---|
373 | LABEL("EVENT : Transaction accepted"); |
---|
374 | |
---|
375 | a_val = false; |
---|
376 | c_val = false; |
---|
377 | n_val = true; |
---|
378 | n_addr = in_EVENT_ADDRESS ->read(); |
---|
379 | n_is_ds_take = in_EVENT_IS_DS_TAKE ->read(); |
---|
380 | nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); |
---|
381 | nn_addr = in_EVENT_ADDRESS_NEXT ->read(); |
---|
382 | nn_is_ds_take= false; |
---|
383 | // nn_val = false; |
---|
384 | // n_is_ds_take = 0; |
---|
385 | |
---|
386 | n_enable [0] = 1; |
---|
387 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
---|
388 | n_enable [i] = 0; |
---|
389 | } |
---|
390 | |
---|
391 | |
---|
392 | { |
---|
393 | string str_a_enable = ""; |
---|
394 | string str_c_enable = ""; |
---|
395 | string str_n_enable = ""; |
---|
396 | |
---|
397 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
398 | { |
---|
399 | str_a_enable += " " + toString(a_enable [i]); |
---|
400 | str_c_enable += " " + toString(c_enable [i]); |
---|
401 | str_n_enable += " " + toString(n_enable [i]); |
---|
402 | } |
---|
403 | |
---|
404 | LABEL("----[ After ]----------------------"); |
---|
405 | LABEL(" * nb_packet : %d",nb_packet); |
---|
406 | LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); |
---|
407 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); |
---|
408 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); |
---|
409 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); |
---|
410 | LABEL("-----------------------------------"); |
---|
411 | } |
---|
412 | |
---|
413 | SC_START(1); |
---|
414 | |
---|
415 | } |
---|
416 | |
---|
417 | /******************************************************** |
---|
418 | * Simulation - End |
---|
419 | ********************************************************/ |
---|
420 | |
---|
421 | TEST_OK ("End of Simulation"); |
---|
422 | delete _time; |
---|
423 | |
---|
424 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
---|
425 | |
---|
426 | delete in_CLOCK; |
---|
427 | delete in_NRESET; |
---|
428 | |
---|
429 | delete out_ADDRESS_VAL ; |
---|
430 | delete in_ADDRESS_ACK ; |
---|
431 | delete out_ADDRESS_INSTRUCTION_ADDRESS ; |
---|
432 | delete [] out_ADDRESS_INSTRUCTION_ENABLE ; |
---|
433 | delete out_ADDRESS_INST_IFETCH_PTR ; |
---|
434 | delete out_ADDRESS_BRANCH_STATE ; |
---|
435 | delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; |
---|
436 | delete out_PREDICT_VAL ; |
---|
437 | delete in_PREDICT_ACK ; |
---|
438 | delete out_PREDICT_PC_PREVIOUS ; |
---|
439 | delete out_PREDICT_PC_CURRENT ; |
---|
440 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
---|
441 | delete in_PREDICT_PC_NEXT ; |
---|
442 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
---|
443 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
---|
444 | delete in_PREDICT_INST_IFETCH_PTR ; |
---|
445 | //delete in_PREDICT_BRANCH_IS_CURRENT ; |
---|
446 | delete in_PREDICT_BRANCH_STATE ; |
---|
447 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; |
---|
448 | delete in_EVENT_VAL ; |
---|
449 | delete out_EVENT_ACK ; |
---|
450 | delete in_EVENT_ADDRESS ; |
---|
451 | delete in_EVENT_ADDRESS_NEXT ; |
---|
452 | delete in_EVENT_ADDRESS_NEXT_VAL ; |
---|
453 | delete in_EVENT_IS_DS_TAKE ; |
---|
454 | #endif |
---|
455 | |
---|
456 | delete _Address_management; |
---|
457 | #ifdef STATISTICS |
---|
458 | delete _parameters_statistics; |
---|
459 | #endif |
---|
460 | } |
---|