[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Address_management_transition.cpp 101 2009-01-15 17:19:08Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | namespace address_management { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Address_management::transition" |
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| 22 | void Address_management::transition (void) |
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| 23 | { |
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[88] | 24 | log_begin(Address_management,FUNCTION); |
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| 25 | log_function(Address_management,FUNCTION,_name.c_str()); |
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[78] | 26 | |
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| 27 | if (PORT_READ(in_NRESET) == 0) |
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| 28 | { |
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[84] | 29 | // nothing is valid |
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[101] | 30 | reg_PC_ACCESS_VAL = 0; |
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| 31 | |
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[84] | 32 | reg_PC_CURRENT_VAL = 0; |
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[88] | 33 | |
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| 34 | reg_PC_NEXT_VAL = 1; |
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| 35 | reg_PC_NEXT = 0x100>>2; |
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[101] | 36 | reg_PC_NEXT_IS_DS_TAKE = 0; |
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| 37 | reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; |
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| 38 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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| 39 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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| 40 | reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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| 41 | reg_PC_NEXT_BRANCH_STATE = 0; |
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| 42 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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[88] | 43 | |
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[101] | 44 | |
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[84] | 45 | reg_PC_NEXT_NEXT_VAL = 0; |
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[78] | 46 | } |
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| 47 | else |
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| 48 | { |
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| 49 | // ========================================= |
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[84] | 50 | // ===== PREDICT =========================== |
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| 51 | // ========================================= |
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| 52 | if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) |
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| 53 | { |
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[101] | 54 | bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; |
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| 55 | if (branch_is_current) |
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| 56 | { |
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| 57 | if (_param->_have_port_inst_ifetch_ptr) |
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| 58 | reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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| 59 | reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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| 60 | if (_param->_have_port_depth) |
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| 61 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 62 | } |
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| 63 | else |
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| 64 | { |
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| 65 | if (_param->_have_port_inst_ifetch_ptr) |
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| 66 | reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); |
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| 67 | reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); |
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| 68 | if (_param->_have_port_depth) |
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| 69 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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| 70 | } |
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| 71 | |
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[84] | 72 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 73 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); |
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| 74 | |
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| 75 | reg_PC_NEXT_NEXT_VAL = 1; // address is valid |
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| 76 | reg_PC_NEXT_NEXT = PORT_READ(in_PREDICT_PC_NEXT ); |
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| 77 | reg_PC_NEXT_NEXT_IS_DS_TAKE = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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| 78 | |
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| 79 | #ifdef STATISTICS |
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[88] | 80 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 81 | (*_stat_nb_transaction_predict) ++; |
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[84] | 82 | #endif |
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| 83 | } |
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| 84 | |
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| 85 | // ========================================= |
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[78] | 86 | // ===== ADDRESS =========================== |
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| 87 | // ========================================= |
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| 88 | // transaction with icache |
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[101] | 89 | if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) |
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| 90 | { |
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| 91 | reg_PC_ACCESS_VAL = 0; |
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[84] | 92 | #ifdef STATISTICS |
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[88] | 93 | if (usage_is_set(_usage,USE_STATISTICS)) |
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[101] | 94 | { |
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[88] | 95 | (*_stat_nb_transaction_address) ++; |
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| 96 | |
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| 97 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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[101] | 98 | if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true) |
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[88] | 99 | (*_stat_sum_packet_size) ++; |
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| 100 | } |
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[84] | 101 | #endif |
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[101] | 102 | } |
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| 103 | |
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| 104 | // Shift register |
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[78] | 105 | |
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[101] | 106 | if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL) |
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| 107 | { |
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| 108 | reg_PC_ACCESS_VAL = 1; // new request |
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| 109 | reg_PC_CURRENT_VAL = 0; // invalid current |
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| 110 | |
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| 111 | reg_PC_ACCESS = reg_PC_CURRENT ; |
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| 112 | reg_PC_ACCESS_IS_DS_TAKE = reg_PC_CURRENT_IS_DS_TAKE ; |
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| 113 | reg_PC_ACCESS_INST_IFETCH_PTR = reg_PC_CURRENT_INST_IFETCH_PTR ; |
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| 114 | reg_PC_ACCESS_BRANCH_STATE = reg_PC_CURRENT_BRANCH_STATE ; |
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| 115 | reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID; |
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| 116 | |
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| 117 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 118 | reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i]; |
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| 119 | } |
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| 120 | |
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| 121 | if (not reg_PC_CURRENT_VAL) |
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| 122 | { |
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| 123 | bool val = reg_PC_NEXT_VAL; |
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| 124 | reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid |
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| 125 | reg_PC_NEXT_VAL = 0; // invalid next |
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[78] | 126 | |
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[101] | 127 | if (val) |
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| 128 | { |
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| 129 | reg_PC_CURRENT = reg_PC_NEXT ; |
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| 130 | reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; |
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| 131 | reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; |
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| 132 | reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; |
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| 133 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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| 134 | |
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| 135 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 136 | reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; |
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| 137 | } |
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| 138 | } |
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[78] | 139 | |
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[101] | 140 | if (not reg_PC_NEXT_VAL) |
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| 141 | { |
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| 142 | bool val = reg_PC_NEXT_NEXT_VAL; |
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| 143 | reg_PC_NEXT_VAL = val; // new PC_NEXT if PC_NEXT_NEXT is valid |
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| 144 | reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next |
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| 145 | |
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| 146 | if (val) |
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| 147 | { |
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| 148 | reg_PC_NEXT = reg_PC_NEXT_NEXT ; |
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| 149 | reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE ; |
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| 150 | // reg_PC_NEXT_INST_IFETCH_PTR = reg_PC_NEXT_NEXT_INST_IFETCH_PTR ; |
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| 151 | // reg_PC_NEXT_BRANCH_STATE = reg_PC_NEXT_NEXT_BRANCH_STATE ; |
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| 152 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID; |
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| 153 | |
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| 154 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 155 | // reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i]; |
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| 156 | } |
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| 157 | } |
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[78] | 158 | |
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| 159 | // ========================================= |
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| 160 | // ===== EVENT ============================= |
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| 161 | // ========================================= |
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| 162 | if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK) |
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| 163 | { |
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[88] | 164 | log_printf(TRACE,Address_management,FUNCTION," * EVENT : Transaction"); |
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| 165 | log_printf(TRACE,Address_management,FUNCTION," * IS_DS_TAKE : %d" ,PORT_READ(in_EVENT_IS_DS_TAKE )); |
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| 166 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS ),PORT_READ(in_EVENT_ADDRESS )<<2); |
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| 167 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT ),PORT_READ(in_EVENT_ADDRESS_NEXT )<<2); |
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| 168 | log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT_VAL : %d" ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL)); |
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[101] | 169 | |
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| 170 | reg_PC_ACCESS_VAL = 0; |
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[84] | 171 | reg_PC_CURRENT_VAL = 0; |
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| 172 | reg_PC_NEXT_VAL = 1; |
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| 173 | reg_PC_NEXT = PORT_READ(in_EVENT_ADDRESS); |
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[78] | 174 | // Event is never is ds_take : |
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| 175 | // * branch miss speculation : can't be place a branch in delay slot |
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| 176 | // * load miss speculation : the load is execute, the event_address is the next address (also the destination of branch) |
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| 177 | // * exception : goto the first instruction of exception handler (also is not in delay slot). |
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[88] | 178 | |
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| 179 | reg_PC_NEXT_IS_DS_TAKE = PORT_READ(in_EVENT_IS_DS_TAKE); |
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[84] | 180 | // reg_PC_NEXT_INST_IFETCH_PTR = 0; |
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| 181 | // reg_PC_NEXT_BRANCH_STATE = BRANCH_STATE_NONE; |
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| 182 | // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; |
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[78] | 183 | |
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[88] | 184 | reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. |
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| 185 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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| 186 | reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; |
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[78] | 187 | |
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[88] | 188 | reg_PC_NEXT_NEXT_VAL = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL); |
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| 189 | reg_PC_NEXT_NEXT = PORT_READ(in_EVENT_ADDRESS_NEXT); |
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| 190 | reg_PC_NEXT_NEXT_IS_DS_TAKE = 0;//?? |
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[84] | 191 | |
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[88] | 192 | // Note : is_ds_take = address_next_val |
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| 193 | // Because, is not ds take, can continue in sequence |
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| 194 | |
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[98] | 195 | // #ifdef DEBUG_TEST |
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| 196 | // if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) |
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| 197 | // throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); |
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| 198 | // #endif |
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[88] | 199 | |
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[84] | 200 | #ifdef STATISTICS |
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[88] | 201 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 202 | (*_stat_nb_transaction_event) ++; |
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[84] | 203 | #endif |
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[78] | 204 | } |
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| 205 | } |
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| 206 | |
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[101] | 207 | #if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE) |
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[88] | 208 | log_printf(TRACE,Address_management,FUNCTION," * Dump PC"); |
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[101] | 209 | { |
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| 210 | std::string instruction_enable; |
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| 211 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 212 | instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " "; |
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| 213 | |
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| 214 | log_printf(TRACE,Address_management,FUNCTION," * Access : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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| 215 | reg_PC_ACCESS_VAL, |
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| 216 | reg_PC_ACCESS_IS_DS_TAKE, |
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| 217 | reg_PC_ACCESS, |
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| 218 | reg_PC_ACCESS<<2, |
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| 219 | reg_PC_ACCESS_BRANCH_STATE, |
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| 220 | reg_PC_ACCESS_INST_IFETCH_PTR, |
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| 221 | reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID, |
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| 222 | instruction_enable.c_str() |
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| 223 | ); |
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| 224 | } |
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| 225 | { |
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| 226 | std::string instruction_enable; |
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| 227 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 228 | instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " "; |
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| 229 | |
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| 230 | log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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| 231 | reg_PC_CURRENT_VAL, |
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| 232 | reg_PC_CURRENT_IS_DS_TAKE, |
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| 233 | reg_PC_CURRENT, |
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| 234 | reg_PC_CURRENT<<2, |
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| 235 | reg_PC_CURRENT_BRANCH_STATE, |
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| 236 | reg_PC_CURRENT_INST_IFETCH_PTR, |
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| 237 | reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID, |
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| 238 | instruction_enable.c_str() |
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| 239 | ); |
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| 240 | } |
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| 241 | { |
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| 242 | std::string instruction_enable; |
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| 243 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 244 | instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " "; |
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| 245 | |
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| 246 | log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", |
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| 247 | reg_PC_NEXT_VAL, |
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| 248 | reg_PC_NEXT_IS_DS_TAKE, |
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| 249 | reg_PC_NEXT, |
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| 250 | reg_PC_NEXT<<2, |
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| 251 | reg_PC_NEXT_BRANCH_STATE, |
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| 252 | reg_PC_NEXT_INST_IFETCH_PTR, |
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| 253 | reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID, |
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| 254 | instruction_enable.c_str()); |
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| 255 | } |
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| 256 | log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)", |
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| 257 | reg_PC_NEXT_NEXT_VAL, |
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| 258 | reg_PC_NEXT_NEXT_IS_DS_TAKE, |
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| 259 | reg_PC_NEXT_NEXT, |
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| 260 | reg_PC_NEXT_NEXT<<2); |
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[84] | 261 | #endif |
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| 262 | |
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[78] | 263 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 264 | end_cycle (); |
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| 265 | #endif |
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[88] | 266 | |
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| 267 | log_end(Address_management,FUNCTION); |
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[78] | 268 | }; |
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| 269 | |
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| 270 | }; // end namespace address_management |
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| 271 | }; // end namespace ifetch_unit |
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| 272 | }; // end namespace front_end |
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| 273 | }; // end namespace multi_front_end |
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| 274 | }; // end namespace core |
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| 275 | |
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| 276 | }; // end namespace behavioural |
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| 277 | }; // end namespace morpheo |
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| 278 | #endif |
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