Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
r98 r101 28 28 { 29 29 // nothing is valid 30 reg_PC_ACCESS_VAL = 0; 31 30 32 reg_PC_CURRENT_VAL = 0; 31 33 32 34 reg_PC_NEXT_VAL = 1; 33 35 reg_PC_NEXT = 0x100>>2; 36 reg_PC_NEXT_IS_DS_TAKE = 0; 37 reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; 38 for (uint32_t i=1; i<_param->_nb_instruction; i++) 39 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 40 reg_PC_NEXT_INST_IFETCH_PTR = 0; 41 reg_PC_NEXT_BRANCH_STATE = 0; 42 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; 43 34 44 35 45 reg_PC_NEXT_NEXT_VAL = 0; … … 42 52 if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL) 43 53 { 54 bool branch_is_current = reg_PC_NEXT_IS_DS_TAKE; 55 if (branch_is_current) 56 { 57 if (_param->_have_port_inst_ifetch_ptr) 58 reg_PC_CURRENT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); 59 reg_PC_CURRENT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); 60 if (_param->_have_port_depth) 61 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); 62 } 63 else 64 { 65 if (_param->_have_port_inst_ifetch_ptr) 66 reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); 67 reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); 68 if (_param->_have_port_depth) 69 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); 70 } 71 44 72 for (uint32_t i=0; i<_param->_nb_instruction; i++) 45 73 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); 46 if (_param->_have_port_inst_ifetch_ptr)47 reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR );48 reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE );49 if (_param->_have_port_depth)50 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);51 74 52 75 reg_PC_NEXT_NEXT_VAL = 1; // address is valid … … 64 87 // ========================================= 65 88 // transaction with icache 66 if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL) 67 { 89 if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) 90 { 91 reg_PC_ACCESS_VAL = 0; 68 92 #ifdef STATISTICS 69 93 if (usage_is_set(_usage,USE_STATISTICS)) 70 if (reg_PC_CURRENT_VAL) 71 { 94 { 72 95 (*_stat_nb_transaction_address) ++; 73 96 74 97 for (uint32_t i=0; i<_param->_nb_instruction; i++) 75 if (reg_PC_ CURRENT_INSTRUCTION_ENABLE [i] == true)98 if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true) 76 99 (*_stat_sum_packet_size) ++; 77 100 } 78 101 #endif 79 80 81 Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL; 82 83 // next pc became current pc 84 reg_PC_CURRENT_VAL = pc_next_val; 85 86 // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next) 87 if (pc_next_val) 88 { 89 reg_PC_CURRENT = reg_PC_NEXT ; 90 reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; 91 reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; 92 reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; 93 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; 94 95 for (uint32_t i=0; i<_param->_nb_instruction; i++) 96 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; 97 98 reg_PC_NEXT_VAL = reg_PC_NEXT_NEXT_VAL ; 99 // if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next) 100 if (reg_PC_NEXT_NEXT_VAL) 101 { 102 reg_PC_NEXT = reg_PC_NEXT_NEXT ; 103 reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE; 104 } 105 106 // invalid next next pc 107 reg_PC_NEXT_NEXT_VAL = 0; 108 } 109 110 } 111 102 } 103 104 // Shift register 105 106 if (not reg_PC_ACCESS_VAL and reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL) 107 { 108 reg_PC_ACCESS_VAL = 1; // new request 109 reg_PC_CURRENT_VAL = 0; // invalid current 110 111 reg_PC_ACCESS = reg_PC_CURRENT ; 112 reg_PC_ACCESS_IS_DS_TAKE = reg_PC_CURRENT_IS_DS_TAKE ; 113 reg_PC_ACCESS_INST_IFETCH_PTR = reg_PC_CURRENT_INST_IFETCH_PTR ; 114 reg_PC_ACCESS_BRANCH_STATE = reg_PC_CURRENT_BRANCH_STATE ; 115 reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID; 116 117 for (uint32_t i=0; i<_param->_nb_instruction; i++) 118 reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i]; 119 } 120 121 if (not reg_PC_CURRENT_VAL) 122 { 123 bool val = reg_PC_NEXT_VAL; 124 reg_PC_CURRENT_VAL = val; // new PC_CURRENT if PC_NEXT is valid 125 reg_PC_NEXT_VAL = 0; // invalid next 126 127 if (val) 128 { 129 reg_PC_CURRENT = reg_PC_NEXT ; 130 reg_PC_CURRENT_IS_DS_TAKE = reg_PC_NEXT_IS_DS_TAKE ; 131 reg_PC_CURRENT_INST_IFETCH_PTR = reg_PC_NEXT_INST_IFETCH_PTR ; 132 reg_PC_CURRENT_BRANCH_STATE = reg_PC_NEXT_BRANCH_STATE ; 133 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID; 134 135 for (uint32_t i=0; i<_param->_nb_instruction; i++) 136 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i]; 137 } 138 } 139 140 if (not reg_PC_NEXT_VAL) 141 { 142 bool val = reg_PC_NEXT_NEXT_VAL; 143 reg_PC_NEXT_VAL = val; // new PC_NEXT if PC_NEXT_NEXT is valid 144 reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next 145 146 if (val) 147 { 148 reg_PC_NEXT = reg_PC_NEXT_NEXT ; 149 reg_PC_NEXT_IS_DS_TAKE = reg_PC_NEXT_NEXT_IS_DS_TAKE ; 150 // reg_PC_NEXT_INST_IFETCH_PTR = reg_PC_NEXT_NEXT_INST_IFETCH_PTR ; 151 // reg_PC_NEXT_BRANCH_STATE = reg_PC_NEXT_NEXT_BRANCH_STATE ; 152 // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID; 153 154 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 155 // reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i]; 156 } 157 } 112 158 113 159 // ========================================= … … 121 167 log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT ),PORT_READ(in_EVENT_ADDRESS_NEXT )<<2); 122 168 log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT_VAL : %d" ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL)); 169 170 reg_PC_ACCESS_VAL = 0; 123 171 reg_PC_CURRENT_VAL = 0; 124 172 reg_PC_NEXT_VAL = 1; … … 157 205 } 158 206 159 #if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)207 #if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE) 160 208 log_printf(TRACE,Address_management,FUNCTION," * Dump PC"); 161 log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL , reg_PC_CURRENT_IS_DS_TAKE , reg_PC_CURRENT , reg_PC_CURRENT <<2); 162 log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL , reg_PC_NEXT_IS_DS_TAKE , reg_PC_NEXT , reg_PC_NEXT <<2); 163 log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2); 209 { 210 std::string instruction_enable; 211 for (uint32_t i=0; i<_param->_nb_instruction; ++i) 212 instruction_enable += toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])+ " "; 213 214 log_printf(TRACE,Address_management,FUNCTION," * Access : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", 215 reg_PC_ACCESS_VAL, 216 reg_PC_ACCESS_IS_DS_TAKE, 217 reg_PC_ACCESS, 218 reg_PC_ACCESS<<2, 219 reg_PC_ACCESS_BRANCH_STATE, 220 reg_PC_ACCESS_INST_IFETCH_PTR, 221 reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID, 222 instruction_enable.c_str() 223 ); 224 } 225 { 226 std::string instruction_enable; 227 for (uint32_t i=0; i<_param->_nb_instruction; ++i) 228 instruction_enable += toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])+ " "; 229 230 log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", 231 reg_PC_CURRENT_VAL, 232 reg_PC_CURRENT_IS_DS_TAKE, 233 reg_PC_CURRENT, 234 reg_PC_CURRENT<<2, 235 reg_PC_CURRENT_BRANCH_STATE, 236 reg_PC_CURRENT_INST_IFETCH_PTR, 237 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID, 238 instruction_enable.c_str() 239 ); 240 } 241 { 242 std::string instruction_enable; 243 for (uint32_t i=0; i<_param->_nb_instruction; ++i) 244 instruction_enable += toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])+ " "; 245 246 log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s", 247 reg_PC_NEXT_VAL, 248 reg_PC_NEXT_IS_DS_TAKE, 249 reg_PC_NEXT, 250 reg_PC_NEXT<<2, 251 reg_PC_NEXT_BRANCH_STATE, 252 reg_PC_NEXT_INST_IFETCH_PTR, 253 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID, 254 instruction_enable.c_str()); 255 } 256 log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)", 257 reg_PC_NEXT_NEXT_VAL, 258 reg_PC_NEXT_NEXT_IS_DS_TAKE, 259 reg_PC_NEXT_NEXT, 260 reg_PC_NEXT_NEXT<<2); 164 261 #endif 165 262
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