1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Ifetch_unit_Glue_genMealy_icache_req.cpp 85 2008-05-14 13:09:48Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace ifetch_unit_glue { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Ifetch_unit_Glue::genMealy_icache_req" |
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22 | void Ifetch_unit_Glue::genMealy_icache_req (void) |
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23 | { |
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24 | log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin"); |
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25 | |
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26 | Tcontrol_t address_val = PORT_READ(in_ICACHE_REQ_ADDRESS_VAL); |
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27 | Tcontrol_t queue_ack = PORT_READ(in_ICACHE_REQ_QUEUE_ACK ); |
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28 | Tcontrol_t ack = PORT_READ(in_ICACHE_REQ_ACK ); |
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29 | |
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30 | PORT_WRITE(out_ICACHE_REQ_VAL , address_val and queue_ack); // have a address valid and queue have a slot empty |
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31 | PORT_WRITE(out_ICACHE_REQ_ADDRESS_ACK, ack and queue_ack); // cache can accept a new transaction and queue have a slot empty |
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32 | PORT_WRITE(out_ICACHE_REQ_QUEUE_VAL , address_val and ack); // cache can accept a new transaction and the address is valid |
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33 | |
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34 | Taddress_t address = PORT_READ(in_ICACHE_REQ_ADDRESS_ADDRESS); |
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35 | PORT_WRITE(out_ICACHE_REQ_ADDRESS ,address); |
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36 | PORT_WRITE(out_ICACHE_REQ_QUEUE_ADDRESS,address); |
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37 | |
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38 | log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End"); |
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39 | }; |
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40 | |
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41 | }; // end namespace ifetch_unit_glue |
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42 | }; // end namespace ifetch_unit |
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43 | }; // end namespace front_end |
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44 | }; // end namespace multi_front_end |
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45 | }; // end namespace core |
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46 | |
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47 | }; // end namespace behavioural |
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48 | }; // end namespace morpheo |
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49 | #endif |
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