1 | /* |
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2 | * $Id: Ifetch_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h" |
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9 | #include "Behavioural/include/Allocation.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Ifetch_unit::allocation" |
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22 | void Ifetch_unit::allocation ( |
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23 | #ifdef STATISTICS |
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24 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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25 | #else |
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26 | void |
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27 | #endif |
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28 | ) |
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29 | { |
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30 | log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); |
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31 | |
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32 | _component = new Component (_usage); |
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33 | |
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34 | Entity * entity = _component->set_entity (_name |
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35 | ,"Ifetch_unit" |
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36 | #ifdef POSITION |
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37 | ,COMBINATORY |
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38 | #endif |
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39 | ); |
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40 | |
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41 | _interfaces = entity->set_interfaces(); |
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42 | |
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43 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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44 | { |
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45 | Interface * interface = _interfaces->set_interface("" |
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46 | #ifdef POSITION |
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47 | ,IN |
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48 | ,SOUTH, |
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49 | "Generalist interface" |
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50 | #endif |
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51 | ); |
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52 | |
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53 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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54 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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55 | } |
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56 | |
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57 | // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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58 | { |
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59 | ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request.")); |
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60 | |
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61 | ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); |
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62 | ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); |
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63 | //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); |
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64 | ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); |
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65 | ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); |
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66 | ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); |
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67 | } |
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68 | |
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69 | // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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70 | { |
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71 | ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons.")); |
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72 | |
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73 | ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); |
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74 | ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); |
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75 | //ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); |
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76 | ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); |
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77 | ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); |
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78 | } |
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79 | { |
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80 | ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); |
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81 | |
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82 | ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction ); |
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83 | } |
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84 | |
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85 | // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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86 | { |
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87 | ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc.")); |
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88 | |
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89 | ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); |
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90 | ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); |
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91 | ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); |
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92 | ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); |
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93 | ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); |
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94 | ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); |
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95 | ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); |
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96 | ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); |
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97 | ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); |
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98 | ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); |
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99 | } |
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100 | { |
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101 | ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); |
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102 | |
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103 | ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); |
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104 | } |
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105 | |
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106 | // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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107 | { |
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108 | ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit.")); |
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109 | |
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110 | //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); |
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111 | ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); |
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112 | ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); |
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113 | ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); |
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114 | ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); |
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115 | ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); |
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116 | } |
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117 | { |
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118 | ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); |
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119 | |
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120 | ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); |
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121 | ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); |
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122 | ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction); |
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123 | } |
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124 | |
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125 | // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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126 | { |
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127 | ALLOC_INTERFACE("event",IN , NORTH, _("Event interface.")); |
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128 | |
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129 | ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); |
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130 | ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); |
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131 | ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); |
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132 | ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); |
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133 | ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); |
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134 | ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); |
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135 | } |
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136 | |
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137 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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138 | std::string name; |
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139 | |
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140 | { |
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141 | name = _name+"_address_management"; |
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142 | log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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143 | |
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144 | _component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management |
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145 | (name.c_str() |
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146 | #ifdef STATISTICS |
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147 | ,param_statistics |
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148 | #endif |
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149 | ,_param->_param_address_management |
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150 | ,_usage); |
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151 | |
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152 | _component->set_component (_component_address_management->_component |
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153 | #ifdef POSITION |
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154 | , 50, 50, 10, 10 |
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155 | #endif |
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156 | ); |
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157 | } |
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158 | |
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159 | { |
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160 | name = _name+"_ifetch_queue"; |
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161 | log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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162 | |
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163 | _component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue |
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164 | (name.c_str() |
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165 | #ifdef STATISTICS |
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166 | ,param_statistics |
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167 | #endif |
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168 | ,_param->_param_ifetch_queue |
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169 | ,_usage); |
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170 | |
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171 | _component->set_component (_component_ifetch_queue->_component |
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172 | #ifdef POSITION |
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173 | , 50, 50, 10, 10 |
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174 | #endif |
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175 | ); |
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176 | } |
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177 | |
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178 | { |
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179 | name = _name+"_ifetch_unit_glue"; |
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180 | log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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181 | |
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182 | _component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue |
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183 | (name.c_str() |
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184 | #ifdef STATISTICS |
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185 | ,param_statistics |
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186 | #endif |
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187 | ,_param->_param_ifetch_unit_glue |
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188 | ,_usage); |
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189 | |
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190 | _component->set_component (_component_ifetch_unit_glue->_component |
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191 | #ifdef POSITION |
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192 | , 50, 50, 10, 10 |
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193 | #endif |
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194 | ); |
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195 | } |
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196 | |
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197 | // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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198 | std::string src,dest; |
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199 | |
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200 | // =================================================================== |
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201 | // =====[ address_management ]======================================== |
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202 | // =================================================================== |
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203 | { |
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204 | src = _name+"_address_management"; |
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205 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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206 | |
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207 | { |
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208 | dest = _name; |
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209 | #ifdef POSITION |
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210 | _component->interface_map (src ,"", |
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211 | dest,""); |
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212 | #endif |
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213 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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214 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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215 | } |
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216 | |
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217 | { |
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218 | dest = _name+"_ifetch_queue"; |
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219 | |
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220 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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221 | { |
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222 | #ifdef POSITION |
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223 | _component->interface_map (src ,"address_"+toString(i), |
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224 | dest,"address_"+toString(i)); |
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225 | #endif |
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226 | COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE", |
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227 | dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE"); |
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228 | } |
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229 | |
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230 | if (_param->_have_port_inst_ifetch_ptr) |
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231 | COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" , |
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232 | dest, "in_ADDRESS_INST_IFETCH_PTR" ); |
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233 | COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" , |
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234 | dest, "in_ADDRESS_BRANCH_STATE" ); |
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235 | if (_param->_have_port_depth) |
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236 | COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", |
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237 | dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); |
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238 | |
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239 | dest = _name+"_ifetch_unit_glue"; |
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240 | |
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241 | #ifdef POSITION |
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242 | _component->interface_map (src ,"address", |
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243 | dest,"address"); |
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244 | #endif |
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245 | |
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246 | COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL" , |
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247 | dest, "in_ICACHE_REQ_ADDRESS_VAL"); |
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248 | COMPONENT_MAP(_component,src , "in_ADDRESS_ACK" , |
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249 | dest,"out_ICACHE_REQ_ADDRESS_ACK"); |
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250 | COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS", |
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251 | dest, "in_ICACHE_REQ_ADDRESS_ADDRESS"); |
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252 | } |
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253 | |
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254 | { |
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255 | dest = _name; |
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256 | |
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257 | #ifdef POSITION |
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258 | _component->interface_map (src ,"predict", |
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259 | dest,"predict"); |
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260 | #endif |
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261 | |
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262 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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263 | { |
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264 | #ifdef POSITION |
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265 | _component->interface_map (src ,"predict_"+toString(i), |
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266 | dest,"predict_"+toString(i)); |
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267 | #endif |
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268 | PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" |
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269 | ,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" ); |
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270 | } |
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271 | |
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272 | PORT_MAP(_component,src ,"out_PREDICT_VAL" |
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273 | ,dest,"out_PREDICT_VAL" ); |
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274 | PORT_MAP(_component,src , "in_PREDICT_ACK" |
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275 | ,dest, "in_PREDICT_ACK" ); |
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276 | PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS" |
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277 | ,dest,"out_PREDICT_PC_PREVIOUS" ); |
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278 | PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT" |
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279 | ,dest,"out_PREDICT_PC_CURRENT" ); |
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280 | PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" |
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281 | ,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" ); |
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282 | PORT_MAP(_component,src , "in_PREDICT_PC_NEXT" |
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283 | ,dest, "in_PREDICT_PC_NEXT" ); |
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284 | PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE" |
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285 | ,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" ); |
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286 | if (_param->_have_port_inst_ifetch_ptr) |
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287 | PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR" |
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288 | ,dest, "in_PREDICT_INST_IFETCH_PTR" ); |
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289 | PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE" |
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290 | ,dest, "in_PREDICT_BRANCH_STATE" ); |
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291 | if (_param->_have_port_depth) |
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292 | PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID" |
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293 | ,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"); |
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294 | } |
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295 | |
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296 | { |
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297 | dest = _name+"_ifetch_unit_glue"; |
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298 | |
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299 | #ifdef POSITION |
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300 | _component->interface_map (src ,"event", |
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301 | dest,"event"); |
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302 | _component->interface_map (src ,"event", |
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303 | _name,"event"); |
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304 | #endif |
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305 | |
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306 | COMPONENT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL"); |
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307 | COMPONENT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK"); |
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308 | |
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309 | |
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310 | dest = _name; |
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311 | PORT_MAP(_component,src , "in_EVENT_ADDRESS" ,dest , "in_EVENT_ADDRESS" ); |
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312 | PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" ,dest , "in_EVENT_ADDRESS_NEXT" ); |
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313 | PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" ); |
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314 | PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" ,dest , "in_EVENT_IS_DS_TAKE" ); |
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315 | } |
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316 | } |
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317 | |
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318 | // =================================================================== |
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319 | // =====[ ifetch_queue ]============================================== |
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320 | // =================================================================== |
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321 | { |
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322 | src = _name+"_ifetch_queue"; |
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323 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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324 | |
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325 | { |
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326 | dest = _name; |
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327 | #ifdef POSITION |
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328 | _component->interface_map (src ,"", |
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329 | dest,""); |
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330 | #endif |
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331 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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332 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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333 | } |
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334 | |
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335 | { |
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336 | dest = _name; |
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337 | |
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338 | #ifdef POSITION |
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339 | _component->interface_map (src ,"address", |
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340 | dest,"address"); |
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341 | #endif |
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342 | |
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343 | if (_param->_have_port_ifetch_queue_ptr) |
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344 | PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" , |
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345 | dest,"out_ICACHE_REQ_PACKET_ID" ); |
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346 | |
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347 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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348 | { |
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349 | #ifdef POSITION |
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350 | _component->interface_map (src ,"address_"+toString(i), |
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351 | dest+"_address_management","address_"+toString(i)); |
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352 | #endif |
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353 | |
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354 | //out_ADDRESS_INSTRUCTION_ENABLE - address_management |
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355 | } |
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356 | |
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357 | dest = _name+"_ifetch_unit_glue"; |
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358 | |
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359 | COMPONENT_MAP(_component,src , "in_ADDRESS_VAL" , |
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360 | dest,"out_ICACHE_REQ_QUEUE_VAL"); |
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361 | COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK" , |
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362 | dest, "in_ICACHE_REQ_QUEUE_ACK"); |
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363 | COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS", |
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364 | dest,"out_ICACHE_REQ_QUEUE_ADDRESS"); |
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365 | // in_ADDRESS_INST_IFETCH_PTR - address_management |
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366 | // in_ADDRESS_BRANCH_STATE - address_management |
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367 | // in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management |
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368 | } |
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369 | |
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370 | { |
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371 | dest = _name; |
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372 | |
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373 | #ifdef POSITION |
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374 | _component->interface_map (src ,"icache_rsp", |
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375 | dest,"icache_rsp"); |
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376 | #endif |
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377 | |
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378 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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379 | { |
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380 | #ifdef POSITION |
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381 | _component->interface_map (src ,"icache_rsp_"+toString(i), |
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382 | dest,"icache_rsp_"+toString(i)); |
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383 | #endif |
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384 | |
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385 | PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" , |
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386 | dest,"out_DECOD_"+toString(i)+"_VAL" ); |
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387 | PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" , |
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388 | dest, "in_DECOD_"+toString(i)+"_ACK" ); |
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389 | PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" , |
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390 | dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" ); |
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391 | } |
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392 | |
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393 | PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" ); |
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394 | if (_param->_have_port_inst_ifetch_ptr) |
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395 | PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" ); |
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396 | PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" ); |
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397 | if (_param->_have_port_depth) |
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398 | PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID"); |
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399 | PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" ); |
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400 | } |
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401 | |
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402 | { |
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403 | dest = _name; |
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404 | |
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405 | #ifdef POSITION |
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406 | _component->interface_map (src ,"icache_rsp", |
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407 | dest,"icache_rsp"); |
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408 | #endif |
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409 | |
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410 | PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" ); |
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411 | PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" ); |
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412 | if (_param->_have_port_ifetch_queue_ptr) |
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413 | PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID"); |
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414 | PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" ); |
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415 | |
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416 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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417 | { |
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418 | #ifdef POSITION |
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419 | _component->interface_map (src ,"icache_rsp_"+toString(i), |
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420 | dest,"icache_rsp_"+toString(i)); |
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421 | #endif |
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422 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION", |
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423 | dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION"); |
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424 | } |
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425 | } |
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426 | |
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427 | { |
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428 | dest = _name+"_ifetch_unit_glue"; |
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429 | |
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430 | #ifdef POSITION |
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431 | _component->interface_map (src ,"event_reset", |
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432 | dest,"event"); |
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433 | #endif |
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434 | |
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435 | COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL"); |
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436 | COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK"); |
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437 | } |
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438 | } |
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439 | |
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440 | // =================================================================== |
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441 | // =====[ ifetch_unit_glue ]========================================== |
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442 | // =================================================================== |
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443 | { |
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444 | src = _name+"_ifetch_unit_glue"; |
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445 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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446 | |
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447 | { |
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448 | dest = _name; |
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449 | #ifdef POSITION |
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450 | _component->interface_map (src ,"", |
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451 | dest,""); |
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452 | #endif |
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453 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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454 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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455 | } |
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456 | |
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457 | { |
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458 | dest = _name; |
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459 | |
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460 | #ifdef POSITION |
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461 | _component->interface_map (src ,"icache_req", |
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462 | dest,"icache_req"); |
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463 | #endif |
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464 | |
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465 | PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_VAL"); |
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466 | PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_ACK"); |
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467 | PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_TYPE"); |
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468 | PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS"); |
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469 | |
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470 | // in_ICACHE_REQ_ADDRESS_VAL - address_management |
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471 | //out_ICACHE_REQ_QUEUE_VAL - ifetch_queue |
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472 | //out_ICACHE_REQ_ADDRESS_ACK - address_management |
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473 | // in_ICACHE_REQ_QUEUE_ACK - ifetch_queue |
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474 | // in_ICACHE_REQ_ADDRESS_ADDRESS - address_management |
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475 | //out_ICACHE_REQ_QUEUE_ADDRESS - ifetch_queue |
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476 | |
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477 | } |
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478 | |
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479 | { |
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480 | dest = _name; |
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481 | |
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482 | #ifdef POSITION |
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483 | _component->interface_map (src ,"event", |
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484 | dest,"event"); |
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485 | #endif |
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486 | |
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487 | PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" ); |
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488 | PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" ); |
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489 | |
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490 | //out_EVENT_ADDRESS_VAL - address_management |
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491 | //out_EVENT_QUEUE_VAL - ifetch_queue |
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492 | // in_EVENT_ADDRESS_ACK - address_management |
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493 | // in_EVENT_QUEUE_ACK - ifetch_queue |
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494 | } |
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495 | } |
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496 | |
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497 | // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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498 | #if DEBUG_Ifetch_unit == true |
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499 | _component->test_map(); |
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500 | #endif |
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501 | |
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502 | #ifdef POSITION |
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503 | if (usage_is_set(_usage,USE_POSITION)) |
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504 | _component->generate_file(); |
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505 | #endif |
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506 | |
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507 | log_printf(FUNC,Ifetch_unit,FUNCTION,"End"); |
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508 | }; |
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509 | |
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510 | }; // end namespace ifetch_unit |
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511 | }; // end namespace front_end |
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512 | }; // end namespace multi_front_end |
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513 | }; // end namespace core |
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514 | |
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515 | }; // end namespace behavioural |
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516 | }; // end namespace morpheo |
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