[81] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace prediction_unit_glue { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Prediction_unit_Glue::genMealy_predict" |
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| 22 | void Prediction_unit_Glue::genMealy_predict (void) |
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| 23 | { |
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[88] | 24 | log_begin(Prediction_unit_Glue,FUNCTION); |
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| 25 | log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); |
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[98] | 26 | |
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| 27 | if (PORT_READ(in_NRESET)) |
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| 28 | { |
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| 29 | // Init |
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[81] | 30 | Tcontrol_t ack [_param->_nb_context]; |
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| 31 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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[98] | 32 | ack [i] = 0; |
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[82] | 33 | |
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| 34 | for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) |
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| 35 | { |
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[88] | 36 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); |
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[100] | 37 | |
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| 38 | // No access |
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[98] | 39 | Tcontrol_t btb_val = false; |
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| 40 | Tcontrol_t dir_val = false; |
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| 41 | Tcontrol_t ras_val = false; |
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| 42 | Tcontrol_t upt_val = false; |
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[81] | 43 | |
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[100] | 44 | // Get ack |
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[98] | 45 | Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); |
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| 46 | Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); |
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| 47 | Tcontrol_t ras_ack = PORT_READ(in_PREDICT_RAS_ACK [i]); |
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| 48 | Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); |
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| 49 | |
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[100] | 50 | // Read context_id |
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[98] | 51 | Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority |
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[88] | 52 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); |
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[81] | 53 | |
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[100] | 54 | // Now : ack transaction |
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[88] | 55 | ack [context] = 1; |
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[98] | 56 | |
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[88] | 57 | if (PORT_READ(in_PREDICT_VAL[context]) == 0) |
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| 58 | { |
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[100] | 59 | // Nothing |
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[88] | 60 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); |
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[81] | 61 | |
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[98] | 62 | // btb_val = false; |
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| 63 | // dir_val = false; |
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| 64 | // ras_val = false; |
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| 65 | // upt_val = false; |
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[88] | 66 | } |
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| 67 | else |
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| 68 | { |
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[100] | 69 | // Have transaction |
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[88] | 70 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); |
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[81] | 71 | |
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[100] | 72 | // Read information (PC) |
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[88] | 73 | Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); |
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| 74 | Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); |
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| 75 | Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); |
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[81] | 76 | |
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[100] | 77 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x (0x%.8x)",pc_previous,pc_previous<<2); |
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| 78 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x (0x%.8x)",pc_current ,pc_current <<2); |
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[98] | 79 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); |
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| 80 | |
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[88] | 81 | Taddress_t pc_next ; |
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| 82 | Tcontrol_t pc_next_is_ds_take ; |
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| 83 | Tbranch_state_t branch_state ; |
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| 84 | // Tprediction_ptr_t branch_update_prediction_id ; |
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| 85 | Tinst_ifetch_ptr_t inst_ifetch_ptr ; |
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| 86 | |
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| 87 | // STEP (1) - Compute the address source |
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[100] | 88 | // -> if pc_current is a ds take, then pc_previous is a branchement |
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| 89 | // get branchement address to send at the BTB |
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[88] | 90 | Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; |
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[100] | 91 | // Address_lsb = position in fetch packet |
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[88] | 92 | Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 |
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| 93 | Taddress_t address_msb; |
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[81] | 94 | |
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[100] | 95 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x (0x%.8x)",address,address<<2); |
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[98] | 96 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); |
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[81] | 97 | |
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[88] | 98 | // STEP (2) - Test if branch (access at branch_target_buffer) |
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[100] | 99 | // Access at the btb |
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[88] | 100 | btb_val = true; |
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[81] | 101 | |
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[100] | 102 | // Create the request |
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[88] | 103 | if (_param->_have_port_context_id) |
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| 104 | PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); |
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| 105 | PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); |
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[81] | 106 | |
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[100] | 107 | // Transaction can be ack if btb is not busy |
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[98] | 108 | ack [context] &= btb_ack; |
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| 109 | |
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| 110 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); |
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| 111 | |
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[100] | 112 | // BTB_ack = 0 ? else can continue |
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[98] | 113 | if (not btb_ack) |
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| 114 | continue; |
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| 115 | |
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[100] | 116 | // Test a special case : |
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| 117 | // if pc_current is a delay slot, then pc_previous is a branchement instruction, also hit must be set. |
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| 118 | // else : an another branch instruction have eject this branch : can't accurate |
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[88] | 119 | Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); |
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| 120 | Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); |
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[81] | 121 | |
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[98] | 122 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit : %d" ,hit); |
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| 123 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); |
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| 124 | |
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[100] | 125 | // STEP (3) : Test if BTB find a branch instruction in the packet |
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[88] | 126 | if (hit == 1) |
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| 127 | { |
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[100] | 128 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB hit : no sequential order"); |
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| 129 | |
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[88] | 130 | // STEP (3a) : branch - test condition |
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| 131 | bool use_dir = false; |
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| 132 | bool use_ras = false; |
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| 133 | bool use_upt = false; |
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[81] | 134 | |
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[100] | 135 | Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); |
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| 136 | Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; |
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[98] | 137 | |
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[100] | 138 | inst_ifetch_ptr = address_src_lsb; |
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| 139 | |
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| 140 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src,address_src<<2); |
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| 141 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); |
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| 142 | |
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| 143 | // Special case : |
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| 144 | // * BTB hit and the branchement is the PC current and it's the last slot. |
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| 145 | // -> next pc must be the delay slot |
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| 146 | if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alors pc_next is the destination of branchement |
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| 147 | (address_src_lsb == (_param->_nb_instruction [context]-1))) |
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[88] | 148 | { |
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[100] | 149 | // branch is in the last slot of the packet |
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| 150 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); |
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| 151 | |
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| 152 | // Branch is the last slot : next paquet is the delay slot |
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[101] | 153 | pc_next = address_src+1; // sequential |
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[100] | 154 | pc_next_is_ds_take = 1; |
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| 155 | address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) |
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| 156 | branch_state = BRANCH_STATE_NONE; |
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| 157 | } |
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| 158 | else |
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| 159 | { |
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| 160 | Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); |
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| 161 | Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); |
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| 162 | Tcontrol_t push ; |
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| 163 | Tcontrol_t direction; |
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| 164 | |
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| 165 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); |
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| 166 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src ,address_src <<2); |
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| 167 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x (0x%.8x)",address_dest,address_dest<<2); |
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| 168 | |
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| 169 | switch (condition) |
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| 170 | { |
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| 171 | case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j |
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[88] | 172 | { |
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[100] | 173 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); |
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| 174 | |
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| 175 | // use none unit (dir, upt and ras) |
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| 176 | direction = true; |
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| 177 | pc_next = address_dest; |
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| 178 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 179 | break; |
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| 180 | } |
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| 181 | case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal |
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| 182 | { |
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| 183 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITH_WRITE_STACK"); |
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| 184 | |
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| 185 | use_upt = true; |
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| 186 | use_ras = true; |
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| 187 | push = true; |
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| 188 | direction = true; |
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| 189 | pc_next = address_dest; |
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| 190 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 191 | break; |
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| 192 | } |
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| 193 | case BRANCH_CONDITION_FLAG_UNSET : // l.bnf |
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| 194 | case BRANCH_CONDITION_FLAG_SET : // l.bf |
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| 195 | { |
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| 196 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_FLAG"); |
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| 197 | |
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| 198 | use_upt = true; |
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| 199 | use_dir = true; |
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| 200 | // Test direction |
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| 201 | direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same |
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| 202 | if (direction = 1) |
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| 203 | { |
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| 204 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 205 | pc_next = address_dest; |
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| 206 | } |
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| 207 | else |
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| 208 | { |
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| 209 | branch_state = BRANCH_STATE_SPEC_NTAKE; |
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| 210 | pc_next = address_src+2; // +1 = delay slot |
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| 211 | } |
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| 212 | break; |
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| 213 | } |
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| 214 | case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) |
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| 215 | { |
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| 216 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK"); |
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| 217 | |
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| 218 | use_upt = true; |
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| 219 | use_ras = true; |
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| 220 | push = true; |
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| 221 | direction = true; |
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| 222 | pc_next = address_dest; |
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[88] | 223 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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[100] | 224 | break; |
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| 225 | } |
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| 226 | case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr |
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| 227 | { |
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| 228 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK"); |
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| 229 | |
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| 230 | use_upt = true; |
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| 231 | use_ras = true; |
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| 232 | push = true; |
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| 233 | direction = true; |
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[88] | 234 | pc_next = address_dest; |
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[100] | 235 | branch_state = BRANCH_STATE_NSPEC_TAKE; |
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| 236 | break; |
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[88] | 237 | } |
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[100] | 238 | case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) |
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[88] | 239 | { |
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[100] | 240 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_STACK"); |
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| 241 | use_upt = true; |
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| 242 | use_ras = true; |
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| 243 | push = false; |
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| 244 | direction = true; |
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| 245 | pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); |
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| 246 | branch_state = BRANCH_STATE_SPEC_TAKE; |
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| 247 | break; |
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[88] | 248 | } |
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[100] | 249 | default : |
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| 250 | { |
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| 251 | ERRORMORPHEO(FUNCTION,"Unknow Condition"); |
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| 252 | break; |
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| 253 | } |
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| 254 | } |
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| 255 | |
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| 256 | if (use_dir) |
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| 257 | { |
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| 258 | ack[context] &= dir_ack; |
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| 259 | PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); |
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| 260 | PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take |
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| 261 | // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); |
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| 262 | } |
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| 263 | |
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| 264 | if (use_ras) |
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| 265 | { |
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| 266 | ack[context] &= ras_ack; |
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| 267 | if (_param->_have_port_context_id) |
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| 268 | PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); |
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| 269 | PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); |
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| 270 | PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); |
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| 271 | |
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| 272 | is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate |
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| 273 | } |
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| 274 | |
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| 275 | if (use_upt) |
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| 276 | { |
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| 277 | ack[context] &= upt_ack; |
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| 278 | |
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| 279 | if (_param->_have_port_context_id) |
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| 280 | PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); |
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| 281 | PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); |
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| 282 | PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); |
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| 283 | PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); |
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| 284 | PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); |
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| 285 | PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); |
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| 286 | // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); |
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| 287 | PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); |
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| 288 | // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); |
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| 289 | } |
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| 290 | |
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| 291 | // ack = 1 if : |
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| 292 | // * btb_ack |
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| 293 | // * use_dir and dir_ack |
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| 294 | // * use_ras and ras_ack |
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| 295 | // * use_upt and upt_ack |
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| 296 | // ack [context] = (btb_ack and |
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| 297 | // (use_dir and dir_ack) and |
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| 298 | // (use_ras and ras_ack) and |
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| 299 | // (use_upt and upt_ack)); |
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[81] | 300 | |
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[100] | 301 | dir_val = (btb_ack and |
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| 302 | use_dir and |
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| 303 | // use_ras and |
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| 304 | // use_upt and |
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| 305 | // (not use_dir or (use_dir and dir_ack)) and |
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| 306 | (not use_ras or (use_ras and ras_ack)) and |
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| 307 | (not use_upt or (use_upt and upt_ack))); |
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[88] | 308 | |
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[100] | 309 | ras_val = (btb_ack and |
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| 310 | // use_dir and |
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| 311 | use_ras and |
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| 312 | // use_upt and |
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| 313 | (not use_dir or (use_dir and dir_ack)) and |
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| 314 | // (not use_ras or (use_ras and ras_ack)) and |
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| 315 | (not use_upt or (use_upt and upt_ack))); |
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| 316 | |
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| 317 | upt_val = (btb_ack and |
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| 318 | // use_dir and |
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| 319 | // use_ras and |
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| 320 | use_upt and |
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| 321 | (not use_dir or (use_dir and dir_ack)) and |
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| 322 | (not use_ras or (use_ras and ras_ack))// and |
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| 323 | // (not use_upt or (use_upt and upt_ack)) |
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| 324 | ); |
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| 325 | |
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| 326 | // pc_next - is previously computed |
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| 327 | // branch_state - is previously computed |
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[81] | 328 | |
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| 329 | |
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[88] | 330 | // branch is in the last slot of the packet |
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| 331 | address_msb = (address_src_lsb+2); // +1 == delayed slot |
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| 332 | pc_next_is_ds_take = 0; |
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| 333 | } |
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[81] | 334 | |
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[88] | 335 | // branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0; |
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| 336 | } |
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| 337 | else |
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| 338 | { |
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| 339 | // STEP (3b) : Sequential order : compute next paquet |
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| 340 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); |
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[81] | 341 | |
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[100] | 342 | // Take the address packet base and add new packet |
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[101] | 343 | pc_next = pc_current-address_lsb+_param->_nb_instruction [context]; // sequential |
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[88] | 344 | pc_next_is_ds_take = 0; // no branch, also no delay slot |
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| 345 | inst_ifetch_ptr = 0; |
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| 346 | branch_state = BRANCH_STATE_NONE; |
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| 347 | // branch_update_prediction_id = 0; |
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[81] | 348 | |
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[88] | 349 | address_msb = _param->_nb_instruction [context]; |
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| 350 | } |
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[82] | 351 | |
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[100] | 352 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); |
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| 353 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next : 0x%.8x (0x%.8x)",pc_next,pc_next<<2); |
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| 354 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next_is_ds_take : %d" ,pc_next_is_ds_take); |
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| 355 | |
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| 356 | // Write Output |
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| 357 | PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); |
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| 358 | PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); |
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[98] | 359 | |
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[100] | 360 | // Create enable mask |
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| 361 | Taddress_t address_limit_min = address_lsb; |
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| 362 | Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); |
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[82] | 363 | |
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[100] | 364 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); |
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| 365 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); |
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| 366 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); |
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| 367 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); |
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| 368 | log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); |
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| 369 | |
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| 370 | for (uint32_t j=0; j<address_limit_min; j++) |
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| 371 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid |
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| 372 | for (uint32_t j=address_limit_min; j<address_limit_max; j++) |
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| 373 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Valid packet |
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| 374 | for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) |
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| 375 | PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid |
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| 376 | |
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| 377 | if (_param->_have_port_inst_ifetch_ptr) |
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| 378 | PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); |
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| 379 | PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); |
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| 380 | if (_param->_have_port_depth) |
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| 381 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); |
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[88] | 382 | } |
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[81] | 383 | |
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[88] | 384 | // Write output |
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| 385 | PORT_WRITE(out_PREDICT_BTB_VAL [i], btb_val); |
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| 386 | PORT_WRITE(out_PREDICT_DIR_VAL [i], dir_val); |
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| 387 | PORT_WRITE(out_PREDICT_RAS_VAL [i], ras_val); |
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| 388 | PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); |
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[81] | 389 | } |
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[100] | 390 | |
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| 391 | // Write output |
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[81] | 392 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 393 | PORT_WRITE(out_PREDICT_ACK[i],ack[i]); |
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[98] | 394 | } |
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[81] | 395 | |
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[88] | 396 | log_end(Prediction_unit_Glue,FUNCTION); |
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[81] | 397 | }; |
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| 398 | |
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| 399 | }; // end namespace prediction_unit_glue |
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| 400 | }; // end namespace prediction_unit |
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| 401 | }; // end namespace front_end |
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| 402 | }; // end namespace multi_front_end |
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| 403 | }; // end namespace core |
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| 404 | |
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| 405 | }; // end namespace behavioural |
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| 406 | }; // end namespace morpheo |
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| 407 | #endif |
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