[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Return_Address_Stack_transition.cpp 107 2009-02-10 23:03:25Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace return_address_stack { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Return_Address_Stack::transition" |
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| 22 | void Return_Address_Stack::transition (void) |
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| 23 | { |
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[100] | 24 | log_begin(Return_Address_Stack,FUNCTION); |
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| 25 | log_function(Return_Address_Stack,FUNCTION,_name.c_str()); |
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[78] | 26 | |
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[81] | 27 | if (PORT_READ(in_NRESET)==0) |
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[78] | 28 | { |
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[100] | 29 | // Reset all structure |
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[78] | 30 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 31 | { |
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| 32 | reg_TOP [i] = 0; |
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[100] | 33 | // reg_BOTTOM [i] = 0; |
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[81] | 34 | reg_NB_ELT [i] = 0; |
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[78] | 35 | |
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| 36 | reg_PREDICT_TOP [i] = 0; |
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[100] | 37 | // reg_PREDICT_BOTTOM [i] = 0; |
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[81] | 38 | reg_PREDICT_NB_ELT [i] = 0; |
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[78] | 39 | } |
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| 40 | } |
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| 41 | else |
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| 42 | { |
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| 43 | // =================================================================== |
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| 44 | // =====[ PREDICT ]=================================================== |
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| 45 | // =================================================================== |
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| 46 | for (uint32_t i=0; i<_param->_nb_inst_predict; i++) |
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| 47 | if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) |
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| 48 | { |
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[100] | 49 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * PREDICT [%d] : Transaction",i); |
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| 50 | |
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| 51 | // Read information and pointer |
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[81] | 52 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; |
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| 53 | Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); |
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[100] | 54 | |
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[81] | 55 | Tptr_t top_old = reg_PREDICT_TOP [context]; |
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| 56 | Tptr_t top_new = top_old; |
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[100] | 57 | // Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; |
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| 58 | // Tptr_t bottom_new = bottom_old; |
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| 59 | Tptr_t nb_elt_old = reg_PREDICT_NB_ELT [context]; |
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| 60 | Tptr_t nb_elt_new = nb_elt_old; |
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[78] | 61 | |
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[100] | 62 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); |
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[81] | 63 | |
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[100] | 64 | // Hit : push or not empty |
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[81] | 65 | // Miss : ifetch is stall, no update |
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[100] | 66 | |
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| 67 | // Test if hit |
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[78] | 68 | if (internal_PREDICT_HIT [i]) |
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| 69 | { |
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[100] | 70 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); |
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| 71 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); |
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| 72 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); |
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| 73 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); |
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[81] | 74 | |
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[100] | 75 | // Test if push |
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[78] | 76 | if (push) |
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| 77 | { |
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[100] | 78 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); |
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| 79 | |
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[81] | 80 | // push : increase the top (circular) |
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[78] | 81 | top_new = (top_old+1)%_param->_size_queue[context]; |
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[100] | 82 | |
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| 83 | // Write new value in Queue |
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[78] | 84 | reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); |
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| 85 | |
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[81] | 86 | // Test if full |
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[100] | 87 | // -> is full, the push erase the oldest value in stack, also nb_elt is the same |
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| 88 | // -> is not full, increase nb_elt |
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| 89 | // if (nb_elt_old==_param->_size_queue[context]) |
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| 90 | // bottom_new = (bottom_old+1)%_param->_size_queue[context]; |
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| 91 | // else |
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| 92 | // nb_elt_new ++; |
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| 93 | if (nb_elt_old!=_param->_size_queue[context]) |
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| 94 | nb_elt_new ++; |
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[78] | 95 | } |
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| 96 | else |
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| 97 | { |
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| 98 | // pop |
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[100] | 99 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); |
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[78] | 100 | |
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[100] | 101 | // Test if the stack is empty |
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| 102 | if (nb_elt_old>0) |
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[81] | 103 | { |
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| 104 | top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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[100] | 105 | nb_elt_new --; |
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[81] | 106 | } |
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[100] | 107 | // no else : can't pop |
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[78] | 108 | } |
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| 109 | |
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[100] | 110 | // Write new pointer |
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| 111 | reg_PREDICT_TOP [context] = top_new; |
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| 112 | // reg_PREDICT_BOTTOM [context] = bottom_new; |
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| 113 | reg_PREDICT_NB_ELT [context] = nb_elt_new; |
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[81] | 114 | |
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[100] | 115 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); |
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| 116 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); |
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| 117 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); |
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| 118 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); |
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| 119 | } |
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| 120 | } |
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[78] | 121 | |
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[81] | 122 | // =================================================================== |
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| 123 | // =====[ DECOD ]===================================================== |
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| 124 | // =================================================================== |
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| 125 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 126 | if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) |
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| 127 | { |
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[100] | 128 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * DECOD [%d] : Transaction",i); |
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| 129 | |
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| 130 | // Read information |
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[81] | 131 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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| 132 | Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); |
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[100] | 133 | |
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| 134 | // Read pointer |
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[81] | 135 | Tptr_t top_old = reg_TOP [context]; |
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| 136 | Tptr_t top_new = top_old; |
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[100] | 137 | // Tptr_t bottom_old = reg_BOTTOM [context]; |
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| 138 | // Tptr_t bottom_new = bottom_old; |
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| 139 | Tptr_t nb_elt_old = reg_NB_ELT [context]; |
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| 140 | Tptr_t nb_elt_new = nb_elt_old; |
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[78] | 141 | |
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[100] | 142 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); |
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[78] | 143 | |
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[100] | 144 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); |
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| 145 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); |
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| 146 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); |
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| 147 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); |
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[78] | 148 | |
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[100] | 149 | // Test if push |
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| 150 | if (push) |
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| 151 | { |
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| 152 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); |
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| 153 | |
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| 154 | // push : increase the top (circular) |
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| 155 | top_new = (top_old+1)%_param->_size_queue[context]; |
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| 156 | |
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| 157 | // Write new value in Queue |
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| 158 | reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); |
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| 159 | |
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| 160 | // Test if full |
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| 161 | // -> is full, the push erase the oldest value in stack, also nb_elt is the same |
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| 162 | // -> is not full, increase nb_elt |
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| 163 | // if (nb_elt_old==_param->_size_queue[context]) |
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| 164 | // bottom_new = (bottom_old+1)%_param->_size_queue[context]; |
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| 165 | // else |
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| 166 | // nb_elt_new ++; |
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| 167 | if (nb_elt_old!=_param->_size_queue[context]) |
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| 168 | nb_elt_new ++; |
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| 169 | } |
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| 170 | else |
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| 171 | { |
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| 172 | // pop |
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| 173 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); |
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| 174 | |
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| 175 | // Test if the stack is empty |
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| 176 | if (nb_elt_old>0) |
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| 177 | { |
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| 178 | top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); |
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| 179 | nb_elt_new --; |
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| 180 | } |
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| 181 | // no else : can't pop |
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| 182 | } |
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| 183 | |
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| 184 | // Write new pointer |
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| 185 | reg_TOP [context] = top_new; |
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| 186 | // reg_BOTTOM [context] = bottom_new; |
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| 187 | reg_NB_ELT [context] = nb_elt_new; |
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| 188 | |
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| 189 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); |
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| 190 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); |
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| 191 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); |
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| 192 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); |
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| 193 | |
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[81] | 194 | // have previous miss of ifetch ? |
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| 195 | // 2 miss : |
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| 196 | // 1) miss predict : is very limited (local at context), can be update very quickly |
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| 197 | // 2) miss decod : result is in commit stage ... |
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[100] | 198 | |
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| 199 | // manage by Update_Fetch_Prediction_Table and Update_Prediction_Table |
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| 200 | // Note : |
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| 201 | // if decod miss : ifetch can have predict call and return branchement. Also, the head of decod can be false |
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| 202 | |
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| 203 | // Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); |
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| 204 | |
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| 205 | // if (miss) |
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| 206 | // { |
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| 207 | // reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; |
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| 208 | // reg_PREDICT_TOP [context] = reg_TOP [context]; |
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| 209 | // reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; |
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[81] | 210 | |
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[100] | 211 | // // Scan full assoc !!! |
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| 212 | // for (uint32_t j=0; j<_param->_size_queue [context]; j++) |
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| 213 | // // Test if this slot is tagged with "predict" : if true, tagged as miss |
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| 214 | // if (reg_stack [context][j]._predict) |
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| 215 | // { |
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| 216 | // reg_stack [context][j]._predict = false; |
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| 217 | // reg_stack [context][j]._miss = true; |
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| 218 | // } |
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| 219 | // } |
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[81] | 220 | } |
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[78] | 221 | |
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| 222 | // =================================================================== |
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| 223 | // =====[ UPDATE ]=================================================== |
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| 224 | // =================================================================== |
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| 225 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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| 226 | if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) |
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| 227 | { |
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[100] | 228 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * UPDATE [%d] : Transaction",i); |
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[81] | 229 | |
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[100] | 230 | Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; |
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| 231 | Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); |
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[78] | 232 | |
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[100] | 233 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * context_id : %d",context_id); |
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| 234 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * flush : %d",flush ); |
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| 235 | |
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| 236 | // An miss prediction on call/return = Return Address Stack is corrupted. |
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| 237 | if (flush) |
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| 238 | { |
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[107] | 239 | Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); |
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| 240 | Tptr_t value = (push)?1:0; |
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| 241 | |
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[100] | 242 | // All pointer is set at 0 |
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[107] | 243 | reg_TOP [context_id] = value; |
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[100] | 244 | // reg_BOTTOM [context_id] = 0; |
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[107] | 245 | reg_NB_ELT [context_id] = value; |
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[100] | 246 | |
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[107] | 247 | reg_PREDICT_TOP [context_id] = value; |
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[100] | 248 | // reg_PREDICT_BOTTOM [context_id] = 0; |
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[107] | 249 | reg_PREDICT_NB_ELT [context_id] = value; |
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| 250 | |
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| 251 | if (push) |
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| 252 | { |
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| 253 | // reinsert push value |
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| 254 | reg_stack [context_id][0]._address = PORT_READ(in_UPDATE_ADDRESS [i]); |
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| 255 | } |
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[100] | 256 | } |
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| 257 | else |
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| 258 | { |
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| 259 | // if miss_prediction -> restore queue |
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| 260 | // else, the prediction is correct |
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| 261 | Tcontrol_t miss_prediction = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); |
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| 262 | |
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| 263 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * miss_prediction : %d",miss_prediction); |
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| 264 | |
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| 265 | #ifdef DEBUG_TEST |
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| 266 | Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); |
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| 267 | Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); |
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| 268 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); |
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| 269 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); |
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| 270 | |
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| 271 | // if (prediction_ifetch) |
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| 272 | // { |
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| 273 | // if (index != reg_PREDICT_TOP [context_id]) |
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| 274 | // throw ERRORMORPHEO(FUNCTION,_("Index is different of predict_top")); |
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| 275 | // } |
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| 276 | // else |
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| 277 | // { |
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| 278 | // if (index != reg_TOP [context_id]) |
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| 279 | // throw ERRORMORPHEO(FUNCTION,_("Index is different of top")); |
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| 280 | // } |
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| 281 | |
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| 282 | #endif |
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| 283 | if (miss_prediction) |
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| 284 | { |
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| 285 | Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); |
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| 286 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * push : %d",push); |
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| 287 | #ifndef DEBUG_TEST |
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| 288 | Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); |
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| 289 | Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); |
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| 290 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); |
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| 291 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); |
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| 292 | #endif |
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| 293 | |
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| 294 | |
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| 295 | Tptr_t top_old = (prediction_ifetch)?reg_PREDICT_TOP [context_id]:reg_TOP [context_id]; |
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| 296 | Tptr_t top_new = top_old; |
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| 297 | |
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| 298 | // Tptr_t bottom_old = (prediction_ifetch)?reg_PREDICT_BOTTOM [context_id]:reg_BOTTOM [context_id]; |
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| 299 | // Tptr_t bottom_new = bottom_old; |
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| 300 | |
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| 301 | Tptr_t nb_elt_old = (prediction_ifetch)?reg_PREDICT_NB_ELT [context_id]:reg_NB_ELT [context_id]; |
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| 302 | Tptr_t nb_elt_new = nb_elt_old; |
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| 303 | |
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| 304 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); |
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| 305 | if (prediction_ifetch) |
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| 306 | { |
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| 307 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); |
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| 308 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); |
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| 309 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); |
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| 310 | } |
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| 311 | else |
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| 312 | { |
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| 313 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_old); |
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| 314 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_old); |
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| 315 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_old); |
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| 316 | } |
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| 317 | |
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| 318 | // if previous is push, pop the value |
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| 319 | // else is previous is pop, push the poped value |
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| 320 | if (push) |
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| 321 | { |
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| 322 | // previous is push, now must be pop |
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| 323 | |
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[107] | 324 | // Test if the stack is empty (if previous flush) |
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| 325 | if (nb_elt_old>0) |
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[100] | 326 | { |
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| 327 | top_new = (top_old==0)?(_param->_size_queue[context_id]-1):(top_old-1); |
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| 328 | nb_elt_new --; |
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| 329 | } |
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| 330 | } |
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| 331 | else |
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| 332 | { |
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| 333 | // previous is pop, now must be push |
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| 334 | Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); |
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| 335 | |
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| 336 | // push : increase the top (circular) |
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| 337 | // if (nb_elt_old==_param->_size_queue[context_id]) |
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| 338 | // bottom_new = (bottom_old+1)%_param->_size_queue[context_id]; |
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| 339 | // else |
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| 340 | // nb_elt_new ++; |
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| 341 | |
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| 342 | if (nb_elt_old!=_param->_size_queue[context_id]) |
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| 343 | nb_elt_new ++; |
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| 344 | |
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| 345 | top_new = index; |
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| 346 | |
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| 347 | reg_stack [context_id][index]._address = address; |
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| 348 | } |
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| 349 | |
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| 350 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); |
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| 351 | |
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| 352 | if (prediction_ifetch) |
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| 353 | { |
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| 354 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); |
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| 355 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); |
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| 356 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); |
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| 357 | |
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| 358 | reg_PREDICT_TOP [context_id] = top_new ; |
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| 359 | // reg_PREDICT_BOTTOM [context_id] = bottom_new; |
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| 360 | reg_PREDICT_NB_ELT [context_id] = nb_elt_new; |
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| 361 | } |
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| 362 | else |
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| 363 | { |
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| 364 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_new); |
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| 365 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_new); |
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| 366 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_new); |
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| 367 | |
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| 368 | reg_TOP [context_id] = top_new ; |
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| 369 | // reg_BOTTOM [context_id] = bottom_new; |
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| 370 | reg_NB_ELT [context_id] = nb_elt_new; |
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| 371 | } |
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| 372 | } |
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| 373 | } |
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[78] | 374 | } |
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| 375 | } |
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| 376 | |
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[100] | 377 | #if defined(DEBUG_Return_Address_Stack) and DEBUG>=DEBUG_TRACE |
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| 378 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * Dump RAS"); |
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| 379 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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| 380 | { |
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| 381 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * Return Address Stack [%d]",i); |
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| 382 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_TOP : %d",reg_TOP [i]); |
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| 383 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); |
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| 384 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); |
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| 385 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_TOP : %d",reg_PREDICT_TOP [i]); |
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| 386 | // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_BOTTOM : %d",reg_PREDICT_BOTTOM [i]); |
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| 387 | log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_NB_ELT : %d",reg_PREDICT_NB_ELT [i]); |
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| 388 | |
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| 389 | for (uint32_t j=0; j<_param->_size_queue[i]; ++j) |
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| 390 | log_printf(TRACE,Return_Address_Stack,FUNCTION," [%d] %.8x (%.8x)",j,reg_stack [i][j]._address,reg_stack [i][j]._address<<2); |
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| 391 | } |
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| 392 | #endif |
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| 393 | |
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[78] | 394 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 395 | end_cycle (); |
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| 396 | #endif |
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| 397 | |
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[100] | 398 | log_end(Return_Address_Stack,FUNCTION); |
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[78] | 399 | }; |
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| 400 | |
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| 401 | }; // end namespace return_address_stack |
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| 402 | }; // end namespace prediction_unit |
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| 403 | }; // end namespace front_end |
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| 404 | }; // end namespace multi_front_end |
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| 405 | }; // end namespace core |
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| 406 | |
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| 407 | }; // end namespace behavioural |
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| 408 | }; // end namespace morpheo |
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| 409 | #endif |
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