Changeset 81 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
- Timestamp:
- Apr 15, 2008, 8:40:01 PM (16 years ago)
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- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
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r78 r81 24 24 log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); 25 25 26 if (PORT_READ(in_NRESET) )26 if (PORT_READ(in_NRESET)==0) 27 27 { 28 28 for (uint32_t i=0; i<_param->_nb_context; i++) … … 30 30 reg_TOP [i] = 0; 31 31 reg_BOTTOM [i] = 0; 32 reg_NB_ELT [i] = 0; 32 33 33 34 reg_PREDICT_TOP [i] = 0; 34 35 reg_PREDICT_BOTTOM [i] = 0; 36 reg_PREDICT_NB_ELT [i] = 0; 35 37 36 38 for (uint32_t j=0; j<_param->_size_queue [i]; j++) 37 reg_stack[i][j]._val = false; 39 { 40 reg_stack[i][j]._val = false; 41 reg_stack[i][j]._predict = false; 42 reg_stack[i][j]._miss = false; 43 } 38 44 } 39 45 } … … 46 52 if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) 47 53 { 48 Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 49 Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); 50 Tptr_t top_old = reg_PREDICT_TOP [i]; 51 Tptr_t top_new; 52 54 log_printf(TRACE,Return_Address_Stack,FUNCTION,"PREDICT[%d] : Transaction",i); 55 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 56 Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); 57 Tptr_t top_old = reg_PREDICT_TOP [context]; 58 Tptr_t top_new = top_old; 59 Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; 60 61 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 62 63 // Hit : push or (val and not miss and not empty) 64 // Miss : ifetch is stall, no update 53 65 if (internal_PREDICT_HIT [i]) 54 66 { 67 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 68 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); 69 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); 70 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); 71 55 72 if (push) 56 73 { 57 // push 74 // push : increase the top (circular) 58 75 top_new = (top_old+1)%_param->_size_queue[context]; 59 76 60 77 reg_stack [context][top_new]._val = true; // New addr 61 reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr )78 reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr (or not)) 62 79 //reg_stack [context][top_new]._miss = ; 63 80 reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); 64 81 65 82 // the stack is full, erase the most old stack 66 if (top_new == reg_PREDICT_BOTTOM [i]) 67 reg_PREDICT_BOTTOM [i] = (reg_PREDICT_BOTTOM [i]+1)%_param->_size_queue[context]; 83 84 // Test if full 85 if (reg_PREDICT_NB_ELT[context]==_param->_size_queue[context]) 86 reg_PREDICT_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; 87 // A new data is write : the stack is not empty 88 if (reg_PREDICT_NB_ELT[context]< _param->_size_queue[context]) 89 reg_PREDICT_NB_ELT[context]++; 68 90 } 69 91 else 70 92 { 71 93 // pop 72 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1);94 // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 73 95 74 96 //reg_stack [context][top_new]._val = ; … … 78 100 79 101 // the stack is empty 80 if (top_old == reg_PREDICT_BOTTOM [i]) 81 reg_PREDICT_BOTTOM [i] = top_new; 82 102 if (reg_PREDICT_NB_ELT[context]>0) 103 { 104 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 105 reg_PREDICT_NB_ELT[context] --; 106 } 83 107 } 84 108 85 reg_PREDICT_TOP [i] = top_new; 109 reg_PREDICT_TOP [context] = top_new; 110 111 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 112 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); 113 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); 114 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); 86 115 } 87 116 } 88 117 89 // // =================================================================== 90 // // =====[ DECOD ]===================================================== 91 // // =================================================================== 92 // for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 93 // if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) 94 // { 95 // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 96 // Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); 97 // Tptr_t top_old = reg_TOP [i]; 98 // Tptr_t top_new; 99 100 // Tcontrol_t hit = PORT_READ(in_DECOD_HIT [i]); 101 // Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 102 103 // if (push) 104 // { 105 // // push 106 // top_new = (top_old+1)%_param->_size_queue[context]; 107 108 // reg_stack [context][top_new]._val = true; 109 // reg_stack [context][top_new]._predict = false; 110 // reg_stack [context][top_new]._miss = false; 111 // reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); 112 113 // // the stack is full, erase the most old stack 114 // if (top_old == reg_BOTTOM [i]) 115 // reg_BOTTOM [i] = top_new; 116 // } 117 // else 118 // { 119 // // pop 118 // =================================================================== 119 // =====[ DECOD ]===================================================== 120 // =================================================================== 121 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 122 if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) 123 { 124 log_printf(TRACE,Return_Address_Stack,FUNCTION,"DECOD[%d] : Transaction",i); 125 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 126 Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); 127 Tptr_t top_old = reg_TOP [context]; 128 Tptr_t top_new = top_old; 129 Tptr_t bottom_old = reg_BOTTOM [context]; 130 //Tcontrol_t hit = internal_DECOD_HIT [i]; 131 Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 132 133 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 134 135 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 136 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); 137 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); 138 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); 139 140 if (push) 141 { 142 // push : increase the top (circular) 143 top_new = (top_old+1)%_param->_size_queue[context]; 144 145 reg_stack [context][top_new]._val = true; // New address 146 reg_stack [context][top_new]._predict = false; // No speculative 147 reg_stack [context][top_new]._miss = false; 148 reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); 149 150 // Test if full : if true, then icrease the bottom (erase the most old stack) 151 if (reg_NB_ELT[context]==_param->_size_queue[context]) 152 reg_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; 153 // A new data is write : the stack is not empty 154 if (reg_NB_ELT[context]< _param->_size_queue[context]) 155 reg_NB_ELT[context]++; 156 } 157 else 158 { 159 // pop 120 160 // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 121 161 122 // //reg_stack [context][top_new]._val = ; 123 // //reg_stack [context][top_new]._predict = ; 124 // //reg_stack [context][top_new]._miss = ; 125 // //reg_stack [context][top_new]._address = ; 126 // } 127 128 // reg_TOP [i] = top_new; 129 130 // // have previous miss of ifetch ? 131 // // 2 miss : 132 // // 1) miss predict : is very limited (local at context), can be update very quickly 133 // // 2) miss decod : result is in commit stage ... 134 // if (miss) 135 // { 136 // reg_PREDICT_BOTTOM [i] = reg_BOTTOM [i]; 137 // reg_PREDICT_TOP [i] = reg_TOP [i]; 138 139 // for (uint32_t j=0; j<_param->_size_queue [i]; j++) 140 // if (reg_stack [context][top_new]._predict) 141 // { 142 // reg_stack [context][top_new]._predict = false; 143 // reg_stack [context][top_new]._miss = true; 144 // } 145 // } 146 // } 162 //reg_stack [context][top_new]._val = ; 163 //reg_stack [context][top_new]._predict = ; 164 //reg_stack [context][top_new]._miss = ; 165 //reg_stack [context][top_new]._address = ; 166 167 // the stack is empty 168 if (reg_NB_ELT[context]>0) 169 { 170 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 171 reg_NB_ELT[context] --; 172 } 173 } 174 175 reg_TOP [context] = top_new; 176 177 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 178 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); 179 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); 180 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); 181 182 // have previous miss of ifetch ? 183 // 2 miss : 184 // 1) miss predict : is very limited (local at context), can be update very quickly 185 // 2) miss decod : result is in commit stage ... 186 if (miss) 187 { 188 reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; 189 reg_PREDICT_TOP [context] = reg_TOP [context]; 190 reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; 191 192 // Scan full assoc !!! 193 for (uint32_t j=0; j<_param->_size_queue [i]; j++) 194 // Test if this slot is tagged with "predict" : if true, tagged as miss 195 if (reg_stack [context][j]._predict) 196 { 197 reg_stack [context][j]._predict = false; 198 reg_stack [context][j]._miss = true; 199 } 200 } 201 } 147 202 148 203 // =================================================================== … … 152 207 if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) 153 208 { 154 Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 155 Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 156 Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 209 ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); 157 210 158 if (PORT_READ(in_UPDATE_MISS_PREDICTION [i])) 159 { 160 if (push) 161 { 162 // push 163 top_new = (top_old+1)%_param->_size_queue[context]; 211 212 // Tcontrol_t miss = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); 213 // // 214 // if (miss) 215 // { 216 // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 217 // Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 218 // Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 219 // Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 220 // Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 221 222 // if (push) 223 // { 224 // // // push 225 // // top_new = (top_old+1)%_param->_size_queue[context]; 164 226 165 reg_stack [context][index]._val = true;166 reg_stack [context][index]._predict = false;167 reg_stack [context][index]._miss = false;168 reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]);169 170 }171 else172 {173 //reg_stack [context][top_new]._val = ;174 //reg_stack [context][top_new]._predict = ;175 //reg_stack [context][top_new]._miss = ;176 //reg_stack [context][top_new]._address = ;177 }178 179 // Mouais bof .......180 reg_PREDICT_TOP [i] = index;181 }227 // // reg_stack [context][index]._val = true; 228 // // reg_stack [context][index]._predict = false; 229 // // reg_stack [context][index]._miss = false; 230 // // reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); 231 232 // } 233 // else 234 // { 235 // // //reg_stack [context][top_new]._val = ; 236 // // //reg_stack [context][top_new]._predict = ; 237 // // //reg_stack [context][top_new]._miss = ; 238 // // //reg_stack [context][top_new]._address = ; 239 // } 240 241 // // // // Mouais bof ....... 242 // // // reg_PREDICT_TOP [context] = index; 243 // } 182 244 } 183 245 } -
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