[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Update_Prediction_Table_transition.cpp 94 2008-12-15 11:04:03Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace prediction_unit { |
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| 17 | namespace update_prediction_table { |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Update_Prediction_Table::transition" |
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| 21 | void Update_Prediction_Table::transition (void) |
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| 22 | { |
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[88] | 23 | log_begin(Update_Prediction_Table,FUNCTION); |
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| 24 | log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); |
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[78] | 25 | |
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[81] | 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[88] | 28 | // Initialisation |
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| 29 | |
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| 30 | reg_UPDATE_PRIORITY = 0; |
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| 31 | |
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| 32 | // All pointer is set at 0 |
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[81] | 33 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 34 | { |
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[88] | 35 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) |
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| 36 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; |
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| 37 | reg_UFPT_BOTTOM [i] = 0; |
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| 38 | reg_UFPT_TOP [i] = 0; |
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| 39 | reg_UFPT_UPDATE [i] = 0; |
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| 40 | reg_UFPT_NB_NEED_UPDATE [i] = 0; |
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| 41 | |
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| 42 | for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) |
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| 43 | reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; |
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| 44 | reg_UPT_BOTTOM [i] = 0; |
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| 45 | reg_UPT_TOP [i] = 0; |
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| 46 | reg_UPT_UPDATE [i] = 0; |
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| 47 | |
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| 48 | reg_IS_ACCURATE [i] = true; |
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[94] | 49 | |
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[88] | 50 | reg_EVENT_STATE [i] = EVENT_STATE_OK; |
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| 51 | } |
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[81] | 52 | } |
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| 53 | else |
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| 54 | { |
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[94] | 55 | bool flush_UFPT [_param->_nb_context]; |
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| 56 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 57 | flush_UFPT [i] = false; |
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| 58 | |
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[81] | 59 | // =================================================================== |
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[88] | 60 | // =====[ GARBAGE COLLECTOR ]========================================= |
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| 61 | // =================================================================== |
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| 62 | |
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| 63 | // Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot |
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| 64 | // * Update state -> new status is "empty" |
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| 65 | // * Update pointer (bottom and accurate) |
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| 66 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR"); |
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| 67 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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| 68 | { |
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| 69 | // UPDATE_FETCH_PREDICTION_TABLE |
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| 70 | { |
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| 71 | uint32_t bottom = reg_UFPT_BOTTOM [i]; |
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| 72 | |
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| 73 | // Test if state is end |
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| 74 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END) |
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| 75 | { |
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| 76 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom); |
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| 77 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom); |
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| 78 | |
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| 79 | // Free slot |
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| 80 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; |
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| 81 | // Update pointer |
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| 82 | reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i]; |
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| 83 | } |
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| 84 | } |
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| 85 | |
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| 86 | // UPDATE_PREDICTION_TABLE |
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| 87 | { |
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| 88 | uint32_t bottom = reg_UPT_BOTTOM [i]; |
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| 89 | |
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| 90 | // Test if state is end |
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| 91 | if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) |
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| 92 | { |
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| 93 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); |
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| 94 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); |
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| 95 | |
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| 96 | // Free slot |
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| 97 | reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; |
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| 98 | // Update pointer |
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| 99 | reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; |
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| 100 | } |
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| 101 | } |
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| 102 | } |
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| 103 | |
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| 104 | // =================================================================== |
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[81] | 105 | // =====[ PREDICT ]=================================================== |
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| 106 | // =================================================================== |
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[88] | 107 | |
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| 108 | // An ifetch_unit compute next cycle and have an branch : predict_val is set |
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| 109 | // * Alloc new entry -> new status is "wait decod" |
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| 110 | // * Save input (to restore in miss or error) |
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| 111 | // * Update pointer |
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| 112 | |
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[81] | 113 | for (uint32_t i=0; i<_param->_nb_inst_predict; i++) |
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| 114 | if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i]) |
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| 115 | { |
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| 116 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; |
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[88] | 117 | uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i]; |
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[81] | 118 | |
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[88] | 119 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i); |
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| 120 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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| 121 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); |
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[81] | 122 | |
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[88] | 123 | #ifdef DEBUG_TEST |
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| 124 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) |
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| 125 | throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state.")); |
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| 126 | #endif |
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[81] | 127 | |
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[88] | 128 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top); |
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| 129 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD; |
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| 130 | |
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| 131 | Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); |
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| 132 | |
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| 133 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition; |
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| 134 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); |
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| 135 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); |
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| 136 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); |
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| 137 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]); |
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| 138 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; |
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| 139 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); |
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| 140 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); |
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| 141 | |
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| 142 | reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context]; |
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| 143 | // reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; |
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| 144 | if (need_update(condition)) |
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| 145 | reg_UFPT_NB_NEED_UPDATE [context] ++; |
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[81] | 146 | } |
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| 147 | |
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| 148 | // =================================================================== |
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| 149 | // =====[ DECOD ]===================================================== |
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| 150 | // =================================================================== |
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[88] | 151 | |
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| 152 | |
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| 153 | // An decod is detected by decod stage |
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| 154 | // 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch |
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| 155 | // * Update state, wait_decod -> wait_end |
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| 156 | // * Pop ufpt -> push upt |
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| 157 | // * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod |
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| 158 | // 2) Miss : The instruction bundle have a branch but it is not predicted |
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| 159 | // * Flush ufpt |
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| 160 | // * decod information is write in upt |
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| 161 | |
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[81] | 162 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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| 163 | if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i]) |
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| 164 | { |
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[88] | 165 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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| 166 | Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]); |
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| 167 | Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]); |
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| 168 | uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i]; |
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| 169 | Tbranch_condition_t condition ; |
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| 170 | Tcontrol_t is_accurate; |
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[94] | 171 | Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); |
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| 172 | Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); |
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| 173 | Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); |
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[81] | 174 | |
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[88] | 175 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i); |
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| 176 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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| 177 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch); |
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| 178 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); |
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| 179 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); |
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[81] | 180 | |
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[88] | 181 | if (miss_ifetch or miss_decod) |
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[81] | 182 | { |
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[88] | 183 | // Have a miss !!! |
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[94] | 184 | #ifdef DEBUG_TEST |
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| 185 | if (reg_EVENT_STATE [context] != EVENT_STATE_OK) |
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| 186 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); |
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| 187 | #endif |
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| 188 | |
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[88] | 189 | if (reg_UFPT_NB_NEED_UPDATE [context] == 0) |
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| 190 | { |
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[94] | 191 | // Change state |
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| 192 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context); |
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| 193 | reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; |
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[88] | 194 | } |
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| 195 | else |
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| 196 | { |
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[94] | 197 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss - flush ufpt)",context); |
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[88] | 198 | reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT; |
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| 199 | } |
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[81] | 200 | |
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[94] | 201 | // Flush UPFT |
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| 202 | flush_UFPT [context] = true; |
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| 203 | |
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| 204 | reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State |
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| 205 | reg_EVENT_ADDRESS_DEST_VAL[context] = last_take; |
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| 206 | reg_EVENT_ADDRESS_DEST [context] = address_dest; |
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| 207 | |
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[88] | 208 | // Push upt (from decod interface) |
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| 209 | condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); |
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| 210 | is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]); |
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| 211 | |
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| 212 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; |
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[94] | 213 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ; |
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| 214 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest; |
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| 215 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ; |
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[88] | 216 | // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; |
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| 217 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; |
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| 218 | // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction |
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| 219 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); |
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| 220 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); |
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| 221 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction |
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[81] | 222 | } |
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| 223 | else |
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| 224 | { |
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| 225 | // Normal case : branch is previous predicated, change state of branch |
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[88] | 226 | uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; |
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[81] | 227 | |
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[88] | 228 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read); |
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| 229 | |
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| 230 | #ifdef DEBUG_TEST |
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| 231 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) |
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| 232 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state.")); |
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| 233 | #endif |
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| 234 | // Change state |
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| 235 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read); |
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| 236 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END; |
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| 237 | |
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| 238 | // Push upt (from Pop ufpt) |
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| 239 | condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition; |
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| 240 | is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate; |
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| 241 | |
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| 242 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; |
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| 243 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ; |
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| 244 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest; |
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| 245 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ; |
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| 246 | // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; |
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| 247 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; |
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| 248 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ; |
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| 249 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ; |
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| 250 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ; |
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| 251 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true; // prediction from ifetch |
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| 252 | |
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| 253 | // Update pointer |
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| 254 | if (need_update(condition)) |
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| 255 | { |
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| 256 | reg_UFPT_NB_NEED_UPDATE [context] --; |
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| 257 | } |
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[81] | 258 | } |
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[88] | 259 | |
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| 260 | // All case !!! |
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| 261 | |
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| 262 | #ifdef DEBUG_TEST |
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| 263 | if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY) |
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| 264 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state.")); |
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| 265 | #endif |
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| 266 | |
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| 267 | // Change state |
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| 268 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write); |
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| 269 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END; |
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| 270 | |
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| 271 | // Write new accurate |
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| 272 | #ifdef DEBUG_TEST |
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| 273 | if (not reg_IS_ACCURATE [context] and not is_accurate) |
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| 274 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag.")); |
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| 275 | #endif |
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| 276 | reg_IS_ACCURATE [context] = is_accurate; |
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| 277 | |
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| 278 | // Update pointer |
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| 279 | reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context]; |
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| 280 | // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; |
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[81] | 281 | } |
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| 282 | |
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| 283 | // =================================================================== |
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| 284 | // =====[ BRANCH_COMPLETE ]=========================================== |
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| 285 | // =================================================================== |
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[88] | 286 | |
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| 287 | // The branch is complete |
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| 288 | // * Hit prediction : |
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| 289 | // * update status |
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| 290 | // * Miss prediction : |
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[81] | 291 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 292 | if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) |
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| 293 | { |
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| 294 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
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[88] | 295 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
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[94] | 296 | Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; |
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| 297 | Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; |
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| 298 | Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; |
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[81] | 299 | |
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[88] | 300 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); |
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| 301 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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| 302 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); |
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[94] | 303 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); |
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[81] | 304 | |
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[94] | 305 | if (miss) |
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[81] | 306 | { |
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[94] | 307 | // Have a miss !!! |
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| 308 | // Flush UPFT |
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| 309 | flush_UFPT [context] = true; |
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| 310 | |
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| 311 | // Flush UPT |
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| 312 | uint32_t top = reg_UPT_TOP [context]; |
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| 313 | uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; |
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| 314 | for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; |
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| 315 | j!=top; |
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| 316 | j=(j+1)%_param->_size_upt_queue[context]) |
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| 317 | reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; |
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| 318 | |
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| 319 | // TOP is next write slot : last slot is TOP-1 |
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| 320 | reg_UPT_UPDATE [context] = new_update; |
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| 321 | |
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| 322 | // reg_UPT_BOTTOM [context]; |
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| 323 | reg_UPT_TOP [context] = depth; |
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[81] | 324 | |
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[94] | 325 | #ifdef DEBUG_TEST |
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| 326 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) |
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| 327 | throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); |
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| 328 | #endif |
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| 329 | |
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| 330 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); |
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| 331 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; |
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| 332 | |
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[88] | 333 | |
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[94] | 334 | Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; |
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[81] | 335 | |
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[94] | 336 | if (reg_UFPT_NB_NEED_UPDATE [context] > 0) |
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| 337 | { |
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| 338 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); |
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| 339 | reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT_AND_UPT; |
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| 340 | } |
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| 341 | else |
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| 342 | { |
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| 343 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_RAS (branch_complete - miss)",context); |
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| 344 | // have ras prediction ? |
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| 345 | reg_EVENT_STATE [context] = (new_update!=depth)?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; |
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| 346 | } |
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[81] | 347 | |
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[94] | 348 | reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State |
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| 349 | reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; |
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| 350 | reg_EVENT_ADDRESS_DEST [context] = good_addr; |
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[81] | 351 | } |
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| 352 | else |
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| 353 | { |
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[88] | 354 | // Hit case |
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| 355 | |
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[81] | 356 | #ifdef DEBUG_TEST |
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[88] | 357 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) |
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| 358 | throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); |
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[81] | 359 | #endif |
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[88] | 360 | |
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| 361 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); |
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| 362 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; |
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[81] | 363 | } |
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| 364 | |
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[88] | 365 | // In all case : update good_take |
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[94] | 366 | reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; |
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[88] | 367 | } |
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[81] | 368 | |
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| 369 | // =================================================================== |
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| 370 | // =====[ UPDATE ]==================================================== |
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| 371 | // =================================================================== |
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| 372 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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[88] | 373 | if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or |
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| 374 | (internal_UPDATE_VAL_WITHOUT_ACK [i])) |
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[81] | 375 | { |
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| 376 | Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; |
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| 377 | Tdepth_t depth = internal_UPDATE_DEPTH [i]; |
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[88] | 378 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); |
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| 379 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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| 380 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); |
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[81] | 381 | |
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[88] | 382 | if (internal_UPDATE_FROM_UFPT [i]) |
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| 383 | { |
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[94] | 384 | // if free a slot, also all queue is updated |
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| 385 | // Last slot ? |
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| 386 | if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) |
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| 387 | switch (reg_EVENT_STATE [context]) |
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| 388 | { |
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| 389 | case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; |
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| 390 | case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = (reg_UPT_UPDATE[context]!=reg_UPT_TOP[context])?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; break; |
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| 391 | default : break; |
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| 392 | } |
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| 393 | |
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[88] | 394 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); |
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| 395 | |
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| 396 | // Change state |
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| 397 | #ifdef DEBUG_TEST |
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| 398 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) |
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| 399 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); |
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| 400 | #endif |
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[81] | 401 | |
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[88] | 402 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); |
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[81] | 403 | |
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[88] | 404 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; |
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| 405 | |
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[94] | 406 | |
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[88] | 407 | // Update pointer |
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[94] | 408 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); |
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| 409 | reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; |
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| 410 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); |
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[88] | 411 | // Free a register that need update ? |
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| 412 | if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) |
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| 413 | reg_UFPT_NB_NEED_UPDATE [context] --; |
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| 414 | } |
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| 415 | else |
---|
| 416 | { |
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| 417 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); |
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| 418 | |
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| 419 | // Change state |
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[94] | 420 | #ifdef DEBUG_TEST |
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| 421 | if (internal_UPDATE_RAS [i]) |
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| 422 | { |
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| 423 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) |
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| 424 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); |
---|
| 425 | } |
---|
| 426 | else |
---|
| 427 | { |
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| 428 | if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and |
---|
| 429 | (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO )) |
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| 430 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); |
---|
| 431 | } |
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[88] | 432 | #endif |
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| 433 | |
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| 434 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); |
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| 435 | |
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| 436 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; |
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| 437 | |
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| 438 | // Update pointer |
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[94] | 439 | bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); |
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| 440 | |
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[88] | 441 | if (internal_UPDATE_RAS [i]) |
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[94] | 442 | { |
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| 443 | reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); |
---|
| 444 | } |
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[88] | 445 | else |
---|
[94] | 446 | { |
---|
| 447 | reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; |
---|
| 448 | } |
---|
| 449 | |
---|
| 450 | // End and event ? |
---|
| 451 | if (end_event and |
---|
| 452 | (reg_EVENT_STATE [context] != EVENT_STATE_OK)) |
---|
| 453 | { |
---|
| 454 | reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; |
---|
| 455 | } |
---|
[88] | 456 | |
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| 457 | // Free the branch with no accurate ? |
---|
| 458 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) |
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[94] | 459 | reg_IS_ACCURATE [context] = true; |
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[88] | 460 | } |
---|
[81] | 461 | } |
---|
| 462 | |
---|
| 463 | // Round robin |
---|
| 464 | reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; |
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| 465 | |
---|
[94] | 466 | // =================================================================== |
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| 467 | // =====[ BRANCH_EVENT ]============================================== |
---|
| 468 | // =================================================================== |
---|
| 469 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 470 | if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) |
---|
| 471 | { |
---|
| 472 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); |
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[82] | 473 | |
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[94] | 474 | #ifdef DEBUG_TEST |
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| 475 | if (reg_EVENT_STATE [i] != EVENT_STATE_UPDATE_CONTEXT) |
---|
| 476 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); |
---|
| 477 | #endif |
---|
[88] | 478 | |
---|
[94] | 479 | // Change state |
---|
| 480 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (branch_event)",i); |
---|
| 481 | |
---|
| 482 | reg_EVENT_STATE [i] = EVENT_STATE_OK; |
---|
| 483 | } |
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| 484 | |
---|
| 485 | // =================================================================== |
---|
| 486 | // =====[ FLUSH ]===================================================== |
---|
| 487 | // =================================================================== |
---|
| 488 | |
---|
| 489 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
| 490 | { |
---|
| 491 | if (flush_UFPT [i]) |
---|
| 492 | { |
---|
| 493 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table"); |
---|
| 494 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i); |
---|
| 495 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); |
---|
| 496 | |
---|
| 497 | // It's to accelerate miss speculation |
---|
| 498 | if (reg_UFPT_NB_NEED_UPDATE [i] == 0) |
---|
| 499 | { |
---|
| 500 | |
---|
| 501 | // No entry need prediction, flush all entry -> Reset |
---|
| 502 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) |
---|
| 503 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; |
---|
| 504 | reg_UFPT_BOTTOM [i] = 0; |
---|
| 505 | reg_UFPT_TOP [i] = 0; |
---|
| 506 | // reg_UFPT_UPDATE [i]; |
---|
| 507 | } |
---|
| 508 | else |
---|
| 509 | { |
---|
| 510 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) |
---|
| 511 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; |
---|
[88] | 512 | |
---|
[94] | 513 | // TOP is next write slot : last slot is TOP-1 |
---|
| 514 | uint32_t top = reg_UFPT_TOP [i]; |
---|
| 515 | reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; |
---|
| 516 | |
---|
| 517 | // reg_UFPT_BOTTOM [i]; |
---|
| 518 | // reg_UFPT_TOP [i]; |
---|
| 519 | } |
---|
[81] | 520 | |
---|
[94] | 521 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]); |
---|
| 522 | |
---|
| 523 | } |
---|
| 524 | } |
---|
| 525 | |
---|
| 526 | // =================================================================== |
---|
| 527 | // =====[ PRINT ]===================================================== |
---|
| 528 | // =================================================================== |
---|
| 529 | |
---|
[82] | 530 | #if (DEBUG >= DEBUG_TRACE) |
---|
[88] | 531 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table"); |
---|
| 532 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY); |
---|
[81] | 533 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
| 534 | { |
---|
[88] | 535 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); |
---|
| 536 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); |
---|
| 537 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); |
---|
[94] | 538 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); |
---|
[88] | 539 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]); |
---|
| 540 | |
---|
| 541 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); |
---|
| 542 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]); |
---|
| 543 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]); |
---|
[94] | 544 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]); |
---|
[88] | 545 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); |
---|
| 546 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) |
---|
| 547 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s", |
---|
| 548 | j, |
---|
| 549 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition, |
---|
| 550 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src, |
---|
| 551 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest, |
---|
| 552 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take, |
---|
| 553 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate, |
---|
| 554 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history, |
---|
| 555 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras, |
---|
| 556 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras, |
---|
| 557 | toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str() |
---|
| 558 | ); |
---|
| 559 | |
---|
| 560 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); |
---|
| 561 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); |
---|
| 562 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); |
---|
| 563 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); |
---|
| 564 | for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) |
---|
| 565 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s", |
---|
| 566 | j, |
---|
| 567 | reg_UPDATE_PREDICTION_TABLE [i][j]._condition, |
---|
| 568 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_src, |
---|
| 569 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest, |
---|
| 570 | reg_UPDATE_PREDICTION_TABLE [i][j]._last_take, |
---|
| 571 | reg_UPDATE_PREDICTION_TABLE [i][j]._good_take, |
---|
| 572 | reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate, |
---|
| 573 | reg_UPDATE_PREDICTION_TABLE [i][j]._history, |
---|
| 574 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras, |
---|
| 575 | reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras, |
---|
| 576 | toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str() |
---|
| 577 | ); |
---|
[81] | 578 | } |
---|
[82] | 579 | #endif |
---|
[88] | 580 | } |
---|
[81] | 581 | |
---|
| 582 | |
---|
[78] | 583 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 584 | end_cycle (); |
---|
| 585 | #endif |
---|
[88] | 586 | |
---|
| 587 | log_end(Update_Prediction_Table,FUNCTION); |
---|
[78] | 588 | }; |
---|
| 589 | |
---|
| 590 | }; // end namespace update_prediction_table |
---|
| 591 | }; // end namespace prediction_unit |
---|
| 592 | }; // end namespace front_end |
---|
| 593 | }; // end namespace multi_front_end |
---|
| 594 | }; // end namespace core |
---|
| 595 | |
---|
| 596 | }; // end namespace behavioural |
---|
| 597 | }; // end namespace morpheo |
---|
| 598 | #endif |
---|