1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Update_Prediction_Table_transition.cpp 108 2009-02-12 11:55:06Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace prediction_unit { |
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17 | namespace update_prediction_table { |
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18 | |
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19 | #undef FUNCTION |
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20 | #define FUNCTION "Update_Prediction_Table::transition" |
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21 | void Update_Prediction_Table::transition (void) |
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22 | { |
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23 | log_begin(Update_Prediction_Table,FUNCTION); |
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24 | log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); |
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25 | |
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26 | if (PORT_READ(in_NRESET) == 0) |
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27 | { |
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28 | // Initialisation |
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29 | |
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30 | reg_UPDATE_PRIORITY = 0; |
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31 | |
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32 | // All pointer is set at 0 |
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33 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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34 | { |
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35 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) |
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36 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; |
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37 | reg_UFPT_BOTTOM [i] = 0; |
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38 | reg_UFPT_TOP [i] = 0; |
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39 | reg_UFPT_UPDATE [i] = 0; |
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40 | reg_UFPT_NB_NEED_UPDATE [i] = 0; |
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41 | reg_UFPT_NB_UPDATE [i] = 0; |
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42 | |
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43 | for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) |
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44 | reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; |
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45 | reg_UPT_BOTTOM [i] = 0; |
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46 | reg_UPT_TOP [i] = 0; |
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47 | reg_UPT_TOP_EVENT [i] = 0; |
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48 | reg_UPT_UPDATE [i] = 0; |
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49 | reg_UPT_EMPTY [i] = true; |
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50 | |
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51 | reg_IS_ACCURATE [i] = true; |
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52 | |
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53 | reg_EVENT_VAL [i] = false; |
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54 | reg_EVENT_STATE [i] = EVENT_STATE_OK; |
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55 | } |
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56 | } |
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57 | else |
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58 | { |
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59 | bool flush_UFPT [_param->_nb_context]; |
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60 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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61 | { |
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62 | flush_UFPT [i] = false; |
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63 | } |
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64 | |
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65 | // =================================================================== |
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66 | // =====[ GARBAGE COLLECTOR ]========================================= |
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67 | // =================================================================== |
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68 | |
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69 | // Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot |
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70 | // * Update state -> new status is "empty" |
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71 | // * Update pointer (bottom and accurate) |
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72 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)"); |
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73 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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74 | { |
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75 | // UPDATE_FETCH_PREDICTION_TABLE |
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76 | { |
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77 | uint32_t bottom = reg_UFPT_BOTTOM [i]; |
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78 | |
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79 | // Test if state is end |
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80 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END) |
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81 | { |
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82 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom); |
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83 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom); |
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84 | |
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85 | // Free slot |
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86 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; |
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87 | // Update pointer |
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88 | reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i]; |
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89 | } |
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90 | } |
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91 | |
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92 | // UPDATE_PREDICTION_TABLE |
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93 | { |
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94 | uint32_t bottom = reg_UPT_BOTTOM [i]; |
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95 | bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END); |
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96 | // bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); |
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97 | // bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); |
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98 | // event_state_t event_state = reg_EVENT_STATE [i]; |
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99 | |
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100 | // Test if state is end |
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101 | // if (end_ok or end_ko) |
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102 | if (end) |
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103 | { |
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104 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); |
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105 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); |
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106 | // Free slot |
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107 | reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; |
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108 | |
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109 | // Update pointer |
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110 | reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; |
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111 | |
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112 | if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i]) |
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113 | reg_UPT_EMPTY [i] = true; // free a slot |
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114 | |
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115 | // if (bottom = reg_UPT_UPDATE [i]) |
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116 | // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; |
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117 | |
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118 | if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) |
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119 | { |
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120 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); |
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121 | |
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122 | reg_EVENT_VAL [i] = false; |
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123 | reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; |
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124 | reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; |
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125 | |
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126 | if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) |
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127 | reg_UPT_EMPTY [i] = false; |
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128 | |
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129 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); |
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130 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); |
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131 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); |
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132 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); |
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133 | } |
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134 | |
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135 | } |
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136 | } |
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137 | } |
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138 | |
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139 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)"); |
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140 | |
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141 | // =================================================================== |
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142 | // =====[ PREDICT ]=================================================== |
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143 | // =================================================================== |
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144 | |
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145 | // An ifetch_unit compute next cycle and have an branch : predict_val is set |
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146 | // * Alloc new entry -> new status is "wait decod" |
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147 | // * Save input (to restore in miss or error) |
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148 | // * Update pointer |
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149 | |
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150 | for (uint32_t i=0; i<_param->_nb_inst_predict; i++) |
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151 | if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i]) |
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152 | { |
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153 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; |
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154 | uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i]; |
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155 | |
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156 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i); |
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157 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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158 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); |
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159 | |
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160 | #ifdef DEBUG_TEST |
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161 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) |
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162 | throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state.")); |
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163 | #endif |
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164 | |
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165 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top); |
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166 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD; |
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167 | |
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168 | Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); |
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169 | |
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170 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition; |
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171 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); |
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172 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); |
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173 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); |
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174 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]); |
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175 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; |
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176 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); |
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177 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); |
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178 | |
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179 | reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context]; |
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180 | // reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; |
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181 | if (need_update(condition)) |
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182 | reg_UFPT_NB_NEED_UPDATE [context] ++; |
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183 | } |
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184 | |
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185 | // =================================================================== |
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186 | // =====[ DECOD ]===================================================== |
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187 | // =================================================================== |
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188 | |
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189 | |
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190 | // An decod is detected by decod stage |
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191 | // 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch |
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192 | // * Update state, wait_decod -> wait_end |
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193 | // * Pop ufpt -> push upt |
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194 | // * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod |
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195 | // 2) Miss : The instruction bundle have a branch but it is not predicted |
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196 | // * Flush ufpt |
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197 | // * decod information is write in upt |
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198 | |
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199 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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200 | if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i]) |
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201 | { |
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202 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; |
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203 | Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]); |
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204 | Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]); |
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205 | uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i]; |
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206 | Tbranch_condition_t condition ; |
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207 | Tcontrol_t is_accurate; |
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208 | Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); |
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209 | Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); |
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210 | Tcontrol_t last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); |
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211 | |
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212 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i); |
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213 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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214 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch); |
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215 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); |
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216 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); |
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217 | |
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218 | if (miss_ifetch or miss_decod) |
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219 | { |
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220 | // Have a miss !!! |
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221 | #ifdef DEBUG_TEST |
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222 | if (reg_EVENT_STATE [context] != EVENT_STATE_OK) |
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223 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); |
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224 | #endif |
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225 | if (reg_UFPT_NB_NEED_UPDATE [context] == 0) |
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226 | { |
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227 | // Change state |
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228 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context); |
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229 | reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; |
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230 | } |
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231 | else |
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232 | { |
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233 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT (decod - miss - flush ufpt)",context); |
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234 | reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; |
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235 | } |
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236 | |
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237 | // Flush UPFT |
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238 | flush_UFPT [context] = true; |
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239 | |
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240 | reg_EVENT_DEPTH [context] = upt_ptr_write; |
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241 | reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State |
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242 | reg_EVENT_ADDRESS_DEST_VAL[context] = last_take; |
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243 | reg_EVENT_ADDRESS_DEST [context] = address_dest; |
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244 | |
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245 | // Push upt (from decod interface) |
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246 | condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); |
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247 | is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]); |
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248 | |
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249 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; |
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250 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ; |
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251 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest; |
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252 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = last_take ; |
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253 | // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; |
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254 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; |
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255 | // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction |
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256 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); |
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257 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); |
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258 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction |
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259 | } |
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260 | else |
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261 | { |
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262 | // Normal case : branch is previous predicated, change state of branch |
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263 | uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; |
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264 | |
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265 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read); |
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266 | |
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267 | #ifdef DEBUG_TEST |
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268 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) |
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269 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state.")); |
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270 | #endif |
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271 | // Change state |
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272 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read); |
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273 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END; |
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274 | |
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275 | // Push upt (from Pop ufpt) |
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276 | condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition; |
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277 | is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate; |
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278 | |
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279 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; |
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280 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ; |
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281 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest; |
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282 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ; |
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283 | // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; |
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284 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; |
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285 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ; |
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286 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ; |
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287 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ; |
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288 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch |
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289 | |
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290 | // Update pointer |
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291 | if (need_update(condition)) |
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292 | { |
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293 | reg_UFPT_NB_NEED_UPDATE [context] --; |
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294 | } |
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295 | } |
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296 | |
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297 | // All case !!! |
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298 | #ifdef DEBUG_TEST |
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299 | if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY) |
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300 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state.")); |
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301 | #endif |
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302 | |
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303 | // Change state |
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304 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write); |
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305 | reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END; |
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306 | |
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307 | // Write new accurate |
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308 | #ifdef DEBUG_TEST |
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309 | if (not reg_IS_ACCURATE [context] and not is_accurate) |
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310 | throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag.")); |
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311 | #endif |
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312 | reg_IS_ACCURATE [context] = is_accurate; |
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313 | |
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314 | // Update pointer |
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315 | reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context]; |
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316 | reg_UPT_EMPTY [context] = false; |
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317 | // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; |
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318 | |
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319 | // if (miss_ifetch or miss_decod) |
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320 | // reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context]; |
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321 | } |
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322 | |
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323 | // =================================================================== |
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324 | // =====[ UPDATE ]==================================================== |
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325 | // =================================================================== |
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326 | { |
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327 | bool can_continue [_param->_nb_context]; |
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328 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
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329 | can_continue [i] = true; |
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330 | |
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331 | for (uint32_t i=0; i<_param->_nb_inst_update; i++) |
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332 | { |
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333 | Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; |
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334 | |
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335 | if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or |
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336 | (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context])) |
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337 | { |
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338 | Tdepth_t depth = internal_UPDATE_DEPTH [i]; |
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339 | |
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340 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); |
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341 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
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342 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); |
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343 | |
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344 | if (internal_UPDATE_FROM_UFPT [i]) |
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345 | { |
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346 | // if free a slot, also all queue is updated |
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347 | // Last slot ? |
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348 | // if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) |
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349 | if ((--reg_UFPT_NB_UPDATE [context])==0) |
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350 | switch (reg_EVENT_STATE [context]) |
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351 | { |
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352 | case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; |
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353 | // impossible to have an update on ufpt and reg_upt_update>reg_upt_top |
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354 | case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; |
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355 | case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; |
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356 | case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; |
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357 | default : break; |
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358 | } |
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359 | |
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360 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); |
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361 | |
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362 | // Change state |
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363 | #ifdef DEBUG_TEST |
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364 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) |
---|
365 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); |
---|
366 | #endif |
---|
367 | |
---|
368 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); |
---|
369 | |
---|
370 | reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; |
---|
371 | |
---|
372 | // Update pointer |
---|
373 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); |
---|
374 | reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; |
---|
375 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); |
---|
376 | // Free a register that need update ? |
---|
377 | if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) |
---|
378 | reg_UFPT_NB_NEED_UPDATE [context] --; |
---|
379 | } |
---|
380 | else |
---|
381 | { |
---|
382 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); |
---|
383 | |
---|
384 | // Change state |
---|
385 | #ifdef DEBUG_TEST |
---|
386 | if (internal_UPDATE_RAS [i]) |
---|
387 | { |
---|
388 | if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and |
---|
389 | (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) ) |
---|
390 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); |
---|
391 | } |
---|
392 | else |
---|
393 | { |
---|
394 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) |
---|
395 | throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); |
---|
396 | } |
---|
397 | #endif |
---|
398 | |
---|
399 | // bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or |
---|
400 | // (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT)); |
---|
401 | #ifdef STATISTICS |
---|
402 | Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; |
---|
403 | bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK); |
---|
404 | #endif |
---|
405 | bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); |
---|
406 | |
---|
407 | // Have an update, test the state to transiste to the good state |
---|
408 | if (ko) |
---|
409 | { |
---|
410 | // Ko : wait end of all instruction |
---|
411 | // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO_WAIT_END (update)",context,depth); |
---|
412 | |
---|
413 | // reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO_WAIT_END; |
---|
414 | |
---|
415 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth); |
---|
416 | |
---|
417 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; |
---|
418 | |
---|
419 | reg_EVENT_VAL [context] = true; |
---|
420 | reg_EVENT_UPT_PTR [context] = depth; |
---|
421 | |
---|
422 | #ifdef STATISTICS |
---|
423 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
424 | (*_stat_nb_branch_miss [context][condition])++; |
---|
425 | #endif |
---|
426 | } |
---|
427 | else |
---|
428 | { |
---|
429 | // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); |
---|
430 | // reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; |
---|
431 | |
---|
432 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); |
---|
433 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; |
---|
434 | |
---|
435 | #ifdef STATISTICS |
---|
436 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
437 | { |
---|
438 | if (ok) |
---|
439 | (*_stat_nb_branch_hit [context][condition]) ++; |
---|
440 | else |
---|
441 | (*_stat_nb_branch_unused [context]) ++; |
---|
442 | } |
---|
443 | #endif |
---|
444 | } |
---|
445 | |
---|
446 | // Update pointer |
---|
447 | // * if update RAS : update pointer is decreaste until it equal at top pointer |
---|
448 | if (internal_UPDATE_RAS [i]) |
---|
449 | { |
---|
450 | // if end_event, restart too bottom, else decrease pointer |
---|
451 | bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); |
---|
452 | |
---|
453 | reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); |
---|
454 | if (end_event) |
---|
455 | { |
---|
456 | // reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; |
---|
457 | |
---|
458 | if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT) |
---|
459 | { |
---|
460 | reg_EVENT_STATE [context] = EVENT_STATE_OK; |
---|
461 | } |
---|
462 | else |
---|
463 | reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; |
---|
464 | } |
---|
465 | else |
---|
466 | { |
---|
467 | reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1); |
---|
468 | } |
---|
469 | } |
---|
470 | else |
---|
471 | { |
---|
472 | // increase pointer |
---|
473 | reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; |
---|
474 | } |
---|
475 | |
---|
476 | // Free the branch with no accurate ? |
---|
477 | if ( (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko) |
---|
478 | reg_IS_ACCURATE [context] = true; |
---|
479 | } |
---|
480 | } |
---|
481 | else |
---|
482 | can_continue [context] = false; |
---|
483 | } |
---|
484 | |
---|
485 | // Round robin |
---|
486 | reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; |
---|
487 | } |
---|
488 | |
---|
489 | |
---|
490 | // =================================================================== |
---|
491 | // =====[ BRANCH_COMPLETE ]=========================================== |
---|
492 | // =================================================================== |
---|
493 | |
---|
494 | // The branch is complete |
---|
495 | // * Hit prediction : |
---|
496 | // * update status |
---|
497 | // * Miss prediction : |
---|
498 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
---|
499 | if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) |
---|
500 | { |
---|
501 | Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; |
---|
502 | Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; |
---|
503 | Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; |
---|
504 | Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; |
---|
505 | Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; |
---|
506 | |
---|
507 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); |
---|
508 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); |
---|
509 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); |
---|
510 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); |
---|
511 | |
---|
512 | if (miss) |
---|
513 | { |
---|
514 | // Have a miss !!! |
---|
515 | // Flush UPFT |
---|
516 | flush_UFPT [context] = true; |
---|
517 | |
---|
518 | // Flush UPT |
---|
519 | uint32_t top = reg_UPT_TOP [context]; |
---|
520 | uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; |
---|
521 | |
---|
522 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); |
---|
523 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); |
---|
524 | |
---|
525 | for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; |
---|
526 | j!=top; |
---|
527 | j=(j+1)%_param->_size_upt_queue[context]) |
---|
528 | reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; |
---|
529 | |
---|
530 | |
---|
531 | // reg_UPT_BOTTOM [context]; |
---|
532 | reg_UPT_TOP [context] = depth; |
---|
533 | reg_UPT_TOP_EVENT [context] = top; |
---|
534 | |
---|
535 | if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) |
---|
536 | reg_UPT_EMPTY [context] = true; |
---|
537 | |
---|
538 | #ifdef DEBUG_TEST |
---|
539 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) |
---|
540 | throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); |
---|
541 | #endif |
---|
542 | |
---|
543 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); |
---|
544 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; |
---|
545 | |
---|
546 | Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; |
---|
547 | event_state_t event_state = reg_EVENT_STATE [context]; |
---|
548 | bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or |
---|
549 | (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or |
---|
550 | (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or |
---|
551 | (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); |
---|
552 | // bool update_ras = (new_update != depth); |
---|
553 | |
---|
554 | // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); |
---|
555 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_update_ras : %d",previous_update_ras); |
---|
556 | |
---|
557 | if (reg_UFPT_NB_NEED_UPDATE [context] > 0) |
---|
558 | { |
---|
559 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); |
---|
560 | reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; |
---|
561 | } |
---|
562 | else |
---|
563 | { |
---|
564 | // if (not previous_update_ras) |
---|
565 | { |
---|
566 | // have ras prediction ? |
---|
567 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); |
---|
568 | |
---|
569 | reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; |
---|
570 | |
---|
571 | } |
---|
572 | } |
---|
573 | |
---|
574 | if (not previous_update_ras) |
---|
575 | { |
---|
576 | reg_UPT_UPDATE [context] = new_update; |
---|
577 | } |
---|
578 | // else no update |
---|
579 | |
---|
580 | reg_EVENT_DEPTH [context] = depth; |
---|
581 | reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State |
---|
582 | reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; |
---|
583 | reg_EVENT_ADDRESS_DEST [context] = good_addr; |
---|
584 | } |
---|
585 | else |
---|
586 | { |
---|
587 | // Hit case |
---|
588 | |
---|
589 | // #ifdef DEBUG_TEST |
---|
590 | // if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) |
---|
591 | // throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); |
---|
592 | // #endif |
---|
593 | |
---|
594 | if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) |
---|
595 | { |
---|
596 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); |
---|
597 | reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; |
---|
598 | } |
---|
599 | } |
---|
600 | |
---|
601 | // In all case : update good_take |
---|
602 | reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; |
---|
603 | |
---|
604 | // Write address_dest if need read register |
---|
605 | Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; |
---|
606 | |
---|
607 | if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or |
---|
608 | (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or |
---|
609 | (condition == BRANCH_CONDITION_READ_STACK ) ) |
---|
610 | reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; |
---|
611 | } |
---|
612 | |
---|
613 | // =================================================================== |
---|
614 | // =====[ BRANCH_EVENT ]============================================== |
---|
615 | // =================================================================== |
---|
616 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
617 | if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) |
---|
618 | { |
---|
619 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i); |
---|
620 | |
---|
621 | // if different : an other branch is occured |
---|
622 | if (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT) |
---|
623 | { |
---|
624 | // Change state |
---|
625 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i); |
---|
626 | |
---|
627 | reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT; |
---|
628 | } |
---|
629 | } |
---|
630 | |
---|
631 | // =================================================================== |
---|
632 | // =====[ EVENT ]===================================================== |
---|
633 | // =================================================================== |
---|
634 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
635 | if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i]) |
---|
636 | { |
---|
637 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); |
---|
638 | |
---|
639 | //---------------------------------------------------------------- |
---|
640 | // Cases |
---|
641 | //---------------------------------------------------------------- |
---|
642 | // * EVENT_TYPE_NONE - nothing |
---|
643 | // * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer |
---|
644 | // * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer |
---|
645 | // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update |
---|
646 | // * EVENT_TYPE_SPR_ACCESS - nothing |
---|
647 | // * EVENT_TYPE_MSYNC - nothing |
---|
648 | // * EVENT_TYPE_PSYNC - nothing |
---|
649 | // * EVENT_TYPE_CSYNC - nothing |
---|
650 | |
---|
651 | Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); |
---|
652 | |
---|
653 | // Test if end of miss -> all previous branch is complete |
---|
654 | // -> all next branch is finish |
---|
655 | |
---|
656 | switch (event_type) |
---|
657 | { |
---|
658 | case EVENT_TYPE_BRANCH_MISS_SPECULATION : |
---|
659 | { |
---|
660 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION"); |
---|
661 | |
---|
662 | #ifdef DEBUG_TEST |
---|
663 | if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) |
---|
664 | throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); |
---|
665 | #endif |
---|
666 | |
---|
667 | // Change state |
---|
668 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); |
---|
669 | |
---|
670 | reg_EVENT_STATE [i] = EVENT_STATE_OK; |
---|
671 | reg_IS_ACCURATE [i] = true; |
---|
672 | |
---|
673 | Tdepth_t depth = reg_EVENT_UPT_PTR [i]; |
---|
674 | |
---|
675 | if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO) |
---|
676 | { |
---|
677 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth); |
---|
678 | |
---|
679 | reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END; |
---|
680 | } |
---|
681 | |
---|
682 | #ifdef DEBUG_TEST |
---|
683 | // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) |
---|
684 | // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); |
---|
685 | // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO) |
---|
686 | // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); |
---|
687 | #endif |
---|
688 | |
---|
689 | // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); |
---|
690 | |
---|
691 | // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; |
---|
692 | |
---|
693 | break; |
---|
694 | } |
---|
695 | case EVENT_TYPE_LOAD_MISS_SPECULATION : |
---|
696 | case EVENT_TYPE_EXCEPTION : |
---|
697 | { |
---|
698 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION"); |
---|
699 | |
---|
700 | // Have a miss !!! |
---|
701 | // Flush UPFT |
---|
702 | flush_UFPT [i] = true; |
---|
703 | |
---|
704 | // Flush UPT |
---|
705 | Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; |
---|
706 | uint32_t top = reg_UPT_TOP [i]; |
---|
707 | uint32_t bottom = reg_UPT_BOTTOM [i]; |
---|
708 | uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; |
---|
709 | bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); |
---|
710 | // bool empty = reg_UPT_EMPTY [i]; |
---|
711 | |
---|
712 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); |
---|
713 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); |
---|
714 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); |
---|
715 | |
---|
716 | event_state_t event_state = reg_EVENT_STATE [i]; |
---|
717 | bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or |
---|
718 | (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or |
---|
719 | (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or |
---|
720 | (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); |
---|
721 | |
---|
722 | bool find = false; // have slot to update ??? |
---|
723 | |
---|
724 | // flush all slot after the event |
---|
725 | for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; |
---|
726 | j!=top; |
---|
727 | j=(j+1)%_param->_size_upt_queue[i]) |
---|
728 | if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and |
---|
729 | (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) |
---|
730 | { |
---|
731 | find = true; |
---|
732 | reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; |
---|
733 | } |
---|
734 | |
---|
735 | if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and |
---|
736 | (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) |
---|
737 | { |
---|
738 | find = true; |
---|
739 | reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; |
---|
740 | } |
---|
741 | |
---|
742 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); |
---|
743 | |
---|
744 | // Test if have update slot |
---|
745 | if (find) |
---|
746 | { |
---|
747 | // flush all slot after the event |
---|
748 | for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; |
---|
749 | j!=top; |
---|
750 | j=(j+1)%_param->_size_upt_queue[i]) |
---|
751 | reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; |
---|
752 | |
---|
753 | reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; |
---|
754 | |
---|
755 | // reg_UPT_BOTTOM [i]; |
---|
756 | // TODO : special case : event is an exception on branch, also depth is not valid |
---|
757 | reg_UPT_TOP [i] = depth; // depth is again valid |
---|
758 | reg_UPT_TOP_EVENT [i] = top; |
---|
759 | |
---|
760 | if (bottom == reg_UPT_TOP [i]) |
---|
761 | reg_UPT_EMPTY [i] = true; |
---|
762 | } |
---|
763 | |
---|
764 | bool update_ras = find and ((top != depth) or full); |
---|
765 | |
---|
766 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); |
---|
767 | |
---|
768 | if (not previous_update_ras and update_ras) |
---|
769 | reg_UPT_UPDATE [i] = new_update; |
---|
770 | |
---|
771 | // new state : |
---|
772 | // * test if ufpt is empty |
---|
773 | // * ok : flush upft and upt |
---|
774 | // * ko : test if have previous flush upt |
---|
775 | // * ok : nothing |
---|
776 | // * ko : flush upt |
---|
777 | reg_EVENT_VAL [i] = true; |
---|
778 | reg_EVENT_UPT_PTR [i] = depth; |
---|
779 | |
---|
780 | if (reg_UFPT_NB_NEED_UPDATE [i] > 0) |
---|
781 | { |
---|
782 | if (update_ras) |
---|
783 | { |
---|
784 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i); |
---|
785 | reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; |
---|
786 | } |
---|
787 | else |
---|
788 | { |
---|
789 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); |
---|
790 | reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; |
---|
791 | } |
---|
792 | } |
---|
793 | else |
---|
794 | { |
---|
795 | // if (not previous_update_ras) |
---|
796 | if (update_ras) |
---|
797 | { |
---|
798 | // have ras prediction ? |
---|
799 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i); |
---|
800 | |
---|
801 | reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; |
---|
802 | } |
---|
803 | else |
---|
804 | { |
---|
805 | // special case : nothing |
---|
806 | reg_EVENT_VAL [i] = false; |
---|
807 | |
---|
808 | reg_EVENT_STATE [i] = EVENT_STATE_OK; |
---|
809 | } |
---|
810 | } |
---|
811 | |
---|
812 | // else no update |
---|
813 | |
---|
814 | reg_EVENT_DEPTH [i] = depth; |
---|
815 | // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State |
---|
816 | // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; |
---|
817 | // reg_EVENT_ADDRESS_DEST [i] = good_addr; |
---|
818 | |
---|
819 | break; |
---|
820 | } |
---|
821 | default : |
---|
822 | { |
---|
823 | // nothing |
---|
824 | break; |
---|
825 | } |
---|
826 | } |
---|
827 | } |
---|
828 | |
---|
829 | // =================================================================== |
---|
830 | // =====[ FLUSH ]===================================================== |
---|
831 | // =================================================================== |
---|
832 | |
---|
833 | for (uint32_t i=0; i<_param->_nb_context; ++i) |
---|
834 | { |
---|
835 | if (flush_UFPT [i]) |
---|
836 | { |
---|
837 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table"); |
---|
838 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i); |
---|
839 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); |
---|
840 | |
---|
841 | // It's to accelerate miss speculation |
---|
842 | if (reg_UFPT_NB_NEED_UPDATE [i] == 0) |
---|
843 | { |
---|
844 | |
---|
845 | // No entry need prediction, flush all entry -> Reset |
---|
846 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) |
---|
847 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; |
---|
848 | reg_UFPT_BOTTOM [i] = 0; |
---|
849 | reg_UFPT_TOP [i] = 0; |
---|
850 | // reg_UFPT_UPDATE [i]; |
---|
851 | } |
---|
852 | else |
---|
853 | { |
---|
854 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) |
---|
855 | // EMPTY : no event |
---|
856 | // END : already update |
---|
857 | // EVENT : previous event |
---|
858 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) |
---|
859 | { |
---|
860 | reg_UFPT_NB_UPDATE [i] ++; |
---|
861 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; |
---|
862 | } |
---|
863 | |
---|
864 | // TOP is next write slot : last slot is TOP-1 |
---|
865 | uint32_t top = reg_UFPT_TOP [i]; |
---|
866 | reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; |
---|
867 | |
---|
868 | // reg_UFPT_BOTTOM [i]; |
---|
869 | // reg_UFPT_TOP [i]; |
---|
870 | } |
---|
871 | |
---|
872 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]); |
---|
873 | |
---|
874 | } |
---|
875 | } |
---|
876 | |
---|
877 | #ifdef STATISTICS |
---|
878 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
879 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
880 | { |
---|
881 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) |
---|
882 | if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) |
---|
883 | (*_stat_ufpt_queue_nb_elt [i]) ++; |
---|
884 | for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) |
---|
885 | if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY) |
---|
886 | (*_stat_upt_queue_nb_elt [i]) ++; |
---|
887 | } |
---|
888 | #endif |
---|
889 | |
---|
890 | // =================================================================== |
---|
891 | // =====[ PRINT ]===================================================== |
---|
892 | // =================================================================== |
---|
893 | |
---|
894 | #if (DEBUG >= DEBUG_TRACE) |
---|
895 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table"); |
---|
896 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY); |
---|
897 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
898 | { |
---|
899 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); |
---|
900 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]); |
---|
901 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); |
---|
902 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); |
---|
903 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); |
---|
904 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); |
---|
905 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); |
---|
906 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2); |
---|
907 | |
---|
908 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); |
---|
909 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]); |
---|
910 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]); |
---|
911 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]); |
---|
912 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); |
---|
913 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); |
---|
914 | for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) |
---|
915 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s", |
---|
916 | j, |
---|
917 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition, |
---|
918 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src, |
---|
919 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2, |
---|
920 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest, |
---|
921 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2, |
---|
922 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take, |
---|
923 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate, |
---|
924 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history, |
---|
925 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras, |
---|
926 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2, |
---|
927 | reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras, |
---|
928 | toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str() |
---|
929 | ); |
---|
930 | |
---|
931 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); |
---|
932 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); |
---|
933 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); |
---|
934 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); |
---|
935 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); |
---|
936 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); |
---|
937 | for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) |
---|
938 | log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s", |
---|
939 | j, |
---|
940 | reg_UPDATE_PREDICTION_TABLE [i][j]._condition, |
---|
941 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_src, |
---|
942 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2, |
---|
943 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest, |
---|
944 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2, |
---|
945 | reg_UPDATE_PREDICTION_TABLE [i][j]._last_take, |
---|
946 | reg_UPDATE_PREDICTION_TABLE [i][j]._good_take, |
---|
947 | reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate, |
---|
948 | reg_UPDATE_PREDICTION_TABLE [i][j]._history, |
---|
949 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras, |
---|
950 | reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2, |
---|
951 | reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras, |
---|
952 | toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str() |
---|
953 | ); |
---|
954 | } |
---|
955 | #endif |
---|
956 | |
---|
957 | #ifdef DEBUG_TEST |
---|
958 | for (uint32_t i=0; i<_param->_nb_context; i++) |
---|
959 | { |
---|
960 | if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i]) |
---|
961 | throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i])); |
---|
962 | if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i]) |
---|
963 | throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i])); |
---|
964 | } |
---|
965 | #endif |
---|
966 | |
---|
967 | } |
---|
968 | |
---|
969 | |
---|
970 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
971 | end_cycle (); |
---|
972 | #endif |
---|
973 | |
---|
974 | log_end(Update_Prediction_Table,FUNCTION); |
---|
975 | }; |
---|
976 | |
---|
977 | }; // end namespace update_prediction_table |
---|
978 | }; // end namespace prediction_unit |
---|
979 | }; // end namespace front_end |
---|
980 | }; // end namespace multi_front_end |
---|
981 | }; // end namespace core |
---|
982 | |
---|
983 | }; // end namespace behavioural |
---|
984 | }; // end namespace morpheo |
---|
985 | #endif |
---|