Changeset 108 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
- Timestamp:
- Feb 12, 2009, 12:55:06 PM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r107 r108 126 126 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 127 127 reg_UPT_EMPTY [i] = false; 128 129 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 130 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 131 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 132 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 128 133 } 129 134 … … 210 215 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); 211 216 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); 212 217 213 218 if (miss_ifetch or miss_decod) 214 219 { … … 218 223 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 219 224 #endif 220 221 225 if (reg_UFPT_NB_NEED_UPDATE [context] == 0) 222 226 { … … 312 316 reg_UPT_EMPTY [context] = false; 313 317 // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; 318 319 // if (miss_ifetch or miss_decod) 320 // reg_UPT_TOP_EVENT [context] = reg_UPT_TOP [context]; 314 321 } 315 316 // ===================================================================317 // =====[ BRANCH_COMPLETE ]===========================================318 // ===================================================================319 320 // The branch is complete321 // * Hit prediction :322 // * update status323 // * Miss prediction :324 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)325 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])326 {327 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;328 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;329 Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];330 Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];331 Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];332 333 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);334 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);335 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);336 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);337 338 if (miss)339 {340 // Have a miss !!!341 // Flush UPFT342 flush_UFPT [context] = true;343 344 // Flush UPT345 uint32_t top = reg_UPT_TOP [context];346 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;347 348 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);349 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);350 351 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];352 j!=top;353 j=(j+1)%_param->_size_upt_queue[context])354 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;355 356 357 // reg_UPT_BOTTOM [context];358 reg_UPT_TOP [context] = depth;359 reg_UPT_TOP_EVENT [context] = top;360 361 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])362 reg_UPT_EMPTY [context] = true;363 364 #ifdef DEBUG_TEST365 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)366 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));367 #endif368 369 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);370 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;371 372 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;373 event_state_t event_state = reg_EVENT_STATE [context];374 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or375 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or376 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or377 (event_state == EVENT_STATE_EVENT_FLUSH_UPT));378 // bool update_ras = (new_update != depth);379 380 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);381 382 if (reg_UFPT_NB_NEED_UPDATE [context] > 0)383 {384 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);385 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;386 }387 else388 {389 // if (not previous_update_ras)390 {391 // have ras prediction ?392 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);393 394 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;395 396 }397 }398 399 if (not previous_update_ras)400 {401 reg_UPT_UPDATE [context] = new_update;402 }403 // else no update404 405 reg_EVENT_DEPTH [context] = depth;406 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State407 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;408 reg_EVENT_ADDRESS_DEST [context] = good_addr;409 }410 else411 {412 // Hit case413 414 #ifdef DEBUG_TEST415 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)416 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));417 #endif418 419 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);420 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;421 }422 423 // In all case : update good_take424 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;425 426 // Write address_dest if need read register427 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;428 429 if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or430 (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or431 (condition == BRANCH_CONDITION_READ_STACK ) )432 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;433 }434 322 435 323 // =================================================================== … … 599 487 } 600 488 489 490 // =================================================================== 491 // =====[ BRANCH_COMPLETE ]=========================================== 492 // =================================================================== 493 494 // The branch is complete 495 // * Hit prediction : 496 // * update status 497 // * Miss prediction : 498 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 499 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) 500 { 501 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 502 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 503 Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; 504 Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; 505 Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; 506 507 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 508 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 509 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 510 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 511 512 if (miss) 513 { 514 // Have a miss !!! 515 // Flush UPFT 516 flush_UFPT [context] = true; 517 518 // Flush UPT 519 uint32_t top = reg_UPT_TOP [context]; 520 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 521 522 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 523 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 524 525 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 526 j!=top; 527 j=(j+1)%_param->_size_upt_queue[context]) 528 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 529 530 531 // reg_UPT_BOTTOM [context]; 532 reg_UPT_TOP [context] = depth; 533 reg_UPT_TOP_EVENT [context] = top; 534 535 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 536 reg_UPT_EMPTY [context] = true; 537 538 #ifdef DEBUG_TEST 539 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 540 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 541 #endif 542 543 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 544 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 545 546 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 547 event_state_t event_state = reg_EVENT_STATE [context]; 548 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 550 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 551 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 552 // bool update_ras = (new_update != depth); 553 554 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 555 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_update_ras : %d",previous_update_ras); 556 557 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 558 { 559 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 560 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 561 } 562 else 563 { 564 // if (not previous_update_ras) 565 { 566 // have ras prediction ? 567 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 568 569 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 570 571 } 572 } 573 574 if (not previous_update_ras) 575 { 576 reg_UPT_UPDATE [context] = new_update; 577 } 578 // else no update 579 580 reg_EVENT_DEPTH [context] = depth; 581 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 582 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 583 reg_EVENT_ADDRESS_DEST [context] = good_addr; 584 } 585 else 586 { 587 // Hit case 588 589 // #ifdef DEBUG_TEST 590 // if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 591 // throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 592 // #endif 593 594 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) 595 { 596 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); 597 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; 598 } 599 } 600 601 // In all case : update good_take 602 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; 603 604 // Write address_dest if need read register 605 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 606 607 if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or 608 (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or 609 (condition == BRANCH_CONDITION_READ_STACK ) ) 610 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; 611 } 612 601 613 // =================================================================== 602 614 // =====[ BRANCH_EVENT ]============================================== … … 695 707 uint32_t bottom = reg_UPT_BOTTOM [i]; 696 708 uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 697 uint32_t full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 709 bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 710 // bool empty = reg_UPT_EMPTY [i]; 711 698 712 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 699 713 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 700 714 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 701 715 702 // Test empty 703 if (not reg_UPT_EMPTY [i]) 716 event_state_t event_state = reg_EVENT_STATE [i]; 717 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 718 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 719 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 720 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 721 722 bool find = false; // have slot to update ??? 723 724 // flush all slot after the event 725 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 726 j!=top; 727 j=(j+1)%_param->_size_upt_queue[i]) 728 if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and 729 (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) 730 { 731 find = true; 732 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 733 } 734 735 if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and 736 (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) 704 737 { 705 #ifdef DEBUG_TEST 706 if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 707 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 708 #endif 738 find = true; 709 739 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 710 740 } 741 742 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 743 744 // Test if have update slot 745 if (find) 746 { 711 747 // flush all slot after the event 712 748 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; … … 714 750 j=(j+1)%_param->_size_upt_queue[i]) 715 751 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 752 753 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 754 755 // reg_UPT_BOTTOM [i]; 756 // TODO : special case : event is an exception on branch, also depth is not valid 757 reg_UPT_TOP [i] = depth; // depth is again valid 758 reg_UPT_TOP_EVENT [i] = top; 759 760 if (bottom == reg_UPT_TOP [i]) 761 reg_UPT_EMPTY [i] = true; 716 762 } 763 764 bool update_ras = find and ((top != depth) or full); 765 766 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 767 768 if (not previous_update_ras and update_ras) 769 reg_UPT_UPDATE [i] = new_update; 717 770 718 // reg_UPT_BOTTOM [i];719 // TODO : special case : event is an exception on branch, also depth is not valid720 reg_UPT_TOP [i] = depth; // depth is again valid721 reg_UPT_TOP_EVENT [i] = top;722 723 if (bottom == reg_UPT_TOP [i])724 reg_UPT_EMPTY [i] = true;725 726 reg_EVENT_VAL [i] = true;727 reg_EVENT_UPT_PTR [i] = depth;728 event_state_t event_state = reg_EVENT_STATE [i];729 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or730 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or731 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or732 (event_state == EVENT_STATE_EVENT_FLUSH_UPT));733 bool update_ras = (top != depth) or full;734 735 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);736 737 771 // new state : 738 772 // * test if ufpt is empty … … 741 775 // * ok : nothing 742 776 // * ko : flush upt 777 reg_EVENT_VAL [i] = true; 778 reg_EVENT_UPT_PTR [i] = depth; 779 743 780 if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 744 781 { … … 766 803 else 767 804 { 805 // special case : nothing 806 reg_EVENT_VAL [i] = false; 807 768 808 reg_EVENT_STATE [i] = EVENT_STATE_OK; 769 809 } 770 810 } 771 772 if (not previous_update_ras and update_ras) 773 { 774 reg_UPT_UPDATE [i] = new_update; 775 } 811 776 812 // else no update 777 813 … … 817 853 { 818 854 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 819 { 820 reg_UFPT_NB_UPDATE [i] ++; 821 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 822 } 855 // EMPTY : no event 856 // END : already update 857 // EVENT : previous event 858 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) 859 { 860 reg_UFPT_NB_UPDATE [i] ++; 861 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 862 } 823 863 824 864 // TOP is next write slot : last slot is TOP-1 … … 862 902 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 863 903 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 864 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x ",reg_EVENT_ADDRESS_SRC [i]);904 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); 865 905 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); 866 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x ",reg_EVENT_ADDRESS_DEST [i]);906 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2); 867 907 868 908 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); … … 914 954 } 915 955 #endif 956 957 #ifdef DEBUG_TEST 958 for (uint32_t i=0; i<_param->_nb_context; i++) 959 { 960 if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i]) 961 throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i])); 962 if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i]) 963 throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i])); 964 } 965 #endif 966 916 967 } 917 968
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