[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Commit_unit_transition.cpp 100 2009-01-08 13:06:27Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace commit_unit { |
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| 17 | |
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| 18 | |
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| 19 | #undef FUNCTION |
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| 20 | #define FUNCTION "Commit_unit::transition" |
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| 21 | void Commit_unit::transition (void) |
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| 22 | { |
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| 23 | log_begin(Commit_unit,FUNCTION); |
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| 24 | log_function(Commit_unit,FUNCTION,_name.c_str()); |
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| 25 | |
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| 26 | if (PORT_READ(in_NRESET) == 0) |
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| 27 | { |
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[100] | 28 | // Clear all bank |
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[88] | 29 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 30 | { |
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| 31 | _rob [i].clear(); |
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| 32 | reg_BANK_PTR [i] = 0; |
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| 33 | } |
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| 34 | |
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[100] | 35 | // Reset pointer |
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[88] | 36 | reg_NUM_BANK_HEAD = 0; |
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| 37 | reg_NUM_BANK_TAIL = 0; |
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| 38 | |
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[100] | 39 | // Reset counter |
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[88] | 40 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 41 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 42 | { |
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| 43 | reg_NB_INST_COMMIT_ALL [i][j] = 0; |
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| 44 | reg_NB_INST_COMMIT_MEM [i][j] = 0; |
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[100] | 45 | |
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| 46 | reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; |
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[88] | 47 | } |
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| 48 | |
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[100] | 49 | // Reset priority algorithm |
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[88] | 50 | _priority_insert->reset(); |
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| 51 | } |
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| 52 | else |
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| 53 | { |
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[100] | 54 | // Compute next priority |
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[88] | 55 | _priority_insert->transition(); |
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| 56 | |
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| 57 | // =================================================================== |
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[100] | 58 | // =====[ GARBAGE COLLECTOR ]========================================= |
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| 59 | // =================================================================== |
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| 60 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 61 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 62 | switch (reg_EVENT_STATE [i][j]) |
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| 63 | { |
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| 64 | case EVENT_STATE_EVENT : reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; break; |
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| 65 | case EVENT_STATE_END : reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; break; |
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| 66 | // case EVENT_STATE_NO_EVENT : |
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| 67 | // case EVENT_STATE_WAITEND : |
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| 68 | default : break; |
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| 69 | } |
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| 70 | |
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| 71 | // =================================================================== |
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[88] | 72 | // =====[ INSERT ]==================================================== |
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| 73 | // =================================================================== |
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| 74 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 75 | if (internal_BANK_INSERT_VAL [i]) |
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| 76 | { |
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[100] | 77 | // get rename unit source and instruction. |
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[88] | 78 | uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; |
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| 79 | uint32_t y = internal_BANK_INSERT_NUM_INST [i]; |
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| 80 | |
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| 81 | if (PORT_READ(in_INSERT_VAL [x][y])) |
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| 82 | { |
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| 83 | log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); |
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| 84 | |
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| 85 | #ifdef STATISTICS |
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| 86 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 87 | (*_stat_nb_inst_insert [x]) ++; |
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| 88 | #endif |
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| 89 | |
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[100] | 90 | // get information |
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[88] | 91 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; |
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| 92 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; |
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| 93 | Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); |
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| 94 | Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); |
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[100] | 95 | bool is_store = is_operation_memory_store(operation); |
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| 96 | |
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[88] | 97 | Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); |
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| 98 | |
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| 99 | log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 100 | log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); |
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[97] | 101 | log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); |
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[88] | 102 | log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); |
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| 103 | log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); |
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[100] | 104 | |
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| 105 | // Create new entry. |
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[88] | 106 | entry_t * entry = new entry_t; |
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| 107 | |
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| 108 | entry->ptr = reg_BANK_PTR [i]; |
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| 109 | entry->front_end_id = front_end_id; |
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| 110 | entry->context_id = context_id ; |
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| 111 | entry->rename_unit_id = x; |
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| 112 | entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; |
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| 113 | entry->type = type; |
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| 114 | entry->operation = operation; |
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| 115 | entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); |
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| 116 | entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); |
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| 117 | entry->exception = exception; |
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| 118 | entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); |
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[100] | 119 | entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store); |
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| 120 | entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store); |
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[88] | 121 | entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); |
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| 122 | entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; |
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| 123 | entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); |
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| 124 | entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); |
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| 125 | entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); |
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| 126 | entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); |
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| 127 | entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); |
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| 128 | entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); |
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| 129 | entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); |
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| 130 | entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); |
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| 131 | entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); |
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| 132 | entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); |
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| 133 | entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); |
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| 134 | entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); |
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| 135 | entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); |
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| 136 | entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); |
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| 137 | entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); |
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| 138 | entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); |
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| 139 | entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); |
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| 140 | |
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[100] | 141 | // Test if exception : |
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| 142 | // * yes : no execute instruction, wait ROB Head |
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| 143 | // * no : test type |
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| 144 | // * BRANCH : l.j -> branch is ended |
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| 145 | // other -> wait the execution end of branchment |
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| 146 | // * MEMORY : store -> wait store is at head of ROB |
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| 147 | // other -> wait end of instruction |
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| 148 | // * OTHER |
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[88] | 149 | if (exception == EXCEPTION_NONE) |
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| 150 | { |
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| 151 | Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); |
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| 152 | // no_execute : l.j, l.nop, l.rfe |
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| 153 | |
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| 154 | log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); |
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| 155 | |
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| 156 | switch (type) |
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| 157 | { |
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| 158 | case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} |
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[100] | 159 | case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} |
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[88] | 160 | default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} |
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| 161 | } |
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| 162 | } |
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| 163 | else |
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| 164 | { |
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[100] | 165 | // Have an exception : wait head of ROB |
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| 166 | |
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[88] | 167 | // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap |
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| 168 | |
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| 169 | entry->state = ROB_END_EXCEPTION_WAIT_HEAD; |
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| 170 | } |
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| 171 | |
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[100] | 172 | // Push in rob |
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[88] | 173 | _rob[i].push_back(entry); |
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| 174 | |
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[100] | 175 | // Update counter and pointer |
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[88] | 176 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; |
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| 177 | if (type == TYPE_MEMORY) |
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| 178 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; |
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| 179 | |
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| 180 | reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank; |
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| 181 | reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank; |
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| 182 | } |
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| 183 | } |
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| 184 | |
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| 185 | // =================================================================== |
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| 186 | // =====[ COMMIT ]==================================================== |
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| 187 | // =================================================================== |
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| 188 | |
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| 189 | #ifdef STATISTICS |
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| 190 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 191 | (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; |
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| 192 | #endif |
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| 193 | |
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| 194 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 195 | for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) |
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| 196 | if (internal_BANK_COMMIT_VAL [i][j]) |
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| 197 | { |
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[100] | 198 | // An instruction is executed. Change state of this instruction |
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| 199 | |
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[88] | 200 | uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; |
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| 201 | |
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| 202 | if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) |
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| 203 | { |
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| 204 | log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); |
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| 205 | |
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| 206 | #ifdef STATISTICS |
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| 207 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 208 | (*_stat_nb_inst_commit) ++; |
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| 209 | #endif |
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| 210 | |
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| 211 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); |
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| 212 | |
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| 213 | // find the good entry !!! |
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[100] | 214 | entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; |
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| 215 | |
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| 216 | //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); |
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| 217 | //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); |
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| 218 | Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); |
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[88] | 219 | |
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[100] | 220 | rob_state_t state = entry->state; |
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| 221 | Tcontext_t front_end_id = entry->front_end_id; |
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| 222 | Tcontext_t context_id = entry->context_id; |
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[88] | 223 | |
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[100] | 224 | // change state : test exception_use |
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[88] | 225 | // * test if exception : exception and mask |
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| 226 | |
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[100] | 227 | bool have_exception = false; |
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| 228 | bool have_miss_speculation = false; |
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| 229 | |
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[88] | 230 | if (exception != EXCEPTION_NONE) |
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[100] | 231 | { |
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| 232 | // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) |
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| 233 | have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); |
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[88] | 234 | |
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[100] | 235 | switch (entry->exception_use) |
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| 236 | { |
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| 237 | // Have overflow exception if bit overflow enable is set. |
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| 238 | case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} |
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| 239 | case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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| 240 | (exception == EXCEPTION_DATA_TLB ) or |
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| 241 | (exception == EXCEPTION_DATA_PAGE) or |
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| 242 | (exception == EXCEPTION_ALIGNMENT)); break;}; |
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| 243 | case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or |
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| 244 | (exception == EXCEPTION_DATA_TLB ) or |
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| 245 | (exception == EXCEPTION_DATA_PAGE)); break;}; |
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| 246 | case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; |
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| 247 | case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; |
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| 248 | case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; |
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| 249 | case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; |
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| 250 | case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; |
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| 251 | case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; |
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| 252 | case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; |
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| 253 | // Case already manage (decod stage -> in insert in ROB) |
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| 254 | case EXCEPTION_USE_TRAP : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 255 | case EXCEPTION_USE_NONE : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 256 | case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 257 | case EXCEPTION_USE_SYSCALL : {have_exception = false; exception = EXCEPTION_NONE; break;}; |
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| 258 | default : |
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| 259 | { |
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| 260 | throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); |
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| 261 | break; |
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| 262 | } |
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| 263 | } |
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| 264 | } |
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| 265 | |
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| 266 | switch (state) |
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| 267 | { |
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| 268 | // Branch ... |
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| 269 | case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} |
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| 270 | // Store KO |
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| 271 | case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} |
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| 272 | // Store OK, Load and other instruction |
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| 273 | case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_MISS:ROB_END_OK_SPECULATIVE); break;} |
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| 274 | default : |
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| 275 | { |
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| 276 | throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); |
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| 277 | break; |
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| 278 | } |
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| 279 | } |
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[88] | 280 | |
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| 281 | // update Re Order Buffer |
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| 282 | entry->state = state; |
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| 283 | entry->exception = exception; |
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| 284 | entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); |
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| 285 | entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); |
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| 286 | entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]); |
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| 287 | } |
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| 288 | } |
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| 289 | |
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| 290 | // =================================================================== |
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| 291 | // =====[ RETIRE ]==================================================== |
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| 292 | // =================================================================== |
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| 293 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 294 | if (internal_BANK_RETIRE_VAL [i]) |
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| 295 | { |
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| 296 | uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i]; |
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| 297 | uint32_t y = internal_BANK_RETIRE_NUM_INST [i]; |
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| 298 | |
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| 299 | log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); |
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| 300 | |
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| 301 | #ifdef DEBUG_TEST |
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| 302 | if (not PORT_READ(in_RETIRE_ACK [x][y])) |
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| 303 | throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); |
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| 304 | #endif |
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| 305 | |
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[98] | 306 | entry_t * entry = _rob [i].front(); |
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[100] | 307 | rob_state_t state = entry->state; |
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| 308 | |
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[98] | 309 | #ifdef STATISTICS |
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| 310 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 311 | { |
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| 312 | if (state == ROB_END_OK) |
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| 313 | (*_stat_nb_inst_retire_ok [x]) ++; |
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| 314 | else |
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| 315 | (*_stat_nb_inst_retire_ko [x]) ++; |
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| 316 | } |
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| 317 | #endif |
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[88] | 318 | |
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| 319 | Tcontext_t front_end_id = entry->front_end_id; |
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| 320 | Tcontext_t context_id = entry->context_id ; |
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| 321 | Ttype_t type = entry->type ; |
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[100] | 322 | |
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| 323 | if (state == ROB_END_BRANCH_MISS) |
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| 324 | { |
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| 325 | reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; |
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| 326 | |
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| 327 | // !!!!!!!!!!! Compute address |
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| 328 | } |
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[88] | 329 | |
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| 330 | // Update nb_inst |
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| 331 | reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; |
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| 332 | if (type == TYPE_MEMORY) |
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| 333 | reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; |
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[100] | 334 | |
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| 335 | if (reg_NB_INST_COMMIT_ALL [front_end_id][context_id] == 0) |
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| 336 | reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_END; |
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| 337 | |
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[88] | 338 | reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; |
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| 339 | |
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| 340 | _rob [i].pop_front(); |
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| 341 | delete entry; |
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| 342 | } |
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| 343 | |
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| 344 | // =================================================================== |
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| 345 | // =====[ REEXECUTE ]================================================= |
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| 346 | // =================================================================== |
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| 347 | if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) |
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| 348 | { |
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| 349 | uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; |
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| 350 | |
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| 351 | entry_t * entry = _rob [num_bank].front(); |
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| 352 | rob_state_t state = entry->state; |
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| 353 | |
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| 354 | switch (state) |
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| 355 | { |
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| 356 | case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } |
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| 357 | case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; } |
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| 358 | default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} |
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| 359 | } |
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| 360 | |
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| 361 | entry->state = state; |
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| 362 | } |
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| 363 | |
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| 364 | // =================================================================== |
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| 365 | // =====[ BRANCH_COMPLETE ]=========================================== |
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| 366 | // =================================================================== |
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| 367 | for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) |
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| 368 | if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) |
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| 369 | { |
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| 370 | uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; |
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| 371 | |
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| 372 | entry_t * entry = _rob [num_bank].front(); |
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| 373 | |
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| 374 | #ifdef DEBUG_TEST |
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| 375 | rob_state_t state = entry->state; |
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| 376 | if (state != ROB_BRANCH_COMPLETE) |
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| 377 | throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); |
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| 378 | #endif |
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| 379 | |
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[100] | 380 | entry->state = (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))?ROB_END_OK_SPECULATIVE:ROB_END_BRANCH_MISS_SPECULATIVE; |
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| 381 | // entry->state = ROB_END_OK_SPECULATIVE; |
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[88] | 382 | } |
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| 383 | |
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| 384 | // =================================================================== |
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[100] | 385 | // =====[ UPDATE ]==================================================== |
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| 386 | // =================================================================== |
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| 387 | { |
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| 388 | // Not yet implemented |
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| 389 | } |
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| 390 | |
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| 391 | // =================================================================== |
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[88] | 392 | // =====[ EVENT ]===================================================== |
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| 393 | // =================================================================== |
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[100] | 394 | { |
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| 395 | // Not yet implemented |
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| 396 | } |
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[88] | 397 | |
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| 398 | // =================================================================== |
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| 399 | // =====[ DEPTH - HEAD ]============================================== |
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| 400 | // =================================================================== |
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| 401 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 402 | if (not _rob[i].empty()) |
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| 403 | { |
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| 404 | // Scan all instruction in windows and test if instruction is speculative |
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| 405 | entry_t * entry = _rob [i].front(); |
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| 406 | |
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| 407 | Tcontext_t front_end_id = entry->front_end_id; |
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| 408 | Tcontext_t context_id = entry->context_id ; |
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| 409 | rob_state_t state = entry->state; |
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| 410 | Tdepth_t depth = entry->depth; |
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| 411 | |
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| 412 | Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [front_end_id][context_id]):0; |
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| 413 | Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[front_end_id][context_id]); |
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| 414 | |
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| 415 | // is a valid instruction ? |
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| 416 | // If DEPTH_CURRENT : |
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| 417 | // equal at DEPTH_MIN -> not speculative |
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| 418 | // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss |
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| 419 | // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative |
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| 420 | |
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| 421 | // All case |
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| 422 | // ....... min ...X... max ....... OK |
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| 423 | // ....... min ....... max ...X... KO |
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| 424 | // ...X... min ....... max ....... KO |
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| 425 | // ....... max ....... min ...X... OK |
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| 426 | // ...X... max ....... min ....... OK |
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| 427 | // ....... max ...X... min ....... KO |
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| 428 | |
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| 429 | Tcontrol_t is_valid = ((depth == depth_min) or |
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| 430 | ((depth_min < depth_max)? |
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| 431 | (depth<depth_max): |
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| 432 | ((depth > depth_min) or (depth < depth_max)))); |
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| 433 | |
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| 434 | //------------------------------------------------------ |
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| 435 | // test if instruction is miss speculative |
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| 436 | //------------------------------------------------------ |
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| 437 | if (not is_valid) |
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| 438 | { |
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| 439 | switch (state) |
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| 440 | { |
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[100] | 441 | case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} |
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| 442 | case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} |
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| 443 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} |
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| 444 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} |
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| 445 | //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} |
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| 446 | case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} |
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| 447 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} |
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| 448 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} |
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| 449 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} |
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| 450 | |
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| 451 | // don't change |
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| 452 | case ROB_STORE_HEAD_KO : {break;} |
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| 453 | case ROB_MISS_WAIT_END : {break;} |
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| 454 | case ROB_END_MISS : {break;} |
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| 455 | |
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| 456 | // can't have miss speculation |
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| 457 | case ROB_STORE_HEAD_OK : |
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| 458 | case ROB_END_OK : |
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| 459 | case ROB_END_KO : |
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| 460 | case ROB_END_BRANCH_MISS : |
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| 461 | case ROB_END_EXCEPTION : |
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| 462 | default : |
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[88] | 463 | { |
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| 464 | throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); |
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| 465 | break; |
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| 466 | } |
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| 467 | } |
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| 468 | } |
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| 469 | |
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| 470 | //------------------------------------------------------ |
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| 471 | // test if instruction is not speculative |
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| 472 | //------------------------------------------------------ |
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| 473 | if (entry->depth == depth_min) |
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| 474 | { |
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| 475 | switch (state) |
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| 476 | { |
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[100] | 477 | case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} |
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| 478 | case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} |
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| 479 | case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} |
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[88] | 480 | default : {break;} |
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| 481 | } |
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| 482 | } |
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| 483 | |
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| 484 | //------------------------------------------------------ |
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| 485 | // test if instruction is store and head |
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| 486 | //------------------------------------------------------ |
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| 487 | if (i == reg_NUM_BANK_HEAD) |
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| 488 | { |
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| 489 | switch (state) |
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| 490 | { |
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| 491 | case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} |
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| 492 | case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;} |
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| 493 | default : {break;} |
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| 494 | } |
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| 495 | } |
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| 496 | |
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| 497 | entry->state = state; |
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| 498 | } |
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| 499 | } |
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| 500 | |
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| 501 | // =================================================================== |
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| 502 | // =====[ OTHER ]===================================================== |
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| 503 | // =================================================================== |
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| 504 | |
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| 505 | log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); |
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| 506 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); |
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| 507 | log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); |
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| 508 | |
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| 509 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 510 | for (uint32_t j=0; j<_param->_nb_context [i]; j++) |
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| 511 | log_printf(TRACE,Commit_unit,FUNCTION," * num_inst[%d][%d] all : %d, mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]); |
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| 512 | |
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| 513 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 514 | { |
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| 515 | log_printf(TRACE,Commit_unit,FUNCTION," * Bank[%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); |
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| 516 | |
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| 517 | #ifdef STATISTICS |
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| 518 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 519 | *(_stat_bank_nb_inst [i]) += _rob[i].size(); |
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| 520 | #endif |
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| 521 | |
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| 522 | uint32_t x=0; |
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| 523 | for (std::list<entry_t*>::iterator it=_rob[i].begin(); |
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| 524 | it!=_rob[i].end(); |
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| 525 | it++) |
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| 526 | { |
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[98] | 527 | log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d", |
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[88] | 528 | x, |
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[97] | 529 | (*it)->front_end_id , |
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| 530 | (*it)->context_id , |
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| 531 | (*it)->rename_unit_id , |
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| 532 | (*it)->depth , |
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| 533 | (*it)->type , |
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| 534 | (*it)->operation , |
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| 535 | (*it)->address , |
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[98] | 536 | (*it)->address << 2 , |
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[97] | 537 | (*it)->is_delay_slot , |
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| 538 | (*it)->use_store_queue , |
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| 539 | (*it)->store_queue_ptr_write , |
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| 540 | (*it)->use_load_queue , |
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| 541 | (*it)->load_queue_ptr_write , |
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| 542 | toString((*it)->state).c_str() , |
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| 543 | (*it)->ptr ); |
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| 544 | log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.1d %.6d %.6d, %.1d %.1d %.6d %.6d ", |
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| 545 | (*it)->read_ra , |
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| 546 | (*it)->num_reg_ra_log , |
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| 547 | (*it)->num_reg_ra_phy , |
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| 548 | (*it)->read_rb , |
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| 549 | (*it)->num_reg_rb_log , |
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| 550 | (*it)->num_reg_rb_phy , |
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| 551 | (*it)->read_rc , |
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| 552 | (*it)->num_reg_rc_log , |
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| 553 | (*it)->num_reg_rc_phy , |
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| 554 | (*it)->write_rd , |
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| 555 | (*it)->num_reg_rd_log , |
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| 556 | (*it)->num_reg_rd_phy_old , |
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| 557 | (*it)->num_reg_rd_phy_new , |
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| 558 | (*it)->write_re , |
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| 559 | (*it)->num_reg_re_log , |
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| 560 | (*it)->num_reg_re_phy_old , |
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| 561 | (*it)->num_reg_re_phy_new ); |
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| 562 | |
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[100] | 563 | log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x", |
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[97] | 564 | (*it)->exception , |
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| 565 | (*it)->exception_use , |
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| 566 | (*it)->flags , |
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| 567 | (*it)->no_sequence , |
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[100] | 568 | (*it)->data_commit |
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[97] | 569 | ); |
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| 570 | |
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[88] | 571 | x++; |
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| 572 | } |
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| 573 | } |
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| 574 | |
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| 575 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 576 | end_cycle (); |
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| 577 | #endif |
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| 578 | |
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| 579 | log_end(Commit_unit,FUNCTION); |
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| 580 | }; |
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| 581 | |
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| 582 | }; // end namespace commit_unit |
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| 583 | }; // end namespace ooo_engine |
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| 584 | }; // end namespace multi_ooo_engine |
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| 585 | }; // end namespace core |
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| 586 | |
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| 587 | }; // end namespace behavioural |
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| 588 | }; // end namespace morpheo |
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| 589 | #endif |
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