[78] | 1 | #ifdef SYSTEMC |
---|
| 2 | /* |
---|
| 3 | * $Id: Register_Address_Translation_unit_transition.cpp 123 2009-06-08 20:43:30Z rosiere $ |
---|
| 4 | * |
---|
| 5 | * [ Description ] |
---|
| 6 | * |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
---|
| 10 | |
---|
| 11 | namespace morpheo { |
---|
| 12 | namespace behavioural { |
---|
| 13 | namespace core { |
---|
| 14 | namespace multi_ooo_engine { |
---|
| 15 | namespace ooo_engine { |
---|
| 16 | namespace rename_unit { |
---|
| 17 | namespace register_translation_unit { |
---|
| 18 | namespace register_address_translation_unit { |
---|
| 19 | |
---|
| 20 | |
---|
| 21 | #undef FUNCTION |
---|
| 22 | #define FUNCTION "Register_Address_Translation_unit::transition" |
---|
| 23 | void Register_Address_Translation_unit::transition (void) |
---|
| 24 | { |
---|
[88] | 25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
---|
| 26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
---|
[78] | 27 | |
---|
| 28 | if (PORT_READ(in_NRESET) == 0) |
---|
| 29 | { |
---|
| 30 | uint32_t gpr = 1; |
---|
| 31 | uint32_t spr = 0; |
---|
| 32 | |
---|
| 33 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
---|
| 34 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
---|
| 35 | { |
---|
[122] | 36 | rat_gpr_not_speculative [i][j][0] = 0; |
---|
| 37 | rat_gpr_speculative_valid [i][j][0] = false; |
---|
[78] | 38 | |
---|
| 39 | for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) |
---|
[100] | 40 | { |
---|
[122] | 41 | rat_gpr_not_speculative [i][j][k] = gpr++; |
---|
| 42 | rat_gpr_speculative_valid [i][j][k] = false; |
---|
[123] | 43 | rat_gpr_speculative [i][j][k] = 0 ; // not necessary |
---|
| 44 | rat_gpr_update_table [i][j][k] = false; // not necessary |
---|
[100] | 45 | } |
---|
[78] | 46 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
---|
[100] | 47 | { |
---|
[122] | 48 | rat_spr_not_speculative [i][j][k] = spr++; |
---|
| 49 | rat_spr_speculative_valid [i][j][k] = false; |
---|
[123] | 50 | rat_spr_speculative [i][j][k] = 0 ; // not necessary |
---|
| 51 | rat_spr_update_table [i][j][k] = false; // not necessary |
---|
[100] | 52 | } |
---|
[78] | 53 | } |
---|
| 54 | } |
---|
| 55 | else |
---|
| 56 | { |
---|
| 57 | // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) |
---|
| 58 | |
---|
| 59 | // ===================================================== |
---|
[122] | 60 | // ====[ RETIRE_EVENT ]================================= |
---|
| 61 | // ===================================================== |
---|
| 62 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
---|
| 63 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
---|
| 64 | if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) |
---|
| 65 | // Test if event have just occure |
---|
| 66 | if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) |
---|
| 67 | { |
---|
| 68 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table"); |
---|
| 69 | |
---|
| 70 | // Reset update_table and validity table |
---|
| 71 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
---|
| 72 | { |
---|
| 73 | rat_gpr_update_table [i][j][k] = false; |
---|
| 74 | rat_gpr_speculative_valid [i][j][k] = false; |
---|
| 75 | } |
---|
| 76 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
---|
| 77 | { |
---|
| 78 | rat_spr_update_table [i][j][k] = false; |
---|
| 79 | rat_spr_speculative_valid [i][j][k] = false; |
---|
| 80 | } |
---|
| 81 | } |
---|
| 82 | |
---|
| 83 | // ===================================================== |
---|
[78] | 84 | // ====[ INSERT ]======================================= |
---|
| 85 | // ===================================================== |
---|
| 86 | // First : interface insert |
---|
[122] | 87 | // this instruction is speculative !!! |
---|
[78] | 88 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
---|
| 89 | // Test transaction |
---|
| 90 | if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) |
---|
| 91 | { |
---|
[104] | 92 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); |
---|
| 93 | |
---|
[78] | 94 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
---|
| 95 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
---|
[122] | 96 | Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); |
---|
| 97 | Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); |
---|
[106] | 98 | |
---|
[122] | 99 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); |
---|
| 100 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); |
---|
[78] | 101 | |
---|
[122] | 102 | // Test if write and modifie RAT |
---|
| 103 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
---|
| 104 | if (write_rd == 1) |
---|
[106] | 105 | { |
---|
[122] | 106 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]); |
---|
| 107 | Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); |
---|
| 108 | |
---|
| 109 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log); |
---|
| 110 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); |
---|
| 111 | |
---|
| 112 | rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy; |
---|
| 113 | rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true; |
---|
[106] | 114 | } |
---|
| 115 | |
---|
[122] | 116 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
---|
| 117 | if (write_re == 1) |
---|
[106] | 118 | { |
---|
[122] | 119 | Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]); |
---|
| 120 | Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); |
---|
| 121 | |
---|
| 122 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log); |
---|
| 123 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); |
---|
| 124 | |
---|
| 125 | rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy; |
---|
| 126 | rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true; |
---|
[106] | 127 | } |
---|
[78] | 128 | } |
---|
| 129 | |
---|
| 130 | // ===================================================== |
---|
| 131 | // ====[ RETIRE ]======================================= |
---|
| 132 | // ===================================================== |
---|
| 133 | // Second : interface retire |
---|
| 134 | // (because if an event on the same thread : the instruction is already renamed) |
---|
| 135 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
| 136 | if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) |
---|
| 137 | { |
---|
[104] | 138 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); |
---|
| 139 | |
---|
[78] | 140 | // if no event : no effect, because the RAT content the most recently register |
---|
| 141 | // but if they have a event (exception or miss speculation), the rat must restore the oldest value |
---|
| 142 | // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register |
---|
| 143 | // the retire interface became of the Re Order Buffer, also is in program sequence ! |
---|
[104] | 144 | |
---|
[122] | 145 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; |
---|
| 146 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; |
---|
| 147 | Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); |
---|
| 148 | Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); |
---|
| 149 | Tcontrol_t restore = internal_RETIRE_RESTORE [i]; |
---|
[104] | 150 | |
---|
[122] | 151 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
---|
| 152 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); |
---|
| 153 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore ); |
---|
[106] | 154 | |
---|
[122] | 155 | // Test if write and have not a previous update |
---|
| 156 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
---|
| 157 | if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) |
---|
| 158 | { |
---|
| 159 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); |
---|
| 160 | |
---|
| 161 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); |
---|
| 162 | |
---|
| 163 | if (not restore) |
---|
| 164 | { |
---|
| 165 | Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
---|
| 166 | |
---|
| 167 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); |
---|
| 168 | |
---|
| 169 | rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; |
---|
| 170 | } |
---|
| 171 | |
---|
| 172 | Tcontrol_t restore_rd = internal_RETIRE_RESTORE_RD_PHY_OLD [i]; |
---|
| 173 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_rd : %d",restore_rd ); |
---|
[112] | 174 | |
---|
[122] | 175 | if (restore_rd) |
---|
| 176 | rat_gpr_update_table [front_end_id][context_id][num_reg_rd_log] = true; |
---|
| 177 | } |
---|
[112] | 178 | |
---|
[122] | 179 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
---|
| 180 | if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1) |
---|
| 181 | { |
---|
| 182 | Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); |
---|
[78] | 183 | |
---|
[122] | 184 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); |
---|
[78] | 185 | |
---|
[122] | 186 | if (not restore) |
---|
| 187 | { |
---|
| 188 | Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
---|
[104] | 189 | |
---|
[122] | 190 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); |
---|
[112] | 191 | |
---|
[122] | 192 | rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; |
---|
| 193 | } |
---|
| 194 | |
---|
| 195 | Tcontrol_t restore_re = internal_RETIRE_RESTORE_RE_PHY_OLD [i]; |
---|
| 196 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re : %d",restore_re ); |
---|
| 197 | |
---|
| 198 | if (restore_re) |
---|
| 199 | rat_spr_update_table [front_end_id][context_id][num_reg_re_log] = true; |
---|
| 200 | } |
---|
| 201 | |
---|
[78] | 202 | } |
---|
| 203 | } |
---|
| 204 | |
---|
[88] | 205 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) |
---|
[106] | 206 | { |
---|
| 207 | uint32_t limit = 4; |
---|
| 208 | |
---|
| 209 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); |
---|
| 210 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
---|
| 211 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
---|
| 212 | { |
---|
| 213 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); |
---|
| 214 | |
---|
| 215 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) |
---|
| 216 | { |
---|
| 217 | std::string str = ""; |
---|
| 218 | for (uint32_t x=0; x<limit; x++) |
---|
| 219 | { |
---|
| 220 | uint32_t index = k+x; |
---|
| 221 | if (index >= _param->_nb_general_register_logic) |
---|
| 222 | break; |
---|
| 223 | else |
---|
[122] | 224 | str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) %.1d | ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index],rat_gpr_update_table[i][j][index]); |
---|
[106] | 225 | } |
---|
| 226 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
---|
| 227 | } |
---|
| 228 | |
---|
| 229 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) |
---|
| 230 | { |
---|
| 231 | std::string str = ""; |
---|
| 232 | |
---|
| 233 | for (uint32_t x=0; x<limit; x++) |
---|
| 234 | { |
---|
| 235 | uint32_t index = k+x; |
---|
| 236 | if (index >= _param->_nb_special_register_logic) |
---|
| 237 | break; |
---|
| 238 | else |
---|
[122] | 239 | str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) %.1d | ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index],rat_spr_update_table[i][j][index]); |
---|
[106] | 240 | } |
---|
| 241 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
---|
| 242 | } |
---|
| 243 | } |
---|
| 244 | } |
---|
| 245 | #endif |
---|
[88] | 246 | |
---|
[106] | 247 | #ifdef DEBUG_TEST |
---|
[122] | 248 | # if 1 |
---|
| 249 | { |
---|
| 250 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
---|
| 251 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
---|
[106] | 252 | { |
---|
[122] | 253 | for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x) |
---|
| 254 | for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) |
---|
[106] | 255 | { |
---|
[122] | 256 | if (rat_gpr_speculative_valid [i][j][x] and |
---|
| 257 | rat_gpr_speculative_valid [i][j][y] and |
---|
| 258 | (rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y])) |
---|
| 259 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x])); |
---|
| 260 | if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y]) |
---|
| 261 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x])); |
---|
| 262 | |
---|
[106] | 263 | } |
---|
[122] | 264 | for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x) |
---|
| 265 | for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) |
---|
| 266 | { |
---|
| 267 | if(rat_spr_speculative_valid [i][j][x] and |
---|
| 268 | rat_spr_speculative_valid [i][j][y] and |
---|
| 269 | (rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y])) |
---|
| 270 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x])); |
---|
| 271 | if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y]) |
---|
| 272 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x])); |
---|
| 273 | |
---|
| 274 | } |
---|
[106] | 275 | } |
---|
[122] | 276 | |
---|
| 277 | } |
---|
| 278 | # endif |
---|
[88] | 279 | #endif |
---|
| 280 | |
---|
[78] | 281 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
---|
| 282 | end_cycle (); |
---|
| 283 | #endif |
---|
| 284 | |
---|
[88] | 285 | log_end(Register_Address_Translation_unit,FUNCTION); |
---|
[78] | 286 | }; |
---|
| 287 | |
---|
| 288 | }; // end namespace register_address_translation_unit |
---|
| 289 | }; // end namespace register_translation_unit |
---|
| 290 | }; // end namespace rename_unit |
---|
| 291 | }; // end namespace ooo_engine |
---|
| 292 | }; // end namespace multi_ooo_engine |
---|
| 293 | }; // end namespace core |
---|
| 294 | |
---|
| 295 | }; // end namespace behavioural |
---|
| 296 | }; // end namespace morpheo |
---|
| 297 | #endif |
---|