[2] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: RegisterFile_Monolithic_vhdl_body.cpp 146 2011-02-01 20:57:54Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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[15] | 9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" |
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[2] | 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace generic { |
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| 14 | namespace registerfile { |
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[15] | 15 | namespace registerfile_monolithic { |
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[2] | 16 | |
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[41] | 17 | void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl) |
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[2] | 18 | { |
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[145] | 19 | #ifndef VHDL_GAISLER |
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| 20 | |
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[94] | 21 | vhdl->set_body (0,""); |
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| 22 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 23 | vhdl->set_comment(0," Ackitement"); |
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| 24 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 25 | vhdl->set_body (0,""); |
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[55] | 26 | |
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| 27 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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[94] | 28 | vhdl->set_body (0,"out_READ_"+toString(i)+"_ACK <= '1';"); |
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[55] | 29 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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[94] | 30 | vhdl->set_body (0,"out_WRITE_"+toString(i)+"_ACK <= '1';"); |
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[55] | 31 | |
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[94] | 32 | vhdl->set_body (0,""); |
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| 33 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 34 | vhdl->set_comment(0," Read RegisterFile"); |
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| 35 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 36 | vhdl->set_body (0,""); |
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[2] | 37 | |
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[55] | 38 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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[62] | 39 | { |
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[75] | 40 | std::string str_address; |
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[62] | 41 | if (_param->_have_port_address) |
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| 42 | str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)"; |
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| 43 | else |
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| 44 | str_address = "0"; |
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[2] | 45 | |
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[94] | 46 | vhdl->set_body (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+") when in_READ_"+toString(i)+"_VAL = '1' else "+std_logic_others(_param->_size_word,0)+";"); |
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[62] | 47 | } |
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[55] | 48 | |
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[94] | 49 | vhdl->set_body (0,""); |
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| 50 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 51 | vhdl->set_comment(0," Write RegisterFile"); |
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| 52 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 53 | vhdl->set_body (0,""); |
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[41] | 54 | |
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[94] | 55 | vhdl->set_body (0,"RegisterFile_write: process (in_CLOCK)"); |
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| 56 | vhdl->set_body (0,"begin -- process RegisterFile_write"); |
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| 57 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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[101] | 58 | |
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| 59 | if (_param->_have_init_value) |
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| 60 | { |
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| 61 | vhdl->set_body (2,"if in_NRESET = '0' then"); |
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| 62 | |
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| 63 | std::string init_value = ((_param->_size_word>1)?"\"":"'")+_param->_init_value+((_param->_size_word>1)?"\"":"'"); |
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| 64 | |
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| 65 | for (uint32_t i=0; i<_param->_nb_word; ++i) |
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| 66 | vhdl->set_body (3,"reg_DATA("+toString(i)+") <= "+init_value+";"); |
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| 67 | |
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| 68 | vhdl->set_body (2,"else"); |
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| 69 | } |
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[2] | 70 | |
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[55] | 71 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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[2] | 72 | { |
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[75] | 73 | std::string str_address; |
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[62] | 74 | if (_param->_have_port_address) |
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| 75 | str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)"; |
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| 76 | else |
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| 77 | str_address = "0"; |
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| 78 | |
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[94] | 79 | vhdl->set_body (2,"if (in_WRITE_"+toString(i)+"_VAL = '1') then"); |
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| 80 | vhdl->set_body (3,"reg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;"); |
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| 81 | vhdl->set_body (2,"end if;"); |
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[2] | 82 | } |
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| 83 | |
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[94] | 84 | vhdl->set_body (1,"end if;"); |
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[101] | 85 | |
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| 86 | if (_param->_have_init_value) |
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| 87 | vhdl->set_body (1,"end if;"); |
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[145] | 88 | vhdl->set_body (0,"end process RegisterFile_write;"); |
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[101] | 89 | |
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[145] | 90 | #else |
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| 91 | // vhdl->set_body (0,""); |
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| 92 | // vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 93 | // vhdl->set_comment(0," Ackitement"); |
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| 94 | // vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 95 | // vhdl->set_body (0,""); |
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| 96 | |
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| 97 | // for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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| 98 | // vhdl->set_body (0,"out_READ_"+toString(i)+"_ACK <= '1';"); |
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| 99 | // for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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| 100 | // vhdl->set_body (0,"out_WRITE_"+toString(i)+"_ACK <= '1';"); |
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| 101 | |
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| 102 | // vhdl->set_body (0,""); |
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| 103 | // vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 104 | // vhdl->set_comment(0," Read RegisterFile"); |
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| 105 | // vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 106 | // vhdl->set_body (0,""); |
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| 107 | |
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| 108 | // for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read) |
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| 109 | // { |
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| 110 | // vhdl->set_body (0,"with in_READ_"+toString(num_read)+"_ADDRESS select"); |
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| 111 | // vhdl->set_body (1,"out_READ_"+toString(num_read)+"_DATA <="); |
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| 112 | // for (uint32_t num_word=0; num_word<_param->_nb_word-1; ++num_word) |
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| 113 | // vhdl->set_body (1,"reg_DATA_"+toString(num_word)+" when "+std_logic_cst(_param->_size_address,num_word)+","); |
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| 114 | // vhdl->set_body (1,"reg_DATA_"+toString(_param->_nb_word-1)+" when others;"); |
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| 115 | // } |
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| 116 | |
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| 117 | // vhdl->set_body (0,""); |
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| 118 | // vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 119 | // vhdl->set_comment(0," Write RegisterFile"); |
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| 120 | // vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 121 | // vhdl->set_body (0,""); |
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| 122 | |
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| 123 | // vhdl->set_body (0,"RegisterFile_write: process (in_CLOCK)"); |
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| 124 | // vhdl->set_body (0,"begin -- process RegisterFile_write"); |
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| 125 | // vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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| 126 | |
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| 127 | // for (uint32_t num_write = 0; num_write < _param->_nb_port_write; num_write++) |
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| 128 | // { |
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| 129 | // vhdl->set_body (2,"if (in_WRITE_"+toString(num_write)+"_VAL = '1') then"); |
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| 130 | // for (uint32_t num_word=0; num_word<_param->_nb_word; ++num_word) |
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| 131 | // { |
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| 132 | // vhdl->set_body (3,"if (in_WRITE_"+toString(num_write)+"_ADDRESS = "+std_logic_cst(_param->_size_address,num_word)+") then"); |
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| 133 | // vhdl->set_body (4,"reg_DATA_"+toString(num_word)+" <= in_WRITE_"+toString(num_write)+"_DATA;"); |
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| 134 | // vhdl->set_body (3,"end if;"); |
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| 135 | // } |
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| 136 | // vhdl->set_body (2,"end if;"); |
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| 137 | // } |
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| 138 | |
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| 139 | // vhdl->set_body (1,"end if;"); |
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| 140 | // vhdl->set_body (0,"end process RegisterFile_write;"); |
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| 141 | |
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| 142 | vhdl->set_body (0,"combinatory : process ("); |
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| 143 | for (uint32_t num_read=0; num_read<_param->_nb_port_read; ++num_read) |
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| 144 | { |
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| 145 | vhdl->set_body (1,"in_READ_"+toString(num_read)+"_VAL,"); |
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| 146 | if (_param->_have_port_address) |
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| 147 | vhdl->set_body (1,"in_READ_"+toString(num_read)+"_ADDRESS,"); |
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| 148 | } |
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| 149 | for (uint32_t num_write=0; num_write<_param->_nb_port_write; ++num_write) |
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| 150 | { |
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| 151 | vhdl->set_body (1,"in_WRITE_"+toString(num_write)+"_VAL,"); |
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| 152 | if (_param->_have_port_address) |
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| 153 | vhdl->set_body (1,"in_WRITE_"+toString(num_write)+"_ADDRESS,"); |
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| 154 | vhdl->set_body (1,"in_WRITE_"+toString(num_write)+"_DATA,"); |
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| 155 | } |
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| 156 | for (uint32_t num_write = 0; num_write < _param->_nb_port_write; num_write++) |
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| 157 | vhdl->set_body (1,"in_NRESET,"); |
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| 158 | vhdl->set_body (1,"reg_DATA)"); |
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| 159 | vhdl->set_body (1,"variable sig_DATA : Treg;"); |
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| 160 | vhdl->set_body (0,"begin"); |
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| 161 | vhdl->set_body (1,""); |
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| 162 | vhdl->set_body (1,"sig_DATA := reg_DATA;"); |
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| 163 | |
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| 164 | vhdl->set_body (1,""); |
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| 165 | vhdl->set_body (1," -- ack"); |
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| 166 | vhdl->set_body (1,""); |
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| 167 | |
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| 168 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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| 169 | vhdl->set_body (1,"out_READ_"+toString(i)+"_ACK <= '1';"); |
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| 170 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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| 171 | vhdl->set_body (1,"out_WRITE_"+toString(i)+"_ACK <= '1';"); |
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| 172 | vhdl->set_body (1,""); |
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| 173 | vhdl->set_body (1," -- Read"); |
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| 174 | vhdl->set_body (1,""); |
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| 175 | |
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| 176 | for (uint32_t i = 0; i < _param->_nb_port_read; i++) |
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| 177 | { |
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| 178 | std::string str_address; |
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| 179 | if (_param->_have_port_address) |
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| 180 | str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)"; |
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| 181 | else |
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| 182 | str_address = "0"; |
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| 183 | |
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| 184 | vhdl->set_body (1,"if (in_READ_"+toString(i)+"_VAL = '1') then"), |
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| 185 | vhdl->set_body (2,"out_READ_"+toString(i)+"_DATA <= sig_DATA.reg ("+str_address+");"); |
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| 186 | vhdl->set_body (1,"else"), |
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| 187 | vhdl->set_body (2,"out_READ_"+toString(i)+"_DATA <= "+std_logic_others(_param->_size_word,0)+";"); |
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| 188 | vhdl->set_body (1,"end if;"); |
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| 189 | } |
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| 190 | vhdl->set_body (1,""); |
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| 191 | vhdl->set_body (1," -- write"); |
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| 192 | vhdl->set_body (1,""); |
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| 193 | |
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| 194 | for (uint32_t i = 0; i < _param->_nb_port_write; i++) |
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| 195 | { |
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| 196 | std::string str_address; |
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| 197 | if (_param->_have_port_address) |
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| 198 | str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)"; |
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| 199 | else |
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| 200 | str_address = "0"; |
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| 201 | |
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| 202 | vhdl->set_body (1,"if (in_WRITE_"+toString(i)+"_VAL = '1') then"); |
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| 203 | vhdl->set_body (2,"sig_DATA.reg("+str_address+") := in_WRITE_"+toString(i)+"_DATA;"); |
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| 204 | vhdl->set_body (1,"end if;"); |
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| 205 | } |
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| 206 | |
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| 207 | vhdl->set_body (1,""); |
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| 208 | vhdl->set_body (1,"reg_DATA_next <= sig_DATA;"); |
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| 209 | vhdl->set_body (1,""); |
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| 210 | vhdl->set_body (0,"end process combinatory;"); |
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| 211 | |
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| 212 | |
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| 213 | vhdl->set_body (0,"sequential: process (in_CLOCK)"); |
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| 214 | vhdl->set_body (0,"begin"); |
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| 215 | vhdl->set_body (1,"if rising_edge(in_CLOCK) then"); |
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| 216 | vhdl->set_body (2,"reg_DATA <= reg_DATA_NEXT;"); |
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| 217 | vhdl->set_body (1,"end if;"); |
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| 218 | vhdl->set_body (0,"end process sequential;"); |
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| 219 | |
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| 220 | #endif |
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| 221 | |
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[2] | 222 | }; |
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| 223 | |
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[15] | 224 | }; // end namespace registerfile_monolithic |
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[2] | 225 | }; // end namespace registerfile |
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| 226 | }; // end namespace generic |
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| 227 | }; // end namespace behavioural |
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| 228 | }; // end namespace morpheo |
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| 229 | #endif |
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