Changeset 62 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp

Timestamp:

Dec 4, 2007, 2:31:54 PM (17 years ago)

Author:

rosiere

Message:

Modification en profondeur de Component-port_map.
Compilation ok pour Register_unit ... a tester (systemC et vhdl)

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp

@@ -37 +37 @@
     
     for (uint32_t i = 0; i < _param->_nb_port_read; i++)
-        vhdl->set_body ("out_READ_"+toString(i)+"_DATA <= reg_DATA (conv_integer(in_READ_"+toString(i)+"_ADDRESS)) when in_READ_"+toString(i)+"_VAL = '1' else "+std_logic_others(_param->_size_word,0)+";");
+      {
+        string str_address;
+        if (_param->_have_port_address)
+          str_address = "conv_integer(in_READ_"+toString(i)+"_ADDRESS)";
+        else
+          str_address = "0";
 
+        vhdl->set_body ("out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+") when in_READ_"+toString(i)+"_VAL = '1' else "+std_logic_others(_param->_size_word,0)+";");
+      }
     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
-      vhdl->set_body ("out_READ_WRITE_"+toString(i)+"_RDATA <= reg_DATA (conv_integer(in_READ_WRITE_"+toString(i)+"_ADDRESS)) when in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_READ)+"' else "+std_logic_others(_param->_size_word,0)+";");
+      {
+        string str_address;
+        if (_param->_have_port_address)
+          str_address = "conv_integer(in_READ_WRITE_"+toString(i)+"_ADDRESS)";
+        else
+          str_address = "0";
+        vhdl->set_body ("out_READ_WRITE_"+toString(i)+"_RDATA <= reg_DATA ("+str_address+") when in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_READ)+"' else "+std_logic_others(_param->_size_word,0)+";");
+      }
 
     vhdl->set_body ("");
@@ -54 +68 @@
     for (uint32_t i = 0; i < _param->_nb_port_write; i++)
       {
-      vhdl->set_body ("\t\tif (in_WRITE_"+toString(i)+"_VAL = '1') then");
-      vhdl->set_body ("\t\t\treg_DATA(conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)) <= in_WRITE_"+toString(i)+"_DATA;");
-      vhdl->set_body ("\t\tend if;");
+        string str_address;
+        if (_param->_have_port_address)
+          str_address = "conv_integer(in_WRITE_"+toString(i)+"_ADDRESS)";
+        else
+          str_address = "0";
+
+        vhdl->set_body ("\t\tif (in_WRITE_"+toString(i)+"_VAL = '1') then");
+        vhdl->set_body ("\t\t\treg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;");
+        vhdl->set_body ("\t\tend if;");
       }
     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
       {
-      vhdl->set_body ("\t\tif (in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_WRITE)+"') then");
-      vhdl->set_body ("\t\t\treg_DATA(conv_integer(in_READ_WRITE_"+toString(i)+"_ADDRESS)) <= in_READ_WRITE_"+toString(i)+"_WDATA;");
-      vhdl->set_body ("\t\tend if;");
+        string str_address;
+        if (_param->_have_port_address)
+          str_address = "conv_integer(in_READ_WRITE_"+toString(i)+"_ADDRESS)";
+        else
+          str_address = "0";
+        
+        vhdl->set_body ("\t\tif (in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_WRITE)+"') then");
+        vhdl->set_body ("\t\t\treg_DATA("+str_address+") <= in_READ_WRITE_"+toString(i)+"_WDATA;");
+        vhdl->set_body ("\t\tend if;");
       }