[2] | 1 | # |
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| 2 | # $Id$ |
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| 3 | # |
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| 4 | # [ Description ] |
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| 5 | # |
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| 6 | # Makefile |
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| 7 | # |
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| 8 | |
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| 9 | #-----[ Variables ]---------------------------------------- |
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| 10 | |
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| 11 | DIR_VHDL = . |
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| 12 | DIR_WORK = work |
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| 13 | |
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| 14 | FPGA_CFG_FILE_LOCAL = mkf.info |
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| 15 | FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural |
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| 16 | FPGA_CFG_FILE_GLOBAL = configure.mkf |
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| 17 | |
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[19] | 18 | FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 19 | $(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| 20 | |
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| 21 | FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 22 | $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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[2] | 23 | #-----[ Rules ]-------------------------------------------- |
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| 24 | .PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.vhdl_sim.log |
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| 25 | |
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| 26 | vhdl : execute $(DIR_WORK) |
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[15] | 27 | @ \ |
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| 28 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \ |
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[2] | 29 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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[15] | 30 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi |
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| 31 | @ \ |
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| 32 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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[2] | 33 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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[15] | 34 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi |
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| 35 | @ \ |
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| 36 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ |
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[2] | 37 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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[15] | 38 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi |
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[2] | 39 | |
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| 40 | vhdl_sim : vhdl |
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[15] | 41 | @ \ |
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| 42 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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[2] | 43 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl_sim.log}); \ |
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[15] | 44 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi |
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[2] | 45 | |
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| 46 | fpga : vhdl_sim |
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| 47 | @$(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL) |
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[19] | 48 | @$(ECHO) "files :::::::: $(FPGA_FILES)" |
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| 49 | @for file in $(FPGA_FILES); do \ |
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[2] | 50 | declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)")); \ |
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| 51 | $(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 52 | $(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 53 | $(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 54 | $(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 55 | $(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 56 | done |
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[15] | 57 | @($(XILINX_ENV); $(CD) $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)) |
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[19] | 58 | @$(MAKE) $(FPGA_LOG_FILES) |
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[2] | 59 | |
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| 60 | $(DIR_LOG)/%.fpga.log : |
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| 61 | @$(ECHO) "Synthetis on FPGA : $*" |
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[15] | 62 | @$(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc > $@ |
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[2] | 63 | |
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| 64 | $(DIR_WORK) : |
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| 65 | @$(ECHO) "Create work-space : $@" |
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[15] | 66 | @$(MODELTECH_VLIB) $@ |
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[2] | 67 | |
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| 68 | $(DIR_LOG)/%.vhdl_sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log |
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[3] | 69 | @$(ECHO) "VHDL's Simulation: $*" |
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[15] | 70 | @$(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" > $@ |
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[2] | 71 | declare -i count=`$(GREP) -ch "Test KO" $@`; \ |
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| 72 | if $(TEST) $$count -eq 0; \ |
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| 73 | then echo " $* ... OK"; \ |
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| 74 | else echo " $* ... KO"; exit 1; \ |
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| 75 | fi; |
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| 76 | |
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| 77 | $(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl |
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| 78 | @$(ECHO) "VHDL's Compilation : $*" |
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[15] | 79 | @$(MODELTECH_VCOM) $< > $@ |
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[2] | 80 | |
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| 81 | synthesis_clean : |
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| 82 | @if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi |
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| 83 | @$(RM) $(DIR_WORK) transcript Makefile.mkf |
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| 84 | |
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| 85 | synthesis_help : |
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| 86 | @$(ECHO) " -----[ Synthesis ]----------------------------------" |
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| 87 | @$(ECHO) "" |
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| 88 | @$(ECHO) " * vhdl : compile all vhdl's file" |
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| 89 | @$(ECHO) " * vhdl_sim : simulate all testbench's file" |
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| 90 | @$(ECHO) " * fpga : synthetis with fpga's tools" |
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| 91 | @$(ECHO) "" |
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