Changeset 100 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit
- Timestamp:
- Jan 8, 2009, 2:06:27 PM (15 years ago)
- Location:
- trunk
- Files:
-
- 12 edited
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- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/config_mono_context.cfg
r82 r100 3 3 1 1 *4 # nb_decod_unit 4 4 30 30 +32 # size_address 5 1 1 *4# nb_instruction [0] [nb_context]5 1 4 *2 # nb_instruction [0] [nb_context] 6 6 1 1 *4 # size_depth [0] [nb_context] 7 7 4 4 *4 # nb_inst_decod [0] [nb_decod_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp
r88 r100 362 362 363 363 // Initialisation 364 const bool test1 = false; 365 const bool test2 = true ; 366 const bool test3 = false; 367 const bool test4 = false; 364 368 365 369 const uint32_t seed = 0; … … 402 406 LABEL("Iteration %d",iteration); 403 407 408 if (test1) 404 409 { 405 410 LABEL("Test sequential"); … … 481 486 } 482 487 488 if (test2) 483 489 { 484 490 LABEL("Test no sequential - L.J"); … … 489 495 for (uint32_t i=0; i<_param->_nb_instruction [context]; i++) 490 496 { 491 Taddress_t addr = (1<<(_param->_nb_instruction[context]+4)); 492 Taddress_t addr_src = addr+i; 497 Taddress_t pc_current = (1<<(_param->_nb_instruction[context]+3)); 498 Taddress_t pc_previous = pc_current-1; 499 Taddress_t addr_src = pc_current+i; 493 500 Taddress_t addr_dest = 0xdeadbeef; 494 495 in_PREDICT_PC_PREVIOUS [context]->write(0); 496 in_PREDICT_PC_CURRENT [context]->write(addr); 497 in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]->write(0); 501 Tcontrol_t is_ds_take= rand()%2; 502 503 in_PREDICT_PC_PREVIOUS [context]->write(pc_previous); 504 in_PREDICT_PC_CURRENT [context]->write(pc_current); 505 in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]->write(is_ds_take); 498 506 499 507 bool find = false; … … 515 523 LABEL(" * BTB address : 0x%x",out_PREDICT_BTB_ADDRESS [port]->read()); 516 524 if ((out_PREDICT_BTB_CONTEXT_ID [port]->read() == context) and 517 (out_PREDICT_BTB_ADDRESS [port]->read() == addr))525 (out_PREDICT_BTB_ADDRESS [port]->read() == (is_ds_take)?pc_previous:pc_current )) 518 526 { 519 527 in_PREDICT_BTB_ACK [port]->write((rand()%100)<percent_transaction_predict); … … 531 539 SC_START(0); 532 540 541 LABEL ("PREDICT_VAL : %d", in_PREDICT_VAL[context]->read()); 542 LABEL ("PREDICT_ACK : %d",out_PREDICT_ACK[context]->read()); 543 533 544 if (in_PREDICT_VAL[context]->read() and out_PREDICT_ACK[context]->read()) 534 545 { 535 546 LABEL ("PREDICT [%d] - Transaction accepted",context); 547 LABEL (" * pc_previous: 0x%x",pc_previous ); 548 LABEL (" * pc_current : 0x%x",pc_current ); 549 LABEL (" * addr_src : 0x%x",addr_src ); 550 LABEL (" * addr_dest : 0x%x",addr_dest ); 551 LABEL (" * is_ds_take : %d" ,is_ds_take); 552 536 553 find = true; 537 538 TEST(Taddress_t ,out_PREDICT_PC_NEXT [context]->read(),addr_dest); 539 TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [context]->read(),i==(_param->_nb_instruction [context]-1)); 554 555 Tcontrol_t next_is_ds_take = (not is_ds_take and (i==(_param->_nb_instruction [context]-1))); 556 557 TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [context]->read(), next_is_ds_take); 558 TEST(Taddress_t ,out_PREDICT_PC_NEXT [context]->read(),(next_is_ds_take)?(addr_src+1):addr_dest); 540 559 TEST(Tinst_ifetch_ptr_t,out_PREDICT_INST_IFETCH_PTR [context]->read(),i); 541 TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [context]->read(),BRANCH_STATE_NSPEC_TAKE);560 TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [context]->read(),(next_is_ds_take)?BRANCH_STATE_NONE:BRANCH_STATE_NSPEC_TAKE); 542 561 // TEST(Tprediction_ptr_t ,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context]->read(),0); 543 562 544 uint32_t k=((addr_src%_param->_nb_instruction[context])==_param->_nb_instruction[context]-1)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction[context])+2); 563 uint32_t k=((is_ds_take)?1:((next_is_ds_take)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction [context])+2))); 564 565 566 // ((addr_src%_param->_nb_instruction[context])==_param->_nb_instruction[context]-1)?_param->_nb_instruction[context]:((addr_src%_param->_nb_instruction[context])+2); 567 545 568 LABEL("instruction enable : "); 546 569 LABEL(" [0:%d[ = 1",k); 547 LABEL(" [%d:%d[ = 1",k,_param->_nb_instruction[context]);570 LABEL(" [%d:%d[ = 0",k,_param->_nb_instruction[context]); 548 571 for (uint32_t j=0; j<k; j++) 549 572 TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),1); 550 573 for (uint32_t j=k; j<_param->_nb_instruction[context]; j++) 551 574 TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [context][j]->read(),0); 552 575 553 576 TEST(Tcontrol_t ,out_PREDICT_BTB_VAL [port]->read(),1); 554 577 TEST(Tcontext_t ,out_PREDICT_BTB_CONTEXT_ID [port]->read(),context); 555 TEST(Taddress_t ,out_PREDICT_BTB_ADDRESS [port]->read(), addr);578 TEST(Taddress_t ,out_PREDICT_BTB_ADDRESS [port]->read(),(is_ds_take)?pc_previous:pc_current); 556 579 } 557 580 … … 571 594 } 572 595 } 573 596 597 if (test3) 574 598 { 575 599 LABEL("Decod - Ok"); … … 618 642 } 619 643 644 if (test4) 620 645 { 621 646 LABEL("Decod - Ko"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
r98 r100 27 27 if (PORT_READ(in_NRESET)) 28 28 { 29 30 29 // Init 31 30 Tcontrol_t ack [_param->_nb_context]; … … 36 35 { 37 36 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); 38 37 38 // No access 39 39 Tcontrol_t btb_val = false; 40 40 Tcontrol_t dir_val = false; … … 42 42 Tcontrol_t upt_val = false; 43 43 44 // Get ack 44 45 Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); 45 46 Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); … … 47 48 Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); 48 49 50 // Read context_id 49 51 Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority 50 52 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); 51 53 54 // Now : ack transaction 52 55 ack [context] = 1; 53 56 54 57 if (PORT_READ(in_PREDICT_VAL[context]) == 0) 55 58 { 59 // Nothing 56 60 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); 57 61 … … 63 67 else 64 68 { 69 // Have transaction 65 70 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); 66 71 72 // Read information (PC) 67 73 Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); 68 74 Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); 69 75 Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); 70 76 71 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x ",pc_previous);72 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x ",pc_current);77 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x (0x%.8x)",pc_previous,pc_previous<<2); 78 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x (0x%.8x)",pc_current ,pc_current <<2); 73 79 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); 74 80 … … 80 86 81 87 // STEP (1) - Compute the address source 82 // if pc_current is a ds take, then pc_previous is a branchement 88 // -> if pc_current is a ds take, then pc_previous is a branchement 89 // get branchement address to send at the BTB 83 90 Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; 91 // Address_lsb = position in fetch packet 84 92 Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 85 93 Taddress_t address_msb; 86 94 87 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x ",address);95 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x (0x%.8x)",address,address<<2); 88 96 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); 89 97 90 98 // STEP (2) - Test if branch (access at branch_target_buffer) 99 // Access at the btb 91 100 btb_val = true; 92 101 102 // Create the request 93 103 if (_param->_have_port_context_id) 94 104 PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); 95 105 PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); 96 106 107 // Transaction can be ack if btb is not busy 97 108 ack [context] &= btb_ack; 98 109 99 110 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); 100 111 101 // BTB_ack = 0 ? 112 // BTB_ack = 0 ? else can continue 102 113 if (not btb_ack) 103 114 continue; 104 115 105 // special case :106 // if pc_current _is_ds, then pc_previous have branch, also hit must be set.107 // else : a another branchhave eject this branch : can't accurate116 // Test a special case : 117 // if pc_current is a delay slot, then pc_previous is a branchement instruction, also hit must be set. 118 // else : an another branch instruction have eject this branch : can't accurate 108 119 Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); 109 120 Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); … … 112 123 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); 113 124 114 // STEP (3) : Test if have branchin the packet125 // STEP (3) : Test if BTB find a branch instruction in the packet 115 126 if (hit == 1) 116 127 { 128 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB hit : no sequential order"); 129 117 130 // STEP (3a) : branch - test condition 118 131 bool use_dir = false; 119 132 bool use_ras = false; 120 133 bool use_upt = false; 121 122 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 123 Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 124 Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 125 Tcontrol_t push ; 126 Tcontrol_t direction; 127 128 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); 129 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x",address_src); 130 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x",address_dest); 131 132 switch (condition) 133 { 134 case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j 135 { 136 // use none unit (dir, upt and ras) 137 direction = true; 138 pc_next = address_dest; 139 branch_state = BRANCH_STATE_NSPEC_TAKE; 140 break; 141 } 142 case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal 143 { 144 use_upt = true; 145 use_ras = true; 146 push = true; 147 direction = true; 148 pc_next = address_dest; 149 branch_state = BRANCH_STATE_NSPEC_TAKE; 150 break; 151 } 152 case BRANCH_CONDITION_FLAG_UNSET : // l.bnf 153 case BRANCH_CONDITION_FLAG_SET : // l.bf 154 { 155 use_upt = true; 156 use_dir = true; 157 // Test direction 158 direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same 159 if (direction = 1) 160 { 161 branch_state = BRANCH_STATE_SPEC_TAKE; 162 pc_next = address_dest; 163 } 164 else 165 { 166 branch_state = BRANCH_STATE_SPEC_NTAKE; 167 pc_next = address_src+2; // +1 = delay slot 168 } 169 break; 170 } 171 case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) 172 { 173 use_upt = true; 174 use_ras = true; 175 push = true; 176 direction = true; 177 pc_next = address_dest; 178 branch_state = BRANCH_STATE_SPEC_TAKE; 179 break; 180 } 181 case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr 182 { 183 use_upt = true; 184 use_ras = true; 185 push = true; 186 direction = true; 187 pc_next = address_dest; 188 branch_state = BRANCH_STATE_NSPEC_TAKE; 189 break; 190 } 191 case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) 192 { 193 use_upt = true; 194 use_ras = true; 195 push = false; 196 direction = true; 197 pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); 198 branch_state = BRANCH_STATE_SPEC_TAKE; 199 break; 200 } 201 default : 202 { 203 ERRORMORPHEO(FUNCTION,"Unknow Condition"); 204 break; 205 } 206 } 207 208 if (use_dir) 209 { 210 ack[context] &= dir_ack; 211 PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); 212 PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take 213 // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); 214 } 215 216 if (use_ras) 217 { 218 ack[context] &= ras_ack; 219 if (_param->_have_port_context_id) 220 PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); 221 PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); 222 PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 223 224 is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate 225 } 226 227 if (use_upt) 228 { 229 ack[context] &= upt_ack; 230 231 if (_param->_have_port_context_id) 232 PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); 233 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); 234 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); 235 PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); 236 PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); 237 PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); 238 // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); 239 PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); 240 // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); 241 } 242 243 // ack = 1 if : 244 // * btb_ack 245 // * use_dir and dir_ack 246 // * use_ras and ras_ack 247 // * use_upt and upt_ack 248 // ack [context] = (btb_ack and 249 // (use_dir and dir_ack) and 250 // (use_ras and ras_ack) and 251 // (use_upt and upt_ack)); 252 253 dir_val = (btb_ack and 254 use_dir and 255 // use_ras and 256 // use_upt and 257 // (not use_dir or (use_dir and dir_ack)) and 258 (not use_ras or (use_ras and ras_ack)) and 259 (not use_upt or (use_upt and upt_ack))); 260 261 ras_val = (btb_ack and 262 // use_dir and 263 use_ras and 264 // use_upt and 265 (not use_dir or (use_dir and dir_ack)) and 266 // (not use_ras or (use_ras and ras_ack)) and 267 (not use_upt or (use_upt and upt_ack))); 268 269 upt_val = (btb_ack and 270 // use_dir and 271 // use_ras and 272 use_upt and 273 (not use_dir or (use_dir and dir_ack)) and 274 (not use_ras or (use_ras and ras_ack))// and 275 // (not use_upt or (use_upt and upt_ack)) 276 ); 277 278 // pc_next - is previously computed 279 // branch_state - is previously computed 280 281 Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; 282 283 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); 134 135 Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 136 Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; 137 138 inst_ifetch_ptr = address_src_lsb; 139 140 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src,address_src<<2); 284 141 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); 285 142 286 if (address_src_lsb == (_param->_nb_instruction [context]-1)) 143 // Special case : 144 // * BTB hit and the branchement is the PC current and it's the last slot. 145 // -> next pc must be the delay slot 146 if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alors pc_next is the destination of branchement 147 (address_src_lsb == (_param->_nb_instruction [context]-1))) 287 148 { 288 149 // branch is in the last slot of the packet 289 150 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); 290 151 152 // Branch is the last slot : next paquet is the delay slot 153 pc_next = address_src+1; // sequencial 154 pc_next_is_ds_take = 1; 291 155 address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) 292 pc_next_is_ds_take = 1;156 branch_state = BRANCH_STATE_NONE; 293 157 } 294 158 else 295 159 { 160 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 161 Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 162 Tcontrol_t push ; 163 Tcontrol_t direction; 164 165 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); 166 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src ,address_src <<2); 167 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x (0x%.8x)",address_dest,address_dest<<2); 168 169 switch (condition) 170 { 171 case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j 172 { 173 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); 174 175 // use none unit (dir, upt and ras) 176 direction = true; 177 pc_next = address_dest; 178 branch_state = BRANCH_STATE_NSPEC_TAKE; 179 break; 180 } 181 case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal 182 { 183 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITH_WRITE_STACK"); 184 185 use_upt = true; 186 use_ras = true; 187 push = true; 188 direction = true; 189 pc_next = address_dest; 190 branch_state = BRANCH_STATE_NSPEC_TAKE; 191 break; 192 } 193 case BRANCH_CONDITION_FLAG_UNSET : // l.bnf 194 case BRANCH_CONDITION_FLAG_SET : // l.bf 195 { 196 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_FLAG"); 197 198 use_upt = true; 199 use_dir = true; 200 // Test direction 201 direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same 202 if (direction = 1) 203 { 204 branch_state = BRANCH_STATE_SPEC_TAKE; 205 pc_next = address_dest; 206 } 207 else 208 { 209 branch_state = BRANCH_STATE_SPEC_NTAKE; 210 pc_next = address_src+2; // +1 = delay slot 211 } 212 break; 213 } 214 case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) 215 { 216 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK"); 217 218 use_upt = true; 219 use_ras = true; 220 push = true; 221 direction = true; 222 pc_next = address_dest; 223 branch_state = BRANCH_STATE_SPEC_TAKE; 224 break; 225 } 226 case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr 227 { 228 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK"); 229 230 use_upt = true; 231 use_ras = true; 232 push = true; 233 direction = true; 234 pc_next = address_dest; 235 branch_state = BRANCH_STATE_NSPEC_TAKE; 236 break; 237 } 238 case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) 239 { 240 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_STACK"); 241 use_upt = true; 242 use_ras = true; 243 push = false; 244 direction = true; 245 pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); 246 branch_state = BRANCH_STATE_SPEC_TAKE; 247 break; 248 } 249 default : 250 { 251 ERRORMORPHEO(FUNCTION,"Unknow Condition"); 252 break; 253 } 254 } 255 256 if (use_dir) 257 { 258 ack[context] &= dir_ack; 259 PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); 260 PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take 261 // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); 262 } 263 264 if (use_ras) 265 { 266 ack[context] &= ras_ack; 267 if (_param->_have_port_context_id) 268 PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); 269 PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); 270 PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 271 272 is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate 273 } 274 275 if (use_upt) 276 { 277 ack[context] &= upt_ack; 278 279 if (_param->_have_port_context_id) 280 PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); 281 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); 282 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); 283 PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); 284 PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); 285 PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); 286 // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); 287 PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); 288 // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); 289 } 290 291 // ack = 1 if : 292 // * btb_ack 293 // * use_dir and dir_ack 294 // * use_ras and ras_ack 295 // * use_upt and upt_ack 296 // ack [context] = (btb_ack and 297 // (use_dir and dir_ack) and 298 // (use_ras and ras_ack) and 299 // (use_upt and upt_ack)); 300 301 dir_val = (btb_ack and 302 use_dir and 303 // use_ras and 304 // use_upt and 305 // (not use_dir or (use_dir and dir_ack)) and 306 (not use_ras or (use_ras and ras_ack)) and 307 (not use_upt or (use_upt and upt_ack))); 308 309 ras_val = (btb_ack and 310 // use_dir and 311 use_ras and 312 // use_upt and 313 (not use_dir or (use_dir and dir_ack)) and 314 // (not use_ras or (use_ras and ras_ack)) and 315 (not use_upt or (use_upt and upt_ack))); 316 317 upt_val = (btb_ack and 318 // use_dir and 319 // use_ras and 320 use_upt and 321 (not use_dir or (use_dir and dir_ack)) and 322 (not use_ras or (use_ras and ras_ack))// and 323 // (not use_upt or (use_upt and upt_ack)) 324 ); 325 326 // pc_next - is previously computed 327 // branch_state - is previously computed 328 329 296 330 // branch is in the last slot of the packet 297 331 address_msb = (address_src_lsb+2); // +1 == delayed slot 298 332 pc_next_is_ds_take = 0; 299 333 } 300 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); 301 302 inst_ifetch_ptr = address_src_lsb; 334 303 335 // branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0; 304 336 } … … 308 340 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); 309 341 310 pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial 342 // Take the address packet base and add new packet 343 pc_next = pc_current-address_lsb+_param->_nb_instruction [context]; // sequencial 311 344 pc_next_is_ds_take = 0; // no branch, also no delay slot 312 345 inst_ifetch_ptr = 0; … … 316 349 address_msb = _param->_nb_instruction [context]; 317 350 } 318 319 PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); 320 PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); 321 322 Taddress_t address_limit_min = address_lsb; 323 Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); 324 325 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); 326 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); 327 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); 328 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); 329 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); 330 331 for (uint32_t j=0; j<address_limit_min; j++) 332 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid 333 for (uint32_t j=address_limit_min; j<address_limit_max; j++) 334 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Vald packet 335 for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) 336 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid 337 if (_param->_have_port_inst_ifetch_ptr) 338 PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); 339 PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); 340 if (_param->_have_port_depth) 341 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); 351 352 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); 353 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next : 0x%.8x (0x%.8x)",pc_next,pc_next<<2); 354 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next_is_ds_take : %d" ,pc_next_is_ds_take); 355 356 // Write Output 357 PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); 358 PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); 359 360 // Create enable mask 361 Taddress_t address_limit_min = address_lsb; 362 Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); 363 364 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); 365 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); 366 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); 367 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); 368 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); 369 370 for (uint32_t j=0; j<address_limit_min; j++) 371 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid 372 for (uint32_t j=address_limit_min; j<address_limit_max; j++) 373 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Valid packet 374 for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) 375 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid 376 377 if (_param->_have_port_inst_ifetch_ptr) 378 PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); 379 PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); 380 if (_param->_have_port_depth) 381 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); 342 382 } 343 383 … … 348 388 PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); 349 389 } 350 390 391 // Write output 351 392 for (uint32_t i=0; i<_param->_nb_context; i++) 352 393 PORT_WRITE(out_PREDICT_ACK[i],ack[i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp
r95 r100 125 125 126 126 // Initialisation 127 127 const bool test1 = true; 128 const bool test2 = true; 129 const bool test3 = true; 130 const bool test4 = true; 131 128 132 const uint32_t seed = 0; 129 133 //const uint32_t seed = static_cast<uint32_t>(time(NULL)); … … 144 148 { 145 149 LABEL("Iteration %d",iteration); 146 147 if ( 1)150 151 if (test1) 148 152 { 149 uint32_t port = rand()%_param->_nb_inst_predict; 150 151 LABEL("PREDICT - PUSH"); 153 uint32_t port = rand()%_param->_nb_inst_predict; 154 155 LABEL("PREDICT - PUSH"); 156 157 in_PREDICT_VAL [port]->write(1); 158 in_PREDICT_PUSH [port]->write(1); 159 160 for (uint32_t i=0; i<_param->_nb_context; i++) 161 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 162 { 163 in_PREDICT_CONTEXT_ID [port]->write(i); 164 in_PREDICT_ADDRESS_PUSH [port]->write(0xdeadbeef+j); 165 166 SC_START(0); 167 168 TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); 169 TEST(Tptr_t , out_PREDICT_INDEX[port]->read(),(j+1)%_param->_size_queue[i]); 170 171 SC_START(1); 172 173 } 174 in_PREDICT_VAL [port]->write(0); 175 176 SC_START(1); 177 178 in_PREDICT_VAL [port]->write(1); 179 in_PREDICT_PUSH [port]->write(1); 180 for (uint32_t i=0; i<_param->_nb_context; i++) 181 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 182 { 183 in_PREDICT_CONTEXT_ID [port]->write(i); 184 in_PREDICT_ADDRESS_PUSH [port]->write(0x21071981+j); 185 186 SC_START(0); 187 188 TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); 189 TEST(Tptr_t , out_PREDICT_INDEX [port]->read(),(j+1)%_param->_size_queue[i]); 190 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),0xdeadbeef+j); 191 192 SC_START(1); 193 } 194 in_PREDICT_VAL [port]->write(0); 195 196 LABEL("PREDICT - POP"); 197 198 in_PREDICT_VAL [port]->write(1); 199 in_PREDICT_PUSH [port]->write(0); 200 for (uint32_t i=0; i<_param->_nb_context; i++) 201 for (uint32_t j=0; j< _param->_size_queue[i]; j++) 202 { 203 in_PREDICT_CONTEXT_ID [port]->write(i); 204 in_PREDICT_ADDRESS_PUSH [port]->write(0xbabedead); 205 206 SC_START(0); 207 208 TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); 209 TEST(Tcontrol_t, out_PREDICT_HIT [port]->read(), 1); 210 uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; 211 TEST(Tptr_t , out_PREDICT_INDEX [port]->read(), k); 212 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); 213 214 SC_START(1); 215 } 216 in_PREDICT_VAL [port]->write(0); 217 218 // Now, the stack is empty 219 } 220 221 if (test2) 222 { 223 uint32_t port = rand()%_param->_nb_inst_decod; 224 225 LABEL("DECOD - without predict"); 226 227 LABEL("DECOD - PUSH"); 228 229 in_DECOD_VAL [port]->write(1); 230 in_DECOD_PUSH [port]->write(1); 231 in_DECOD_MISS_PREDICTION [port]->write(0); 232 233 for (uint32_t i=0; i<_param->_nb_context; i++) 234 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 235 { 236 in_DECOD_CONTEXT_ID [port]->write(i); 237 in_DECOD_ADDRESS_PUSH [port]->write(0xbeefcaca+j); 238 239 SC_START(0); 240 241 TEST(Tcontrol_t, out_DECOD_ACK [port]->read(), 1); 242 TEST(Tptr_t , out_DECOD_INDEX[port]->read(),(j+1)%_param->_size_queue[i]); 243 244 SC_START(1); 245 246 } 247 in_DECOD_VAL [port]->write(0); 152 248 153 in_PREDICT_VAL [port]->write(1); 154 in_PREDICT_PUSH [port]->write(1); 155 for (uint32_t i=0; i<_param->_nb_context; i++) 156 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 157 { 158 in_PREDICT_CONTEXT_ID [port]->write(i); 159 in_PREDICT_ADDRESS_PUSH [port]->write(0xdeadbeef+j); 160 161 SC_START(0); 162 163 TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); 164 TEST(Tptr_t , out_PREDICT_INDEX[port]->read(),(j+1)%_param->_size_queue[i]); 165 166 SC_START(1); 167 168 } 169 in_PREDICT_VAL [port]->write(0); 170 171 SC_START(1); 172 173 in_PREDICT_VAL [port]->write(1); 174 in_PREDICT_PUSH [port]->write(1); 175 for (uint32_t i=0; i<_param->_nb_context; i++) 176 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 177 { 178 in_PREDICT_CONTEXT_ID [port]->write(i); 179 in_PREDICT_ADDRESS_PUSH [port]->write(0x21071981+j); 180 181 SC_START(0); 182 183 TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); 184 TEST(Tptr_t , out_PREDICT_INDEX [port]->read(),(j+1)%_param->_size_queue[i]); 185 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),0xdeadbeef+j); 186 187 SC_START(1); 188 } 189 in_PREDICT_VAL [port]->write(0); 190 191 LABEL("PREDICT - POP"); 192 193 in_PREDICT_VAL [port]->write(1); 194 in_PREDICT_PUSH [port]->write(0); 195 for (uint32_t i=0; i<_param->_nb_context; i++) 196 for (uint32_t j=0; j< _param->_size_queue[i]; j++) 197 { 198 in_PREDICT_CONTEXT_ID [port]->write(i); 199 in_PREDICT_ADDRESS_PUSH [port]->write(0xbabedead); 200 201 SC_START(0); 202 203 TEST(Tcontrol_t, out_PREDICT_ACK [port]->read(), 1); 204 TEST(Tcontrol_t, out_PREDICT_HIT [port]->read(), 1); 205 uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; 206 TEST(Tptr_t , out_PREDICT_INDEX [port]->read(), k); 207 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); 208 209 SC_START(1); 210 } 211 in_PREDICT_VAL [port]->write(0); 212 } 213 214 // Now, the stack is empty 215 216 if (1) 217 { 218 uint32_t port1 = rand()%_param->_nb_inst_decod; 219 uint32_t port2 = rand()%_param->_nb_inst_predict; 220 221 LABEL("DECOD - without predict"); 222 223 LABEL("DECOD - PUSH"); 224 225 in_DECOD_VAL [port1]->write(1); 226 in_DECOD_PUSH [port1]->write(1); 227 in_DECOD_MISS_PREDICTION [port1]->write(0); 228 229 for (uint32_t i=0; i<_param->_nb_context; i++) 230 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 231 { 232 in_DECOD_CONTEXT_ID [port1]->write(i); 233 in_DECOD_ADDRESS_PUSH [port1]->write(0xbeefcaca+j); 234 235 SC_START(0); 236 237 TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); 238 TEST(Tptr_t , out_DECOD_INDEX[port1]->read(),(j+1)%_param->_size_queue[i]); 239 240 SC_START(1); 241 242 } 243 in_DECOD_VAL [port1]->write(0); 244 245 SC_START(1); 246 247 in_DECOD_VAL [port1]->write(1); 248 in_DECOD_PUSH [port1]->write(1); 249 for (uint32_t i=0; i<_param->_nb_context; i++) 250 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 251 { 252 in_DECOD_CONTEXT_ID [port1]->write(i); 253 in_DECOD_ADDRESS_PUSH [port1]->write(0x21071981+j); 254 255 SC_START(0); 256 257 TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); 258 TEST(Tptr_t , out_DECOD_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); 259 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),0xbeefcaca+j); 260 261 SC_START(1); 262 } 263 in_DECOD_VAL [port1]->write(0); 264 265 LABEL("DECOD - POP"); 266 267 in_DECOD_VAL [port1]->write(1); 268 in_DECOD_PUSH [port1]->write(0); 269 for (uint32_t i=0; i<_param->_nb_context; i++) 270 for (uint32_t j=0; j< _param->_size_queue[i]; j++) 271 { 272 in_DECOD_CONTEXT_ID [port1]->write(i); 273 in_DECOD_ADDRESS_PUSH [port1]->write(0xbabedead); 274 275 SC_START(0); 276 277 TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); 278 TEST(Tcontrol_t, out_DECOD_HIT [port1]->read(), 1); 279 uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; 280 TEST(Tptr_t , out_DECOD_INDEX [port1]->read(), k); 281 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); 282 283 SC_START(1); 284 } 285 in_DECOD_VAL [port1]->write(0); 286 287 LABEL("DECOD - with predict"); 288 289 LABEL("DECOD - PUSH (size_queue/2)"); 290 291 in_DECOD_VAL [port1]->write(1); 292 in_DECOD_PUSH [port1]->write(1); 293 in_DECOD_MISS_PREDICTION [port1]->write(1); 294 295 for (uint32_t i=0; i<_param->_nb_context; i++) 296 for (uint32_t j=0; j<_param->_size_queue[i]/2;j++) 297 { 298 in_DECOD_CONTEXT_ID [port1]->write(i); 299 in_DECOD_ADDRESS_PUSH [port1]->write(0x01234567+j); 300 301 SC_START(0); 302 303 TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); 304 TEST(Tptr_t , out_DECOD_INDEX[port1]->read(),(j+1)%_param->_size_queue[i]); 305 306 SC_START(1); 307 308 } 309 in_DECOD_VAL [port1]->write(0); 310 311 LABEL("PREDICT - PUSH (size_queue/2)"); 312 313 in_PREDICT_VAL [port2]->write(1); 314 in_PREDICT_PUSH [port2]->write(1); 315 316 for (uint32_t i=0; i<_param->_nb_context; i++) 317 for (uint32_t j=0; j<_param->_size_queue[i]/2;j++) 318 { 319 in_PREDICT_CONTEXT_ID [port2]->write(i); 320 in_PREDICT_ADDRESS_PUSH [port2]->write((0x89abcdef+j)+(_param->_size_queue[i]/2)); 321 322 SC_START(0); 323 324 TEST(Tcontrol_t, out_PREDICT_ACK [port2]->read(), 1); 325 TEST(Tptr_t , out_PREDICT_INDEX[port2]->read(),(j+1+(_param->_size_queue[i]/2))%_param->_size_queue[i]); 326 327 SC_START(1); 328 } 329 330 in_PREDICT_VAL [port2]->write(0); 331 332 LABEL("PREDICT - POP (size_queue/2)"); 333 334 in_PREDICT_VAL [port2]->write(1); 335 in_PREDICT_PUSH [port2]->write(0); 336 for (uint32_t i=0; i<_param->_nb_context; i++) 337 { 338 for (uint32_t j=0; j< _param->_size_queue[i]/2; j++) 339 { 340 in_PREDICT_CONTEXT_ID [port2]->write(i); 341 in_PREDICT_ADDRESS_PUSH [port2]->write(0xbabedead); 342 343 SC_START(0); 344 345 TEST(Tcontrol_t, out_PREDICT_ACK [port2]->read(), 1); 346 TEST(Tcontrol_t, out_PREDICT_HIT [port2]->read(), 1); 347 uint32_t k= (_param->_size_queue[i]-j)%_param->_size_queue[i]; 348 TEST(Tptr_t , out_PREDICT_INDEX [port2]->read(), k); 349 350 Taddress_t res = (0x89abcdef+((k==0)?(_param->_size_queue[i]-1):(k-1))); 351 LABEL("k : %d",k); 352 LABEL("res : %x",res); 353 LABEL("@_pop : %x",out_PREDICT_ADDRESS_POP[port2]->read()); 354 355 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port2]->read(),res); 356 357 SC_START(1); 358 } 359 360 for (uint32_t j=0; j< _param->_size_queue[i]/2; j++) 361 { 362 in_PREDICT_CONTEXT_ID [port2]->write(i); 363 in_PREDICT_ADDRESS_PUSH [port2]->write(0xbabedead); 364 365 SC_START(0); 366 367 TEST(Tcontrol_t, out_PREDICT_ACK [port2]->read(), 1); 368 TEST(Tcontrol_t, out_PREDICT_HIT [port2]->read(), 1); 369 uint32_t k=(_param->_size_queue[i]/2-j)%_param->_size_queue[i]; 370 TEST(Tptr_t , out_PREDICT_INDEX [port2]->read(), k); 371 372 Taddress_t res = (0x01234567+((k==0)?(_param->_size_queue[i]/2-1):(k-1))); 373 374 LABEL("k : %d",k); 375 LABEL("res : %x",res); 376 LABEL("@_pop : %x",out_PREDICT_ADDRESS_POP[port2]->read()); 377 378 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port2]->read(),res); 379 380 SC_START(1); 381 } 382 } 383 384 in_PREDICT_VAL [port2]->write(0); 385 386 in_DECOD_VAL [port1]->write(1); 387 in_DECOD_PUSH [port1]->write(0); 388 in_DECOD_MISS_PREDICTION [port1]->write(0); 389 390 for (uint32_t i=0; i<_param->_nb_context; i++) 391 { 392 for (uint32_t j=0; j< _param->_size_queue[i]/2; j++) 393 { 394 in_DECOD_CONTEXT_ID [port1]->write(i); 395 in_DECOD_ADDRESS_PUSH [port1]->write(0xbabedead); 396 397 SC_START(0); 398 399 TEST(Tcontrol_t, out_DECOD_ACK [port1]->read(), 1); 400 TEST(Tcontrol_t, out_DECOD_HIT [port1]->read(), 1); 401 uint32_t k=(_param->_size_queue[i]/2-j)%_param->_size_queue[i]; 402 TEST(Tptr_t , out_DECOD_INDEX [port1]->read(), k); 403 404 Taddress_t res = (0x01234567+((k==0)?(_param->_size_queue[i]/2-1):(k-1))); 405 406 LABEL("k : %d",k); 407 LABEL("res : %x",res); 408 LABEL("@_pop : %x",out_DECOD_ADDRESS_POP[port1]->read()); 409 410 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port1]->read(),res); 411 412 SC_START(1); 413 } 414 } 415 416 in_DECOD_VAL [port1]->write(0); 249 SC_START(1); 250 251 in_DECOD_VAL [port]->write(1); 252 in_DECOD_PUSH [port]->write(1); 253 for (uint32_t i=0; i<_param->_nb_context; i++) 254 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 255 { 256 in_DECOD_CONTEXT_ID [port]->write(i); 257 in_DECOD_ADDRESS_PUSH [port]->write(0x21071981+j); 258 259 SC_START(0); 260 261 TEST(Tcontrol_t, out_DECOD_ACK [port]->read(), 1); 262 TEST(Tptr_t , out_DECOD_INDEX [port]->read(),(j+1)%_param->_size_queue[i]); 263 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port]->read(),0xbeefcaca+j); 264 265 SC_START(1); 266 } 267 in_DECOD_VAL [port]->write(0); 268 269 LABEL("DECOD - POP"); 270 271 in_DECOD_VAL [port]->write(1); 272 in_DECOD_PUSH [port]->write(0); 273 for (uint32_t i=0; i<_param->_nb_context; i++) 274 for (uint32_t j=0; j< _param->_size_queue[i]; j++) 275 { 276 in_DECOD_CONTEXT_ID [port]->write(i); 277 in_DECOD_ADDRESS_PUSH [port]->write(0xbabedead); 278 279 SC_START(0); 280 281 TEST(Tcontrol_t, out_DECOD_ACK [port]->read(), 1); 282 TEST(Tcontrol_t, out_DECOD_HIT [port]->read(), 1); 283 uint32_t k=(_param->_size_queue[i]-j)%_param->_size_queue[i]; 284 TEST(Tptr_t , out_DECOD_INDEX [port]->read(), k); 285 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port]->read(),(0x21071981+((k==0)?(_param->_size_queue[i]-1):(k-1)))); 286 287 SC_START(1); 288 } 289 in_DECOD_VAL [port]->write(0); 290 // Now, the stack is empty 291 } 292 293 if (test3) 294 { 295 uint32_t port1 = rand()%_param->_nb_inst_predict; 296 uint32_t port2 = rand()%_param->_nb_inst_decod; 297 uint32_t port3 = rand()%_param->_nb_inst_update; 298 299 LABEL("Test UPDATE"); 300 301 LABEL("Predict"); 302 in_PREDICT_VAL [port1]->write(1); 303 in_PREDICT_PUSH [port1]->write(1); 304 for (uint32_t i=0; i<_param->_nb_context; i++) 305 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 306 { 307 in_PREDICT_CONTEXT_ID [port1]->write(i); 308 in_PREDICT_ADDRESS_PUSH [port1]->write(0x25071959+j); 309 310 SC_START(0); 311 312 TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); 313 TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); 314 // TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0xdeadbeef+j); 315 316 SC_START(1); 317 } 318 in_PREDICT_VAL [port1]->write(0); 319 320 LABEL("Decod"); 321 in_DECOD_VAL [port2]->write(1); 322 in_DECOD_PUSH [port2]->write(1); 323 for (uint32_t i=0; i<_param->_nb_context; i++) 324 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 325 { 326 in_DECOD_CONTEXT_ID [port2]->write(i); 327 in_DECOD_ADDRESS_PUSH [port2]->write(0x25071959+j); 328 in_DECOD_MISS_PREDICTION [port2]->write(0); 329 330 SC_START(0); 331 332 TEST(Tcontrol_t, out_DECOD_ACK [port2]->read(), 1); 333 TEST(Tptr_t , out_DECOD_INDEX [port2]->read(),(j+1)%_param->_size_queue[i]); 334 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x25071959+j); 335 336 SC_START(1); 337 } 338 in_DECOD_VAL [port2]->write(0); 339 340 LABEL("Update Decod OK"); 341 in_UPDATE_VAL [port3]->write(1); 342 in_UPDATE_PUSH [port3]->write(1); 343 in_UPDATE_FLUSH[port3]->write(0); 344 for (uint32_t i=0; i<_param->_nb_context; i++) 345 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 346 { 347 uint32_t x=(_param->_size_queue[i]/2)-1; 348 in_UPDATE_CONTEXT_ID [port3]->write(i); 349 in_UPDATE_MISS_PREDICTION [port3]->write(0); 350 in_UPDATE_PREDICTION_IFETCH [port3]->write(0); 351 in_UPDATE_INDEX [port3]->write((x+1)%_param->_size_queue[i]); 352 in_UPDATE_ADDRESS [port3]->write(0x25071959+x); 353 354 SC_START(0); 355 356 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 357 358 SC_START(1); 359 } 360 in_UPDATE_VAL [port3]->write(0); 361 362 LABEL("Update FLUSH"); 363 in_UPDATE_VAL [port3]->write(1); 364 in_UPDATE_FLUSH[port3]->write(1); 365 for (uint32_t i=0; i<_param->_nb_context; i++) 366 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 367 { 368 in_UPDATE_CONTEXT_ID [port3]->write(i); 369 SC_START(1); 370 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 371 } 372 in_UPDATE_VAL [port3]->write(0); 373 374 375 // Tcontrol_t, in_UPDATE_VAL 376 // Tcontrol_t,out_UPDATE_ACK 377 // Tcontext_t, in_UPDATE_CONTEXT_ID 378 // Tcontrol_t, in_UPDATE_PUSH 379 // Tcontrol_t, in_UPDATE_FLUSH 380 // Tptr_t , in_UPDATE_INDEX 381 // Taddress_t, in_UPDATE_ADDRESS 382 // Tcontrol_t, in_UPDATE_MISS_PREDICTION 383 // Tcontrol_t, in_UPDATE_PREDICTION_IFETCH 384 385 386 } 387 388 if (test4) 389 { 390 uint32_t port1 = rand()%_param->_nb_inst_predict; 391 uint32_t port2 = rand()%_param->_nb_inst_decod; 392 uint32_t port3 = rand()%_param->_nb_inst_update; 393 394 LABEL("Test UPDATE"); 395 396 LABEL("Predict"); 397 in_PREDICT_VAL [port1]->write(1); 398 in_PREDICT_PUSH [port1]->write(1); 399 for (uint32_t i=0; i<_param->_nb_context; i++) 400 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 401 { 402 in_PREDICT_CONTEXT_ID [port1]->write(i); 403 in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j); 404 405 SC_START(0); 406 407 TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); 408 TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); 409 // TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0xdeadbeef+j); 410 411 SC_START(1); 412 } 413 in_PREDICT_VAL [port1]->write(0); 414 415 LABEL("Decod"); 416 in_DECOD_VAL [port2]->write(1); 417 in_DECOD_PUSH [port2]->write(1); 418 for (uint32_t i=0; i<_param->_nb_context; i++) 419 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 420 { 421 in_DECOD_CONTEXT_ID [port2]->write(i); 422 in_DECOD_ADDRESS_PUSH [port2]->write(0x14011959+j); 423 in_DECOD_MISS_PREDICTION [port2]->write(0); 424 425 SC_START(0); 426 427 TEST(Tcontrol_t, out_DECOD_ACK [port2]->read(), 1); 428 TEST(Tptr_t , out_DECOD_INDEX [port2]->read(),(j+1)%_param->_size_queue[i]); 429 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x14011959+j); 430 431 SC_START(1); 432 } 433 in_DECOD_VAL [port2]->write(0); 434 435 LABEL("Update Decod KO"); 436 in_UPDATE_VAL [port3]->write(1); 437 in_UPDATE_PUSH [port3]->write(1); 438 in_UPDATE_FLUSH[port3]->write(0); 439 for (uint32_t i=0; i<_param->_nb_context; i++) 440 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 441 { 442 uint32_t x=(_param->_size_queue[i]/2); 443 in_UPDATE_CONTEXT_ID [port3]->write(i); 444 in_UPDATE_MISS_PREDICTION [port3]->write(1); 445 in_UPDATE_PREDICTION_IFETCH [port3]->write(0); 446 in_UPDATE_INDEX [port3]->write((x-j)%_param->_size_queue[i]); 447 in_UPDATE_ADDRESS [port3]->write(0xffffffff+x); 448 449 SC_START(0); 450 451 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 452 453 SC_START(1); 454 } 455 in_UPDATE_VAL [port3]->write(0); 456 457 LABEL("Decod"); 458 in_DECOD_VAL [port2]->write(1); 459 in_DECOD_PUSH [port2]->write(1); 460 for (uint32_t i=0; i<_param->_nb_context; i++) 461 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 462 { 463 in_DECOD_CONTEXT_ID [port2]->write(i); 464 in_DECOD_ADDRESS_PUSH [port2]->write(0x14011959+j); 465 in_DECOD_MISS_PREDICTION [port2]->write(0); 466 467 SC_START(0); 468 469 TEST(Tcontrol_t, out_DECOD_ACK [port2]->read(), 1); 470 TEST(Tptr_t , out_DECOD_INDEX [port2]->read(),(j+1)%_param->_size_queue[i]); 471 TEST(Taddress_t, out_DECOD_ADDRESS_POP[port2]->read(),0x14011959+j); 472 473 SC_START(1); 474 } 475 in_DECOD_VAL [port2]->write(0); 476 477 478 LABEL("Update Decod KO"); 479 in_UPDATE_VAL [port3]->write(1); 480 in_UPDATE_PUSH [port3]->write(1); 481 in_UPDATE_FLUSH[port3]->write(0); 482 for (uint32_t i=0; i<_param->_nb_context; i++) 483 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 484 { 485 uint32_t x=(_param->_size_queue[i]/2); 486 in_UPDATE_CONTEXT_ID [port3]->write(i); 487 in_UPDATE_MISS_PREDICTION [port3]->write(1); 488 in_UPDATE_PREDICTION_IFETCH [port3]->write(0); 489 in_UPDATE_INDEX [port3]->write((x-j)%_param->_size_queue[i]); 490 in_UPDATE_ADDRESS [port3]->write(0xffffffff+x); 491 492 SC_START(0); 493 494 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 495 496 SC_START(1); 497 } 498 in_UPDATE_VAL [port3]->write(0); 499 500 LABEL("Update Predict KO"); 501 in_UPDATE_VAL [port3]->write(1); 502 in_UPDATE_PUSH [port3]->write(1); 503 in_UPDATE_FLUSH[port3]->write(0); 504 for (uint32_t i=0; i<_param->_nb_context; i++) 505 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 506 { 507 uint32_t x=(_param->_size_queue[i]); 508 in_UPDATE_CONTEXT_ID [port3]->write(i); 509 in_UPDATE_MISS_PREDICTION [port3]->write(1); 510 in_UPDATE_PREDICTION_IFETCH [port3]->write(1); 511 in_UPDATE_INDEX [port3]->write((x-j)%_param->_size_queue[i]); 512 in_UPDATE_ADDRESS [port3]->write(0xffffffff+x); 513 514 SC_START(0); 515 516 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 517 518 SC_START(1); 519 } 520 in_UPDATE_VAL [port3]->write(0); 521 522 LABEL("Predict"); 523 in_PREDICT_VAL [port1]->write(1); 524 in_PREDICT_PUSH [port1]->write(1); 525 for (uint32_t i=0; i<_param->_nb_context; i++) 526 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 527 { 528 in_PREDICT_CONTEXT_ID [port1]->write(i); 529 in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j); 530 531 SC_START(0); 532 533 TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); 534 TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); 535 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0x14011959+j); 536 537 SC_START(1); 538 } 539 in_PREDICT_VAL [port1]->write(0); 540 541 LABEL("Update Predict KO"); 542 in_UPDATE_VAL [port3]->write(1); 543 in_UPDATE_PUSH [port3]->write(0); 544 in_UPDATE_FLUSH[port3]->write(0); 545 for (uint32_t i=0; i<_param->_nb_context; i++) 546 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 547 { 548 uint32_t x=(_param->_size_queue[i]); 549 in_UPDATE_CONTEXT_ID [port3]->write(i); 550 in_UPDATE_MISS_PREDICTION [port3]->write(1); 551 in_UPDATE_PREDICTION_IFETCH [port3]->write(1); 552 in_UPDATE_INDEX [port3]->write((x+j+1)%_param->_size_queue[i]); 553 in_UPDATE_ADDRESS [port3]->write(0x87654321+j); 554 555 SC_START(0); 556 557 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 558 559 SC_START(1); 560 } 561 in_UPDATE_VAL [port3]->write(0); 562 563 LABEL("Predict"); 564 in_PREDICT_VAL [port1]->write(1); 565 in_PREDICT_PUSH [port1]->write(1); 566 for (uint32_t i=0; i<_param->_nb_context; i++) 567 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 568 { 569 in_PREDICT_CONTEXT_ID [port1]->write(i); 570 in_PREDICT_ADDRESS_PUSH [port1]->write(0x14011959+j); 571 572 SC_START(0); 573 574 TEST(Tcontrol_t, out_PREDICT_ACK [port1]->read(), 1); 575 TEST(Tptr_t , out_PREDICT_INDEX [port1]->read(),(j+1)%_param->_size_queue[i]); 576 TEST(Taddress_t, out_PREDICT_ADDRESS_POP[port1]->read(),0x87654321+j); 577 578 SC_START(1); 579 } 580 in_PREDICT_VAL [port1]->write(0); 581 582 LABEL("Update FLUSH"); 583 in_UPDATE_VAL [port3]->write(1); 584 in_UPDATE_FLUSH[port3]->write(1); 585 for (uint32_t i=0; i<_param->_nb_context; i++) 586 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) 587 { 588 in_UPDATE_CONTEXT_ID [port3]->write(i); 589 SC_START(1); 590 TEST(Tcontrol_t, out_UPDATE_ACK [port3]->read(), 1); 591 } 592 in_UPDATE_VAL [port3]->write(0); 417 593 } 418 594 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h
r95 r100 88 88 public : SC_IN (Tcontext_t) ** in_UPDATE_CONTEXT_ID ; //[nb_inst_update] 89 89 public : SC_IN (Tcontrol_t) ** in_UPDATE_PUSH ; //[nb_inst_update] 1 = push, else pop 90 public : SC_IN (Tcontrol_t) ** in_UPDATE_FLUSH ; //[nb_inst_update] 1 = push, else pop90 public : SC_IN (Tcontrol_t) ** in_UPDATE_FLUSH ; //[nb_inst_update] 91 91 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; //[nb_inst_update] 92 92 public : SC_IN (Tptr_t ) ** in_UPDATE_INDEX ; //[nb_inst_update] … … 99 99 private : ras_entry_t ** reg_stack ; //[nb_context][size_queue] 100 100 private : Tptr_t * reg_TOP ; //[nb_context] 101 101 //private : Tptr_t * reg_BOTTOM ; //[nb_context] 102 102 private : Tptr_t * reg_NB_ELT ; //[nb_context] 103 103 private : Tptr_t * reg_PREDICT_TOP ; //[nb_context] 104 104 //private : Tptr_t * reg_PREDICT_BOTTOM; //[nb_context] 105 105 private : Tptr_t * reg_PREDICT_NB_ELT; //[nb_context] 106 106 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Types.h
r81 r100 21 21 class ras_entry_t 22 22 { 23 24 25 23 //public : bool _val ; 24 //public : bool _predict; 25 //public : bool _miss ; 26 26 public : Taddress_t _address; 27 27 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp
r95 r100 107 107 108 108 reg_TOP = new Tptr_t [_param->_nb_context]; 109 109 // reg_BOTTOM = new Tptr_t [_param->_nb_context]; 110 110 reg_NB_ELT = new Tptr_t [_param->_nb_context]; 111 111 112 112 reg_PREDICT_TOP = new Tptr_t [_param->_nb_context]; 113 113 // reg_PREDICT_BOTTOM = new Tptr_t [_param->_nb_context]; 114 114 reg_PREDICT_NB_ELT = new Tptr_t [_param->_nb_context]; 115 115 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp
r95 r100 64 64 delete [] reg_stack; 65 65 delete [] reg_TOP; 66 66 // delete [] reg_BOTTOM; 67 67 delete [] reg_NB_ELT; 68 68 delete [] reg_PREDICT_TOP; 69 69 // delete [] reg_PREDICT_BOTTOM; 70 70 delete [] reg_PREDICT_NB_ELT; 71 71 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_decod.cpp
r81 r100 22 22 void Return_Address_Stack::genMealy_decod (void) 23 23 { 24 log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); 24 log_begin(Return_Address_Stack,FUNCTION); 25 log_function(Return_Address_Stack,FUNCTION,_name.c_str()); 25 26 26 27 #ifdef DEBUG_TEST 28 // just to test if have many transaction on a same context 27 29 bool context_valid [_param->_nb_context]; 28 30 for (uint32_t i=0; i<_param->_nb_context; i++) … … 32 34 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 33 35 { 36 // Read context number 34 37 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 35 38 … … 49 52 // if pop : val and not miss 50 53 // when the predictor : if hit = 0, wait (is not accurate) 51 internal_DECOD_HIT [i] = (push or (reg_ stack[context][top]._val and not reg_stack[context][top]._miss and (reg_NB_ELT[context]>0)));54 internal_DECOD_HIT [i] = (push or (reg_NB_ELT[context]>0)); 52 55 PORT_WRITE(out_DECOD_HIT [i], internal_DECOD_HIT [i]); 53 56 … … 61 64 } 62 65 63 log_ printf(FUNC,Return_Address_Stack,FUNCTION,"End");66 log_end(Return_Address_Stack,FUNCTION); 64 67 }; 65 68 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_genMealy_predict.cpp
r81 r100 22 22 void Return_Address_Stack::genMealy_predict (void) 23 23 { 24 log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); 24 log_begin(Return_Address_Stack,FUNCTION); 25 log_function(Return_Address_Stack,FUNCTION,_name.c_str()); 25 26 26 27 #ifdef DEBUG_TEST 28 // just to test if have many transaction on a same context 27 29 bool context_valid [_param->_nb_context]; 28 30 for (uint32_t i=0; i<_param->_nb_context; i++) … … 32 34 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 33 35 { 36 // Read context number 34 37 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 35 38 36 39 #ifdef DEBUG_TEST 37 40 if (PORT_READ(in_PREDICT_VAL [i])) … … 42 45 } 43 46 #endif 44 47 48 // Get top 45 49 Tptr_t top = reg_PREDICT_TOP[context]; 46 50 Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); 47 51 48 // if push : value is hit 49 // if pop : val and not miss 50 internal_PREDICT_HIT [i] = (push or (reg_stack[context][top]._val and not reg_stack[context][top]._miss and (reg_PREDICT_NB_ELT[context]>0))); 52 // Hit : 53 // * if push : value is hit 54 // * if pop : no empty 55 internal_PREDICT_HIT [i] = (push or (reg_PREDICT_NB_ELT[context]>0)); 56 51 57 PORT_WRITE(out_PREDICT_HIT [i], internal_PREDICT_HIT [i]); 52 58 53 59 // if pop : address_pop = stack [top] 54 // if push : stock [top+1] = address_push; also st ock [top+1] is erase ! give the old value atthe update table60 // if push : stock [top+1] = address_push; also stack [top+1] is erase ! save the old value in the update table 55 61 if (push) 56 62 top = (top+1)%_param->_size_queue[context]; … … 60 66 } 61 67 62 log_ printf(FUNC,Return_Address_Stack,FUNCTION,"End");68 log_end(Return_Address_Stack,FUNCTION); 63 69 }; 64 70 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
r95 r100 22 22 void Return_Address_Stack::transition (void) 23 23 { 24 log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); 24 log_begin(Return_Address_Stack,FUNCTION); 25 log_function(Return_Address_Stack,FUNCTION,_name.c_str()); 25 26 26 27 if (PORT_READ(in_NRESET)==0) 27 28 { 29 // Reset all structure 28 30 for (uint32_t i=0; i<_param->_nb_context; i++) 29 31 { 30 32 reg_TOP [i] = 0; 31 reg_BOTTOM [i] = 0;33 // reg_BOTTOM [i] = 0; 32 34 reg_NB_ELT [i] = 0; 33 35 34 36 reg_PREDICT_TOP [i] = 0; 35 reg_PREDICT_BOTTOM [i] = 0;37 // reg_PREDICT_BOTTOM [i] = 0; 36 38 reg_PREDICT_NB_ELT [i] = 0; 37 38 for (uint32_t j=0; j<_param->_size_queue [i]; j++)39 {40 reg_stack[i][j]._val = false;41 reg_stack[i][j]._predict = false;42 reg_stack[i][j]._miss = false;43 }44 39 } 45 40 } … … 52 47 if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) 53 48 { 54 log_printf(TRACE,Return_Address_Stack,FUNCTION,"PREDICT[%d] : Transaction",i); 49 log_printf(TRACE,Return_Address_Stack,FUNCTION," * PREDICT [%d] : Transaction",i); 50 51 // Read information and pointer 55 52 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 56 53 Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); 54 57 55 Tptr_t top_old = reg_PREDICT_TOP [context]; 58 56 Tptr_t top_new = top_old; 59 Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; 60 61 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 62 63 // Hit : push or (val and not miss and not empty) 57 // Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; 58 // Tptr_t bottom_new = bottom_old; 59 Tptr_t nb_elt_old = reg_PREDICT_NB_ELT [context]; 60 Tptr_t nb_elt_new = nb_elt_old; 61 62 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 63 64 // Hit : push or not empty 64 65 // Miss : ifetch is stall, no update 66 67 // Test if hit 65 68 if (internal_PREDICT_HIT [i]) 66 69 { 67 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 68 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); 69 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); 70 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); 71 70 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 71 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); 72 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); 73 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); 74 75 // Test if push 72 76 if (push) 73 77 { 78 log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); 79 74 80 // push : increase the top (circular) 75 81 top_new = (top_old+1)%_param->_size_queue[context]; 76 77 reg_stack [context][top_new]._val = true; // New addr 78 reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr (or not)) 79 //reg_stack [context][top_new]._miss = ; 82 83 // Write new value in Queue 80 84 reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); 81 85 82 // the stack is full, erase the most old stack83 84 86 // Test if full 85 if (reg_PREDICT_NB_ELT[context]==_param->_size_queue[context]) 86 reg_PREDICT_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; 87 // A new data is write : the stack is not empty 88 if (reg_PREDICT_NB_ELT[context]< _param->_size_queue[context]) 89 reg_PREDICT_NB_ELT[context]++; 87 // -> is full, the push erase the oldest value in stack, also nb_elt is the same 88 // -> is not full, increase nb_elt 89 // if (nb_elt_old==_param->_size_queue[context]) 90 // bottom_new = (bottom_old+1)%_param->_size_queue[context]; 91 // else 92 // nb_elt_new ++; 93 if (nb_elt_old!=_param->_size_queue[context]) 94 nb_elt_new ++; 90 95 } 91 96 else 92 97 { 93 98 // pop 94 // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 95 96 //reg_stack [context][top_new]._val = ; 97 //reg_stack [context][top_new]._predict = ; 98 //reg_stack [context][top_new]._miss = ; 99 //reg_stack [context][top_new]._address = ; 100 101 // the stack is empty 102 if (reg_PREDICT_NB_ELT[context]>0) 99 log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); 100 101 // Test if the stack is empty 102 if (nb_elt_old>0) 103 103 { 104 104 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 105 reg_PREDICT_NB_ELT[context]--;105 nb_elt_new --; 106 106 } 107 // no else : can't pop 107 108 } 108 109 109 reg_PREDICT_TOP [context] = top_new; 110 111 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 112 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); 113 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); 114 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); 115 } 116 } 110 // Write new pointer 111 reg_PREDICT_TOP [context] = top_new; 112 // reg_PREDICT_BOTTOM [context] = bottom_new; 113 reg_PREDICT_NB_ELT [context] = nb_elt_new; 114 115 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 116 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); 117 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); 118 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); 119 } 120 } 117 121 118 122 // =================================================================== … … 122 126 if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) 123 127 { 124 log_printf(TRACE,Return_Address_Stack,FUNCTION,"DECOD[%d] : Transaction",i); 128 log_printf(TRACE,Return_Address_Stack,FUNCTION," * DECOD [%d] : Transaction",i); 129 130 // Read information 125 131 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 126 132 Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); 133 134 // Read pointer 127 135 Tptr_t top_old = reg_TOP [context]; 128 136 Tptr_t top_new = top_old; 129 Tptr_t bottom_old = reg_BOTTOM [context]; 130 //Tcontrol_t hit = internal_DECOD_HIT [i]; 131 Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 132 133 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 134 135 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 136 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); 137 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); 138 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); 139 140 if (push) 141 { 142 // push : increase the top (circular) 143 top_new = (top_old+1)%_param->_size_queue[context]; 144 145 reg_stack [context][top_new]._val = true; // New address 146 reg_stack [context][top_new]._predict = false; // No speculative 147 reg_stack [context][top_new]._miss = false; 148 reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); 149 150 // Test if full : if true, then icrease the bottom (erase the most old stack) 151 if (reg_NB_ELT[context]==_param->_size_queue[context]) 152 reg_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; 153 // A new data is write : the stack is not empty 154 if (reg_NB_ELT[context]< _param->_size_queue[context]) 155 reg_NB_ELT[context]++; 156 } 157 else 158 { 159 // pop 160 // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 161 162 //reg_stack [context][top_new]._val = ; 163 //reg_stack [context][top_new]._predict = ; 164 //reg_stack [context][top_new]._miss = ; 165 //reg_stack [context][top_new]._address = ; 166 167 // the stack is empty 168 if (reg_NB_ELT[context]>0) 169 { 170 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 171 reg_NB_ELT[context] --; 172 } 173 } 174 175 reg_TOP [context] = top_new; 176 177 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 178 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); 179 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); 180 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); 181 137 // Tptr_t bottom_old = reg_BOTTOM [context]; 138 // Tptr_t bottom_new = bottom_old; 139 Tptr_t nb_elt_old = reg_NB_ELT [context]; 140 Tptr_t nb_elt_new = nb_elt_old; 141 142 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 143 144 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 145 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); 146 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); 147 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); 148 149 // Test if push 150 if (push) 151 { 152 log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); 153 154 // push : increase the top (circular) 155 top_new = (top_old+1)%_param->_size_queue[context]; 156 157 // Write new value in Queue 158 reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); 159 160 // Test if full 161 // -> is full, the push erase the oldest value in stack, also nb_elt is the same 162 // -> is not full, increase nb_elt 163 // if (nb_elt_old==_param->_size_queue[context]) 164 // bottom_new = (bottom_old+1)%_param->_size_queue[context]; 165 // else 166 // nb_elt_new ++; 167 if (nb_elt_old!=_param->_size_queue[context]) 168 nb_elt_new ++; 169 } 170 else 171 { 172 // pop 173 log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); 174 175 // Test if the stack is empty 176 if (nb_elt_old>0) 177 { 178 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 179 nb_elt_new --; 180 } 181 // no else : can't pop 182 } 183 184 // Write new pointer 185 reg_TOP [context] = top_new; 186 // reg_BOTTOM [context] = bottom_new; 187 reg_NB_ELT [context] = nb_elt_new; 188 189 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 190 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); 191 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); 192 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); 193 182 194 // have previous miss of ifetch ? 183 195 // 2 miss : 184 196 // 1) miss predict : is very limited (local at context), can be update very quickly 185 197 // 2) miss decod : result is in commit stage ... 186 if (miss) 187 { 188 reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; 189 reg_PREDICT_TOP [context] = reg_TOP [context]; 190 reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; 198 199 // manage by Update_Fetch_Prediction_Table and Update_Prediction_Table 200 // Note : 201 // if decod miss : ifetch can have predict call and return branchement. Also, the head of decod can be false 202 203 // Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 204 205 // if (miss) 206 // { 207 // reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; 208 // reg_PREDICT_TOP [context] = reg_TOP [context]; 209 // reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; 191 210 192 // Scan full assoc !!!193 for (uint32_t j=0; j<_param->_size_queue [context]; j++)194 // Test if this slot is tagged with "predict" : if true, tagged as miss195 if (reg_stack [context][j]._predict)196 {197 reg_stack [context][j]._predict = false;198 reg_stack [context][j]._miss = true;199 }200 }211 // // Scan full assoc !!! 212 // for (uint32_t j=0; j<_param->_size_queue [context]; j++) 213 // // Test if this slot is tagged with "predict" : if true, tagged as miss 214 // if (reg_stack [context][j]._predict) 215 // { 216 // reg_stack [context][j]._predict = false; 217 // reg_stack [context][j]._miss = true; 218 // } 219 // } 201 220 } 202 221 … … 207 226 if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) 208 227 { 209 throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); 210 211 212 // Tcontrol_t miss = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); 213 // // 214 // if (miss) 215 // { 216 // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 217 // Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 218 // Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 219 // Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); 220 // Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 221 // Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 222 223 // if (push) 224 // { 225 // // // push 226 // // top_new = (top_old+1)%_param->_size_queue[context]; 227 228 // // reg_stack [context][index]._val = true; 229 // // reg_stack [context][index]._predict = false; 230 // // reg_stack [context][index]._miss = false; 231 // // reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); 232 233 // } 234 // else 235 // { 236 // // //reg_stack [context][top_new]._val = ; 237 // // //reg_stack [context][top_new]._predict = ; 238 // // //reg_stack [context][top_new]._miss = ; 239 // // //reg_stack [context][top_new]._address = ; 240 // } 241 242 // // // // Mouais bof ....... 243 // // // reg_PREDICT_TOP [context] = index; 244 // } 228 log_printf(TRACE,Return_Address_Stack,FUNCTION," * UPDATE [%d] : Transaction",i); 229 230 Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 231 Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); 232 233 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context_id : %d",context_id); 234 log_printf(TRACE,Return_Address_Stack,FUNCTION," * flush : %d",flush ); 235 236 // An miss prediction on call/return = Return Address Stack is corrupted. 237 if (flush) 238 { 239 // All pointer is set at 0 240 reg_TOP [context_id] = 0; 241 // reg_BOTTOM [context_id] = 0; 242 reg_NB_ELT [context_id] = 0; 243 244 reg_PREDICT_TOP [context_id] = 0; 245 // reg_PREDICT_BOTTOM [context_id] = 0; 246 reg_PREDICT_NB_ELT [context_id] = 0; 247 } 248 else 249 { 250 // if miss_prediction -> restore queue 251 // else, the prediction is correct 252 Tcontrol_t miss_prediction = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); 253 254 log_printf(TRACE,Return_Address_Stack,FUNCTION," * miss_prediction : %d",miss_prediction); 255 256 #ifdef DEBUG_TEST 257 Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 258 Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 259 log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); 260 log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); 261 262 // if (prediction_ifetch) 263 // { 264 // if (index != reg_PREDICT_TOP [context_id]) 265 // throw ERRORMORPHEO(FUNCTION,_("Index is different of predict_top")); 266 // } 267 // else 268 // { 269 // if (index != reg_TOP [context_id]) 270 // throw ERRORMORPHEO(FUNCTION,_("Index is different of top")); 271 // } 272 273 #endif 274 if (miss_prediction) 275 { 276 Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 277 log_printf(TRACE,Return_Address_Stack,FUNCTION," * push : %d",push); 278 #ifndef DEBUG_TEST 279 Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 280 Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 281 log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); 282 log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); 283 #endif 284 285 286 Tptr_t top_old = (prediction_ifetch)?reg_PREDICT_TOP [context_id]:reg_TOP [context_id]; 287 Tptr_t top_new = top_old; 288 289 // Tptr_t bottom_old = (prediction_ifetch)?reg_PREDICT_BOTTOM [context_id]:reg_BOTTOM [context_id]; 290 // Tptr_t bottom_new = bottom_old; 291 292 Tptr_t nb_elt_old = (prediction_ifetch)?reg_PREDICT_NB_ELT [context_id]:reg_NB_ELT [context_id]; 293 Tptr_t nb_elt_new = nb_elt_old; 294 295 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 296 if (prediction_ifetch) 297 { 298 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); 299 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); 300 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); 301 } 302 else 303 { 304 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_old); 305 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_old); 306 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_old); 307 } 308 309 // if previous is push, pop the value 310 // else is previous is pop, push the poped value 311 if (push) 312 { 313 // previous is push, now must be pop 314 315 // Test if the stack is empty 316 if (nb_elt_old>0) // ?? 317 { 318 top_new = (top_old==0)?(_param->_size_queue[context_id]-1):(top_old-1); 319 nb_elt_new --; 320 } 321 } 322 else 323 { 324 // previous is pop, now must be push 325 Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 326 327 // push : increase the top (circular) 328 // if (nb_elt_old==_param->_size_queue[context_id]) 329 // bottom_new = (bottom_old+1)%_param->_size_queue[context_id]; 330 // else 331 // nb_elt_new ++; 332 333 if (nb_elt_old!=_param->_size_queue[context_id]) 334 nb_elt_new ++; 335 336 top_new = index; 337 338 reg_stack [context_id][index]._address = address; 339 } 340 341 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 342 343 if (prediction_ifetch) 344 { 345 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); 346 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); 347 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); 348 349 reg_PREDICT_TOP [context_id] = top_new ; 350 // reg_PREDICT_BOTTOM [context_id] = bottom_new; 351 reg_PREDICT_NB_ELT [context_id] = nb_elt_new; 352 } 353 else 354 { 355 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_new); 356 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_new); 357 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_new); 358 359 reg_TOP [context_id] = top_new ; 360 // reg_BOTTOM [context_id] = bottom_new; 361 reg_NB_ELT [context_id] = nb_elt_new; 362 } 363 } 364 } 245 365 } 246 366 } 367 368 #if defined(DEBUG_Return_Address_Stack) and DEBUG>=DEBUG_TRACE 369 log_printf(TRACE,Return_Address_Stack,FUNCTION," * Dump RAS"); 370 for (uint32_t i=0; i<_param->_nb_context; ++i) 371 { 372 log_printf(TRACE,Return_Address_Stack,FUNCTION," * Return Address Stack [%d]",i); 373 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_TOP : %d",reg_TOP [i]); 374 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); 375 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); 376 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_TOP : %d",reg_PREDICT_TOP [i]); 377 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_BOTTOM : %d",reg_PREDICT_BOTTOM [i]); 378 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_NB_ELT : %d",reg_PREDICT_NB_ELT [i]); 379 380 for (uint32_t j=0; j<_param->_size_queue[i]; ++j) 381 log_printf(TRACE,Return_Address_Stack,FUNCTION," [%d] %.8x (%.8x)",j,reg_stack [i][j]._address,reg_stack [i][j]._address<<2); 382 } 383 #endif 247 384 248 385 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) … … 250 387 #endif 251 388 252 log_ printf(FUNC,Return_Address_Stack,FUNCTION,"End");389 log_end(Return_Address_Stack,FUNCTION); 253 390 }; 254 391
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