Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop
- Files:
-
- 20 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h
r81 r101 28 28 void operation_l_addc (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 29 29 void operation_l_sub (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 30 //void operation_l_mul (execute_operation_t * op, execute_register_t * reg, execute_param_t * param);31 //void operation_l_mulu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param);32 //void operation_l_div (execute_operation_t * op, execute_register_t * reg, execute_param_t * param);33 //void operation_l_divu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param);30 void operation_l_mul (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 31 void operation_l_mulu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 32 void operation_l_div (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 33 void operation_l_divu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 34 34 void operation_l_and (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); 35 35 void operation_l_or (execute_operation_t * op, execute_register_t * reg, execute_param_t * param); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp
r100 r101 90 90 91 91 bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); 92 bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); 92 // bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); 93 // In ISA : l.sub don't change flag carry 94 bool carry_out = get_flag(op->_data_rc,FLAG_CY); 93 95 94 96 // Result … … 104 106 105 107 #undef FUNCTION 108 #define FUNCTION "Functionnal_unit::operation_l_mul" 109 void operation_l_mul (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) 110 { 111 log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mul"); 112 113 Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); 114 Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); 115 Tgeneral_data_t gpr3 ; 116 bool overflow ; 117 bool carry_out ; 118 119 if (param->_size_data == 32) 120 { 121 int64_t res = static_cast<int64_t>(gpr1) * static_cast<int64_t>(gpr2); 122 123 log_printf(TRACE,Functionnal_unit,FUNCTION," * res : %llx",res); 124 125 gpr3 = param->_mask_data & static_cast<Tgeneral_data_t>(res); 126 carry_out = res != gpr3; 127 overflow = carry_out; 128 } 129 else 130 { 131 throw ERRORMORPHEO(FUNCTION,_("64 bits multiplcation : not yet implemented\n")); 132 } 133 134 // Result 135 op->_timing = param->_timing[op->_type][op->_operation]; 136 op->_data_rd = gpr3; 137 op->_data_re = 0; 138 op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); 139 op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); 140 op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; 141 op->_no_sequence = 0; 142 //op->_address = 0; 143 }; 144 145 #undef FUNCTION 146 #define FUNCTION "Functionnal_unit::operation_l_mulu" 147 void operation_l_mulu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) 148 { 149 log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mulu"); 150 151 Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); 152 Tgeneral_data_t gpr2 = unsigned(param->_size_data,op->_data_rb); 153 Tgeneral_data_t gpr3 ; 154 bool overflow ; 155 bool carry_out ; 156 157 if (param->_size_data == 32) 158 { 159 uint64_t res = static_cast<uint64_t>(gpr1) * static_cast<uint64_t>(gpr2); 160 161 log_printf(TRACE,Functionnal_unit,FUNCTION," * res : %llx",res); 162 163 gpr3 = param->_mask_data & static_cast<Tgeneral_data_t>(res); 164 carry_out = res != gpr3; 165 overflow = carry_out; 166 } 167 else 168 { 169 throw ERRORMORPHEO(FUNCTION,_("64 bits multiplcation : not yet implemented\n")); 170 } 171 172 // Result 173 op->_timing = param->_timing[op->_type][op->_operation]; 174 op->_data_rd = gpr3; 175 op->_data_re = 0; 176 op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); 177 op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); 178 op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; 179 op->_no_sequence = 0; 180 //op->_address = 0; 181 }; 182 183 #undef FUNCTION 184 #define FUNCTION "Functionnal_unit::operation_l_div" 185 void operation_l_div (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) 186 { 187 log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_div"); 188 189 Tgeneral_data_t gpr1 = signed(param->_size_data,op->_data_ra); 190 Tgeneral_data_t gpr2 = signed(param->_size_data,op->_data_rb); 191 Tgeneral_data_t gpr3 = (gpr2!=0)?(gpr1/gpr2):0; 192 bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); 193 bool carry_out = (gpr2==0); 194 195 // Result 196 op->_timing = param->_timing[op->_type][op->_operation]; 197 op->_data_rd = gpr3; 198 op->_data_re = 0; 199 op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); 200 op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); 201 op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; 202 op->_no_sequence = 0; 203 //op->_address = 0; 204 }; 205 206 #undef FUNCTION 207 #define FUNCTION "Functionnal_unit::operation_l_divu" 208 void operation_l_divu (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) 209 { 210 log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_divu"); 211 212 Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); 213 Tgeneral_data_t gpr2 = unsigned(param->_size_data,op->_data_rb); 214 Tgeneral_data_t gpr3 = (gpr2!=0)?(gpr1/gpr2):0; 215 bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); 216 bool carry_out = (gpr2==0); 217 218 // Result 219 op->_timing = param->_timing[op->_type][op->_operation]; 220 op->_data_rd = gpr3; 221 op->_data_re = 0; 222 op->_data_re = set_flag(op->_data_re,FLAG_OV,overflow ); 223 op->_data_re = set_flag(op->_data_re,FLAG_CY,carry_out); 224 op->_exception = (overflow==1)?EXCEPTION_ALU_RANGE:EXCEPTION_ALU_NONE; 225 op->_no_sequence = 0; 226 //op->_address = 0; 227 }; 228 229 #undef FUNCTION 106 230 #define FUNCTION "Functionnal_unit::operation_l_and" 107 231 void operation_l_and (execute_operation_t * op, execute_register_t * reg, execute_param_t * param) … … 465 589 Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); 466 590 591 // Tgeneral_data_t is unsigned 467 592 bool f_out = (gpr1 >= gpr2); 468 593 … … 485 610 Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); 486 611 612 // Tgeneral_data_t is unsigned 487 613 bool f_out = (gpr1 > gpr2); 488 614 … … 505 631 Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); 506 632 633 // Tgeneral_data_t is unsigned 507 634 bool f_out = (gpr1 <= gpr2); 508 635 … … 525 652 Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); 526 653 654 // Tgeneral_data_t is unsigned 527 655 bool f_out = (gpr1 < gpr2); 528 656 … … 544 672 Tgeneral_data_t gpr1 = op->_data_ra; 545 673 Tgeneral_data_t gpr2 = (op->_has_immediat==1)?op->_immediat:op->_data_rb; 546 547 log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra : %.8x",unsigned(param->_size_data,op->_data_ra)); 548 log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ras : %.8x", signed(param->_size_data,op->_data_ra)); 549 log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb : %.8x",unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb)); 550 log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rbs : %.8x", signed(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb)); 551 674 552 675 bool f_out; 553 676 554 switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 555 { 556 case 1 /*b01*/ : f_out = 1 ; break; 557 case 2 /*b10*/ : f_out = 0 ; break; 558 default : f_out = signed(param->_size_data,gpr1) >= signed(param->_size_data,gpr2); break; 559 } 560 561 log_printf(TRACE,Functionnal_unit,FUNCTION," * f_out : %.8x",f_out); 677 if (param->_size_data == 32) 678 f_out = static_cast<int32_t>(gpr1) >= static_cast<int32_t>(gpr2); 679 else 680 f_out = static_cast<int64_t>(gpr1) >= static_cast<int64_t>(gpr2); 681 682 // switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 683 // { 684 // case 1 /*b01*/ : f_out = 1 ; break; 685 // case 2 /*b10*/ : f_out = 0 ; break; 686 // default : f_out = signed(param->_size_data,gpr1) >= signed(param->_size_data,gpr2); break; 687 // } 562 688 563 689 // Result … … 581 707 bool f_out; 582 708 583 switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 584 { 585 case 1 /*b01*/ : f_out = 1; break; 586 case 2 /*b10*/ : f_out = 0; break; 587 default : f_out = signed(param->_size_data,gpr1) > signed(param->_size_data,gpr2); break; 588 } 709 if (param->_size_data == 32) 710 f_out = static_cast<int32_t>(gpr1) > static_cast<int32_t>(gpr2); 711 else 712 f_out = static_cast<int64_t>(gpr1) > static_cast<int64_t>(gpr2); 713 714 // switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 715 // { 716 // case 1 /*b01*/ : f_out = 1; break; 717 // case 2 /*b10*/ : f_out = 0; break; 718 // default : f_out = signed(param->_size_data,gpr1) > signed(param->_size_data,gpr2); break; 719 // } 589 720 590 721 // Result … … 608 739 bool f_out; 609 740 610 switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 611 { 612 case 1 /*b01*/ : f_out = 0; break; 613 case 2 /*b10*/ : f_out = 1; break; 614 default : f_out = signed(param->_size_data,gpr1) <= signed(param->_size_data,gpr2); break; 615 } 741 if (param->_size_data == 32) 742 f_out = static_cast<int32_t>(gpr1) <= static_cast<int32_t>(gpr2); 743 else 744 f_out = static_cast<int64_t>(gpr1) <= static_cast<int64_t>(gpr2); 745 746 // switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 747 // { 748 // case 1 /*b01*/ : f_out = 0; break; 749 // case 2 /*b10*/ : f_out = 1; break; 750 // default : f_out = signed(param->_size_data,gpr1) <= signed(param->_size_data,gpr2); break; 751 // } 616 752 617 753 // Result … … 635 771 bool f_out; 636 772 637 switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 638 { 639 case 1 /*b01*/ : f_out = 0; break; 640 case 2 /*b10*/ : f_out = 1; break; 641 default : f_out = signed(param->_size_data,gpr1) < signed(param->_size_data,gpr2); break; 642 } 773 if (param->_size_data == 32) 774 f_out = static_cast<int32_t>(gpr1) < static_cast<int32_t>(gpr2); 775 else 776 f_out = static_cast<int64_t>(gpr1) < static_cast<int64_t>(gpr2); 777 778 // switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) 779 // { 780 // case 1 /*b01*/ : f_out = 0; break; 781 // case 2 /*b10*/ : f_out = 1; break; 782 // default : f_out = signed(param->_size_data,gpr1) < signed(param->_size_data,gpr2); break; 783 // } 643 784 644 785 // Result -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp
r100 r101 18 18 public : const Tcontext_t _front_end_id ; 19 19 public : const Tcontext_t _ooo_engine_id; 20 public : const Tpacket_t_packet_id ;20 public : const uint32_t _packet_id ; 21 21 public : const Toperation_t _operation ; 22 22 public : const Ttype_t _type ; … … 40 40 Tcontext_t front_end_id , 41 41 Tcontext_t ooo_engine_id, 42 Tpacket_tpacket_id ,42 uint32_t packet_id , 43 43 Toperation_t operation , 44 44 Ttype_t type , … … 356 356 transaction_in.push_back(execute_transaction(_param,0,0,0, 99,OPERATION_FIND_L_FL1 ,TYPE_FIND,0,0 ,0x80000000,0x0 ,0 ,1,63,32 ,0,15,FLAG_CY ,EXCEPTION_NONE ,0)); 357 357 358 //transaction_in.push_back(execute_transaction(_param,0,0,0,100,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12344321,0x1 ,0 ,1,63,0x12344320,1,15,0 ,EXCEPTION_NONE ,0));359 //transaction_in.push_back(execute_transaction(_param,0,0,0,101,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0xffffffff,0 ,1,56,0x12345679,1,3 ,0 ,EXCEPTION_NONE ,0));360 //transaction_in.push_back(execute_transaction(_param,0,0,0,102,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0x12345678,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0));361 //transaction_in.push_back(execute_transaction(_param,0,0,0,103,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x0 ,0x0 ,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0));362 // transaction_in.push_back(execute_transaction(_param,0,0,0,104,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x70000000,0x90000000,0 ,1,56,0x0 ,1,3 ,FLAG_CY ,EXCEPTION_NONE,0));363 // transaction_in.push_back(execute_transaction(_param,0,0,0,105,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x80001000,0x80000000,0 ,1,1 ,0x1000 ,1,0 ,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0));364 // transaction_in.push_back(execute_transaction(_param,0,0,0,106,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x00000001,0x7fffffff,FLAG_CY|FLAG_OV,1,1 ,0x80000000,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0));358 transaction_in.push_back(execute_transaction(_param,0,0,0,100,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12344321,0x1 ,0 ,1,63,0x12344320,1,15,0 ,EXCEPTION_NONE ,0)); 359 transaction_in.push_back(execute_transaction(_param,0,0,0,101,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0xffffffff,0 ,1,56,0x12345679,1,3 ,0 ,EXCEPTION_NONE ,0)); 360 transaction_in.push_back(execute_transaction(_param,0,0,0,102,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x12345678,0x12345678,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0)); 361 transaction_in.push_back(execute_transaction(_param,0,0,0,103,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x0 ,0x0 ,0 ,1,56,0x0 ,1,3 ,0 ,EXCEPTION_NONE ,0)); 362 transaction_in.push_back(execute_transaction(_param,0,0,0,104,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x70000000,0x90000000,0 ,1,56,0xe0000000,1,3 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); 363 transaction_in.push_back(execute_transaction(_param,0,0,0,105,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x80001000,0x80000000,0 ,1,1 ,0x1000 ,1,0 , FLAG_OV,EXCEPTION_ALU_RANGE,0)); 364 transaction_in.push_back(execute_transaction(_param,0,0,0,106,OPERATION_ALU_L_SUB ,TYPE_ALU,0,0 ,0x00000001,0x7fffffff,FLAG_CY|FLAG_OV,1,1 ,0x80000002,1,0 ,FLAG_CY ,EXCEPTION_NONE ,0)); 365 365 366 366 transaction_in.push_back(execute_transaction(_param,0,0,0,120,OPERATION_TEST_L_SFEQ ,TYPE_TEST,0,0 ,0xdead ,0xdead ,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // + == + … … 440 440 transaction_in.push_back(execute_transaction(_param,0,0,0,232,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0x21071981,0x25071959,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + < + 441 441 transaction_in.push_back(execute_transaction(_param,0,0,0,233,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbeef,0 ,0,63,0x0 ,1,15,FLAG_F ,EXCEPTION_NONE ,0)); // - == - 442 transaction_in.push_back(execute_transaction(_param,0,0,0,234,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15, FLAG_F,EXCEPTION_NONE ,0)); // - > -442 transaction_in.push_back(execute_transaction(_param,0,0,0,234,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbabe,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - > - 443 443 transaction_in.push_back(execute_transaction(_param,0,0,0,235,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0xdeadbabe,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - < - 444 444 transaction_in.push_back(execute_transaction(_param,0,0,0,236,OPERATION_TEST_L_SFGES ,TYPE_TEST,0,0 ,0xdeadbeef,0x21524111,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // - == + (in unsigned) … … 569 569 transaction_in.push_back(execute_transaction(_param,0,0,0,628,OPERATION_SPECIAL_L_MFSPR ,TYPE_SPECIAL,1,GROUP_CUSTOM_7<<11, 0,0x0 ,0 ,1,63,0xa ,0, 0,0 ,EXCEPTION_ALU_NONE ,0,(GROUP_CUSTOM_7<<11)|0)); 570 570 571 transaction_in.push_back(execute_transaction(_param,0,0,0,700,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); 572 transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); 573 transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); 574 transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15, FLAG_OV,EXCEPTION_ALU_RANGE,0)); 575 transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MUL ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY ,EXCEPTION_NONE ,0)); 576 577 transaction_in.push_back(execute_transaction(_param,0,0,0,700,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00000001,0x00000001,0 ,1,63,0x00000001,1,15,0 ,EXCEPTION_NONE ,0)); 578 transaction_in.push_back(execute_transaction(_param,0,0,0,701,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00002107,0x00001981,0 ,1,63,0x034a5387,1,15,0 ,EXCEPTION_NONE ,0)); 579 transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x00048698,0x0000dead,0 ,1,63,0xefc6c4b8,1,15,FLAG_CY|FLAG_OV,EXCEPTION_ALU_RANGE,0)); 580 transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000002,0 ,1,63,0x80000000,1,15, FLAG_OV,EXCEPTION_ALU_RANGE,0)); 581 transaction_in.push_back(execute_transaction(_param,0,0,0,702,OPERATION_MUL_L_MULU ,TYPE_MUL,0,0 ,0x40000000,0x00000004,0 ,1,63,0x00000000,1,15,FLAG_CY ,EXCEPTION_NONE ,0)); 582 583 584 571 585 LABEL("Reset"); 572 586 in_NRESET.write(0); … … 585 599 586 600 LABEL("Iteration %d",iteration); 587 601 588 602 while (nb_transaction_out > 0) 589 603 { 590 604 Tcontrol_t val = ((rand()%100) < percent_transaction_execute_in) and not transaction_in.empty(); 591 605 in_EXECUTE_IN_VAL .write(val); … … 601 615 in_EXECUTE_IN_OOO_ENGINE_ID .write(transaction_in.front()._ooo_engine_id); 602 616 if (_param->_have_port_rob_ptr) 603 in_EXECUTE_IN_PACKET_ID .write(transaction_in.front()._packet_id);617 in_EXECUTE_IN_PACKET_ID .write(static_cast<Tpacket_t>(transaction_in.front()._packet_id)); 604 618 in_EXECUTE_IN_OPERATION .write(transaction_in.front()._operation ); 605 619 in_EXECUTE_IN_TYPE .write(transaction_in.front()._type ); … … 624 638 // TEST 625 639 if (_param->_have_port_rob_ptr) 626 TEST(Tpacket_t , out_EXECUTE_OUT_PACKET_ID .read(), transaction_out.front()._packet_id);640 TEST(Tpacket_t , out_EXECUTE_OUT_PACKET_ID .read(), static_cast<Tpacket_t>(transaction_out.front()._packet_id )); 627 641 if (_param->_have_port_context_id) 628 642 TEST(Tcontext_t , out_EXECUTE_OUT_CONTEXT_ID .read(), transaction_out.front()._context_id ); … … 649 663 TEST(Tgeneral_data_t , out_EXECUTE_OUT_DATA_RD .read(), transaction_out.front()._data_rd ); 650 664 TEST(Tgeneral_data_t , out_EXECUTE_OUT_ADDRESS .read(), transaction_out.front()._address ); 651 break;652 665 } 653 666 … … 659 672 TEST(Tgeneral_data_t , out_EXECUTE_OUT_DATA_RD .read(), transaction_out.front()._data_rd ); 660 673 TEST(Tgeneral_data_t , out_EXECUTE_OUT_ADDRESS .read(), transaction_out.front()._address ); 661 break;662 674 } 663 675 … … 685 697 686 698 SC_START(1); 687 699 } 688 700 689 701 } 702 690 703 /******************************************************** 691 704 * Simulation - End -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp
r97 r101 174 174 if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_ADDC ]._latence > 0) 175 175 _function_execute[TYPE_ALU ][OPERATION_ALU_L_ADDC ] = &(operation_l_addc ); 176 //if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_SUB ]._latence > 0)177 //_function_execute[TYPE_ALU ][OPERATION_ALU_L_SUB ] = &(operation_l_sub );176 if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_SUB ]._latence > 0) 177 _function_execute[TYPE_ALU ][OPERATION_ALU_L_SUB ] = &(operation_l_sub ); 178 178 if (_param->_timing[TYPE_ALU ][OPERATION_ALU_L_AND ]._latence > 0) 179 179 _function_execute[TYPE_ALU ][OPERATION_ALU_L_AND ] = &(operation_l_and ); … … 214 214 if (_param->_timing[TYPE_TEST ][OPERATION_TEST_L_SFNE ]._latence > 0) 215 215 _function_execute[TYPE_TEST ][OPERATION_TEST_L_SFNE ] = &(operation_l_sfne ); 216 //if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MUL ]._latence > 0)217 //_function_execute[TYPE_MUL ][OPERATION_MUL_L_MUL ] = &(operation_l_mul );218 //if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MULU ]._latence > 0)219 // _function_execute[TYPE_DIV][OPERATION_MUL_L_MULU ] = &(operation_l_mulu );220 //if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIV ]._latence > 0)221 //_function_execute[TYPE_DIV ][OPERATION_DIV_L_DIV ] = &(operation_l_div );222 //if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIVU ]._latence > 0)223 //_function_execute[TYPE_DIV ][OPERATION_DIV_L_DIVU ] = &(operation_l_divu );216 if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MUL ]._latence > 0) 217 _function_execute[TYPE_MUL ][OPERATION_MUL_L_MUL ] = &(operation_l_mul ); 218 if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MULU ]._latence > 0) 219 _function_execute[TYPE_MUL ][OPERATION_MUL_L_MULU ] = &(operation_l_mulu ); 220 if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIV ]._latence > 0) 221 _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIV ] = &(operation_l_div ); 222 if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIVU ]._latence > 0) 223 _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIVU ] = &(operation_l_divu ); 224 224 if (_param->_timing[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ]._latence > 0) 225 225 _function_execute[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ] = &(operation_l_extend_s); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h
r88 r101 133 133 // Address's Read must be aligned 134 134 135 if ((address & _mask_addr) != 0)136 TEST_KO("<Memory_t::read> Address is not aligned");135 // if ((address & _mask_addr) != 0) 136 // TEST_KO("<Memory_t::read> Address is not aligned"); 137 137 138 138 if (context>_nb_context) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp
r81 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void) 25 25 { 26 log_ printf(FUNC,Load_store_unit,FUNCTION,"Begin");27 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");26 log_begin(Load_store_unit,FUNCTION); 27 log_end (Load_store_unit,FUNCTION); 28 28 }; 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
r88 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMealy_insert (void) 25 25 { 26 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 26 log_begin(Load_store_unit,FUNCTION); 27 log_function(Load_store_unit,FUNCTION,_name.c_str()); 27 28 28 29 // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 52 53 PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]); 53 54 54 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");55 log_end(Load_store_unit,FUNCTION); 55 56 }; 56 57 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp
r81 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMealy_retire (void) 25 25 { 26 log_ printf(FUNC,Load_store_unit,FUNCTION,"Begin");27 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");26 log_begin(Load_store_unit,FUNCTION); 27 log_end (Load_store_unit,FUNCTION); 28 28 }; 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
r97 r101 24 24 void Load_store_unit::function_speculative_load_commit_genMoore (void) 25 25 { 26 log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); 26 log_begin(Load_store_unit,FUNCTION); 27 log_function(Load_store_unit,FUNCTION,_name.c_str()); 27 28 28 29 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 44 45 // Test store and load queue 45 46 46 log_printf(TRACE,Load_store_unit,FUNCTION," genMoore :Test MEMORY_OUT");47 48 log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue");47 log_printf(TRACE,Load_store_unit,FUNCTION," * Test MEMORY_OUT"); 48 49 log_printf(TRACE,Load_store_unit,FUNCTION," * Load queue"); 49 50 for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++) 50 51 // for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++) … … 71 72 _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed, 72 73 _load_queue [internal_MEMORY_OUT_PTR]._access_size); 73 log_printf(TRACE,Load_store_unit,FUNCTION," * data : %.8x",data_new); 74 log_printf(TRACE,Load_store_unit,FUNCTION," * data (old) : %.8x",data_old); 75 log_printf(TRACE,Load_store_unit,FUNCTION," * data (new) : %.8x",data_new); 74 76 log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata); 75 77 log_printf(TRACE,Load_store_unit,FUNCTION," * shift : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift); … … 91 93 if (not internal_MEMORY_OUT_VAL) 92 94 { 93 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue");95 log_printf(TRACE,Load_store_unit,FUNCTION," * Store queue"); 94 96 if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) 95 97 { … … 143 145 Tdcache_data_t dcache_req_wdata ; 144 146 145 log_printf(TRACE,Load_store_unit,FUNCTION," genMoore :Test DCACHE_REQ");147 log_printf(TRACE,Load_store_unit,FUNCTION," * Test DCACHE_REQ"); 146 148 147 149 internal_DCACHE_REQ_VAL = 0; … … 152 154 if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE) 153 155 { 154 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue[%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);156 log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ); 155 157 156 158 internal_DCACHE_REQ_VAL = 1; … … 169 171 170 172 dcache_req_packet_id = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write); 171 dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address & _param->_mask_address_msb;173 dcache_req_address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb; 172 174 dcache_req_type = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation); 175 176 // log_printf(TRACE,Load_store_unit,FUNCTION," * address : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address); 177 // log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %.8x",_param->_mask_address_msb); 178 log_printf(TRACE,Load_store_unit,FUNCTION," * dcache_req_address : %.8x",dcache_req_address); 179 173 180 #ifdef SYSTEMC_VHDL_COMPATIBILITY 174 181 dcache_req_wdata = 0; … … 210 217 PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); 211 218 212 log_ printf(FUNC,Load_store_unit,FUNCTION,"End");219 log_end(Load_store_unit,FUNCTION); 213 220 }; 214 221 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r97 r101 260 260 ( internal_MEMORY_IN_ACK == 1)) 261 261 { 262 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_IN [%d]",internal_MEMORY_IN_PORT); 263 262 264 // Test operation : 263 265 //~~~~~~~~~~~~~~~~~ … … 440 442 (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) 441 443 { 442 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT transaction");444 log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); 443 445 444 446 switch (internal_MEMORY_OUT_SELECT_QUEUE) … … 498 500 (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) 499 501 { 500 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ ");502 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ[0]"); 501 503 502 504 switch (internal_DCACHE_REQ_SELECT_QUEUE) … … 602 604 ( internal_DCACHE_RSP_ACK == 1)) 603 605 { 604 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP ");606 log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP [0]"); 605 607 606 608 // don't use context_id : because there are one queue for all thread … … 610 612 Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); 611 613 612 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); 614 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); 615 log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); 616 log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); 613 617 614 618 if (DCACHE_RSP_IS_LOAD(packet_id) == 1) … … 623 627 throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons.")); 624 628 #endif 625 629 630 _load_queue [packet_id]._rdata = rdata; 626 631 627 632 if (error != DCACHE_ERROR_NONE) … … 639 644 // FIXME : convention : if bus error, the cache return the fautive address ! 640 645 // But, the load's address is aligned ! 641 _load_queue [packet_id]._rdata = rdata; 642 646 643 647 switch (_load_queue [packet_id]._state) 644 648 { … … 695 699 uint32_t j = (*_speculative_access_queue_control)[i]; 696 700 697 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %. 6d, %.2d, %s",701 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s", 698 702 j, 699 703 _speculative_access_queue[j]._context_id , … … 719 723 uint32_t j = i; 720 724 721 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %. 6d, %.2d, %s",725 log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s", 722 726 j, 723 727 _load_queue[j]._context_id , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp
r100 r101 33 33 (_param->_size_queue, 34 34 _param->_size_internal_queue, 35 0 35 0, 36 false, 37 false 36 38 ); 37 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h
r97 r101 14 14 15 15 #include <iostream> 16 #include < queue>16 #include <list> 17 17 #include "Common/include/ToString.h" 18 18 #include "Common/include/Debug.h" … … 99 99 100 100 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 101 private : std:: queue<execute_queue_entry_t *> * _queue;101 private : std::list<execute_queue_entry_t *> * _queue; 102 102 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 103 private : Tcontrol_t internal_EXECUTE_QUEUE_IN_ACK ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp
r97 r101 96 96 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 97 97 98 _queue = new std:: queue<execute_queue_entry_t *>;98 _queue = new std::list<execute_queue_entry_t *>; 99 99 100 100 #ifdef POSITION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp
r88 r101 72 72 { 73 73 delete _queue->front(); 74 _queue->pop ();74 _queue->pop_front(); 75 75 } 76 76 delete _queue; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp
r96 r101 23 23 void Execute_queue::genMoore (void) 24 24 { 25 log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); 25 log_begin(Execute_queue,FUNCTION); 26 log_function(Execute_queue,FUNCTION,_name.c_str()); 26 27 27 28 // -----[ Interface "execute_queue_in" ]-------------------------------- … … 59 60 } 60 61 61 log_ printf(FUNC,Execute_queue,FUNCTION,"End");62 log_end(Execute_queue,FUNCTION); 62 63 }; 63 64 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp
r96 r101 23 23 void Execute_queue::transition (void) 24 24 { 25 log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); 25 log_begin(Execute_queue,FUNCTION); 26 log_function(Execute_queue,FUNCTION,_name.c_str()); 26 27 27 28 if (PORT_READ(in_NRESET) == 0) … … 32 33 // > 2) flush all slot in one cycle 33 34 34 while (_queue->empty() == false) 35 _queue->pop(); 35 _queue->clear(); 36 36 } 37 37 else … … 53 53 PORT_READ(in_EXECUTE_QUEUE_IN_DATA )); 54 54 55 _queue->push (entry);55 _queue->push_back(entry); 56 56 } 57 57 … … 60 60 { 61 61 delete _queue->front(); 62 _queue->pop ();62 _queue->pop_front(); 63 63 } 64 64 } … … 69 69 #endif 70 70 71 #if DEBUG_Execute_queue and (DEBUG >= DEBUG_TRACE) 72 log_printf(TRACE,Execute_queue,FUNCTION," * Dump Execute_queue"); 73 { 74 uint32_t i=0; 75 for (std::list<execute_queue_entry_t *>::iterator it=_queue->begin(); 76 it!=_queue->end(); 77 ++it) 78 { 79 log_printf(TRACE,Execute_queue,FUNCTION," [%d] %.2d %.2d %.2d, %.4d, %.1d, %.2d %.1d, %.8x %.8x", 80 i, 81 (*it)->_context_id , 82 (*it)->_front_end_id , 83 (*it)->_ooo_engine_id, 84 (*it)->_packet_id , 85 //(*it)->_operation , 86 //(*it)->_type , 87 (*it)->_flags , 88 (*it)->_exception , 89 (*it)->_no_sequence , 90 (*it)->_address , 91 (*it)->_data 92 ); 93 i++; 94 } 95 } 96 #endif 97 71 98 72 99 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) … … 74 101 #endif 75 102 76 log_ printf(FUNC,Execute_queue,FUNCTION,"End");103 log_end(Execute_queue,FUNCTION); 77 104 }; 78 105 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp
r100 r101 35 35 (_param->_size_queue, 36 36 _param->_size_internal_queue, 37 0 37 0, 38 false, 39 false 38 40 ); 39 41 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp
r88 r101 23 23 void Write_queue::genMoore (void) 24 24 { 25 log_printf(FUNC,Write_queue,FUNCTION,"Begin"); 25 log_begin(Write_queue,FUNCTION); 26 log_function(Write_queue,FUNCTION,_name.c_str()); 26 27 27 28 // -----[ Interface "Write_queue_in" ]-------------------------------- … … 109 110 } 110 111 } 111 log_ printf(FUNC,Write_queue,FUNCTION,"End");112 log_end(Write_queue,FUNCTION); 112 113 }; 113 114 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp
r97 r101 24 24 void Write_queue::transition (void) 25 25 { 26 log_printf(FUNC,Write_queue,FUNCTION,"Begin"); 26 log_begin(Write_queue,FUNCTION); 27 log_function(Write_queue,FUNCTION,_name.c_str()); 27 28 28 29 if (PORT_READ(in_NRESET) == 0) … … 87 88 #endif 88 89 90 #if DEBUG_Write_queue and (DEBUG >= DEBUG_TRACE) 91 log_printf(TRACE,Write_queue,FUNCTION," * Dump Write_queue"); 92 { 93 uint32_t i=0; 94 95 for (std::list<write_queue_entry_t *>::iterator it=_queue->begin(); 96 it!=_queue->end(); 97 ++it) 98 { 99 log_printf(TRACE,Write_queue,FUNCTION," [%d] %.2d %.2d %.2d, %.4d, %.1d %.4d %.8x, %.1d %.4d %.1d, %.2d %.1d, %.8x", 100 i, 101 (*it)->_context_id , 102 (*it)->_front_end_id , 103 (*it)->_ooo_engine_id, 104 (*it)->_packet_id , 105 //(*it)->_operation , 106 //(*it)->_type , 107 (*it)->_write_rd , 108 (*it)->_num_reg_rd , 109 (*it)->_data_rd , 110 (*it)->_write_re , 111 (*it)->_num_reg_re , 112 (*it)->_data_re , 113 (*it)->_exception , 114 (*it)->_no_sequence , 115 (*it)->_address ); 116 i++; 117 } 118 } 119 #endif 120 89 121 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 90 122 end_cycle (); 91 123 #endif 92 124 93 log_ printf(FUNC,Write_queue,FUNCTION,"End");125 log_end(Write_queue,FUNCTION); 94 126 }; 95 127 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp
r88 r101 104 104 0, 105 105 nb_general_register[i], 106 1); 106 1, 107 "1"); 107 108 108 109 __param_spr [i] = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters … … 122 123 0, 123 124 nb_special_register[i], 124 1); 125 1, 126 "1"); 125 127 126 128 _param_gpr [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_gpr [i]);
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