Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Files:
-
- 6 edited
-
SelfTest/src/test.cpp (modified) (15 diffs)
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include/Context_State.h (modified) (1 diff)
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include/Types.h (modified) (2 diffs)
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src/Context_State.cpp (modified) (2 diffs)
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src/Context_State_genMoore.cpp (modified) (1 diff)
-
src/Context_State_transition.cpp (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r98 r101 213 213 // Initialisation 214 214 215 const bool test1 = true; 216 const bool test2 = true; 217 const bool test3 = true; 218 const bool test4 = true; 219 const bool test5 = true; 220 const bool test6 = true; 221 const bool test7 = true; 222 const bool test8 = true; 223 const bool test9 = true; 224 const bool test10 = true; 225 const bool test11 = true; 226 const bool test12 = true; 227 215 228 const uint32_t seed = 0; 216 229 //const uint32_t seed = static_cast<uint32_t>(time(NULL)); … … 264 277 uint32_t context = rand()%_param->_nb_context; 265 278 266 if ( 1)279 if (test1) 267 280 { 268 281 SC_START(3); … … 285 298 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 286 299 287 do 288 { 289 in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); 290 291 SC_START(1); 292 } 293 while (not ( in_DECOD_EVENT_VAL [port]->read() and 294 out_DECOD_EVENT_ACK [port]->read())); 295 in_DECOD_EVENT_VAL [port]->write(0); 300 in_DECOD_EVENT_VAL [port]->write(1); 301 302 SC_START(0); 303 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 304 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); 305 306 SC_START(1); 307 308 in_NB_INST_DECOD_ALL [context]->write(0); 309 in_NB_INST_COMMIT_ALL [context]->write(0); 310 in_NB_INST_COMMIT_MEM [context]->write(0); 311 312 LABEL("msync (send decod)"); 313 SC_START(0); 314 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 315 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); 316 317 SC_START(1); 318 319 in_DECOD_EVENT_VAL [port]->write(0); 320 in_NB_INST_COMMIT_ALL [context]->write(1); 296 321 297 322 LABEL("msync (wait end)"); … … 300 325 SC_START(3); 301 326 302 in_NB_INST_DECOD_ALL [context]->write(0); 303 in_NB_INST_COMMIT_ALL [context]->write(1); 304 in_NB_INST_COMMIT_MEM [context]->write(0); 305 306 SC_START(1); 307 308 LABEL("msync (send decod)"); 309 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 310 311 SC_START(3); 312 313 in_NB_INST_DECOD_ALL [context]->write(1); 314 SC_START(1); 315 316 LABEL("msync (wait end)"); 317 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 318 in_NB_INST_DECOD_ALL [context]->write(0); 319 in_NB_INST_COMMIT_MEM [context]->write(1); 320 321 SC_START(3); 322 323 in_NB_INST_COMMIT_MEM [context]->write(0); 327 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 328 in_NB_INST_COMMIT_ALL [context]->write(0); 329 324 330 SC_START(1); 325 331 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 326 332 } 327 333 328 if ( 1)334 if (test2) 329 335 { 330 336 SC_START(3); 331 337 332 338 LABEL("psync (begin)"); 333 in_NB_INST_DECOD_ALL [context]->write(1);334 in_NB_INST_COMMIT_ALL [context]->write(1);335 in_NB_INST_COMMIT_MEM [context]->write(1);336 337 uint32_t port = rand()%_param->_nb_decod_unit;338 339 in_DECOD_EVENT_CONTEXT_ID [port]->write(context);340 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);341 in_DECOD_EVENT_ADDRESS [port]->write(0x200);342 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);343 if (_param->_have_port_depth)344 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));345 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);346 347 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);348 349 do350 {351 in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);352 353 SC_START(1);354 }355 while (not ( in_DECOD_EVENT_VAL [port]->read() and356 out_DECOD_EVENT_ACK [port]->read()));357 in_DECOD_EVENT_VAL [port]->write(0);358 359 LABEL("psync (wait end)");360 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);361 362 SC_START(3);363 364 in_NB_INST_DECOD_ALL [context]->write(0);365 in_NB_INST_COMMIT_ALL [context]->write(0);366 in_NB_INST_COMMIT_MEM [context]->write(0);367 368 SC_START(1);369 370 bool find = false;371 do372 {373 in_EVENT_ACK [context]->write(rand()%percent_transaction_event);374 375 SC_START(0);376 377 if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())378 {379 TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);380 TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);381 TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);382 TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);383 384 find = true;385 }386 387 SC_START(1);388 }389 while (not find);390 391 in_EVENT_ACK [context]->write(0);392 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);393 }394 395 if (1)396 {397 SC_START(3);398 399 LABEL("csync (begin)");400 339 in_NB_INST_DECOD_ALL [context]->write(1); 401 340 in_NB_INST_COMMIT_ALL [context]->write(1); … … 410 349 if (_param->_have_port_depth) 411 350 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 412 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); 413 414 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 415 416 do 417 { 418 in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); 419 420 SC_START(1); 421 } 422 while (not ( in_DECOD_EVENT_VAL [port]->read() and 423 out_DECOD_EVENT_ACK [port]->read())); 424 in_DECOD_EVENT_VAL [port]->write(0); 425 426 LABEL("csync (wait end)"); 427 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 428 429 SC_START(3); 430 351 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); 352 353 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 354 355 in_DECOD_EVENT_VAL [port]->write(1); 356 357 SC_START(0); 358 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 359 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); 360 361 SC_START(1); 362 431 363 in_NB_INST_DECOD_ALL [context]->write(0); 432 364 in_NB_INST_COMMIT_ALL [context]->write(0); 433 365 in_NB_INST_COMMIT_MEM [context]->write(0); 434 366 367 LABEL("psync (send decod)"); 368 SC_START(0); 369 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 370 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); 371 372 SC_START(1); 373 374 in_DECOD_EVENT_VAL [port]->write(0); 375 in_NB_INST_COMMIT_ALL [context]->write(1); 376 377 LABEL("psync (wait end)"); 378 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 379 380 SC_START(3); 381 382 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 383 in_NB_INST_COMMIT_ALL [context]->write(0); 384 435 385 SC_START(1); 436 386 … … 448 398 TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0); 449 399 TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0); 450 451 find = true; 452 } 453 454 SC_START(1); 455 } 456 while (not find); 400 401 find = true; 402 } 403 404 SC_START(1); 405 } 406 while (not find); 407 457 408 in_EVENT_ACK [context]->write(0); 409 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 458 410 } 459 411 460 if ( 1)412 if (test3) 461 413 { 462 414 SC_START(3); 463 415 464 LABEL(" spr(begin)");416 LABEL("csync (begin)"); 465 417 in_NB_INST_DECOD_ALL [context]->write(1); 466 418 in_NB_INST_COMMIT_ALL [context]->write(1); … … 471 423 in_DECOD_EVENT_CONTEXT_ID [port]->write(context); 472 424 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); 473 in_DECOD_EVENT_ADDRESS [port]->write(0x100); 474 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); 425 in_DECOD_EVENT_ADDRESS [port]->write(0x300); 426 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0300); 427 if (_param->_have_port_depth) 428 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); 429 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); 430 431 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 432 433 in_DECOD_EVENT_VAL [port]->write(1); 434 435 SC_START(0); 436 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 437 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); 438 439 SC_START(1); 440 441 in_NB_INST_DECOD_ALL [context]->write(0); 442 in_NB_INST_COMMIT_ALL [context]->write(0); 443 in_NB_INST_COMMIT_MEM [context]->write(0); 444 445 LABEL("csync (send decod)"); 446 SC_START(0); 447 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 448 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); 449 450 SC_START(1); 451 452 in_DECOD_EVENT_VAL [port]->write(0); 453 in_NB_INST_COMMIT_ALL [context]->write(1); 454 455 LABEL("csync (wait end)"); 456 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 457 458 SC_START(3); 459 460 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 461 in_NB_INST_COMMIT_ALL [context]->write(0); 462 463 SC_START(1); 464 465 bool find = false; 466 do 467 { 468 in_EVENT_ACK [context]->write(rand()%percent_transaction_event); 469 470 SC_START(0); 471 472 if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read()) 473 { 474 TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x301); 475 TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdead0300); 476 TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0); 477 TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0); 478 479 find = true; 480 } 481 482 SC_START(1); 483 } 484 while (not find); 485 486 in_EVENT_ACK [context]->write(0); 487 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 488 489 } 490 491 if (test4) 492 { 493 SC_START(3); 494 495 LABEL("spr_access (begin)"); 496 in_NB_INST_DECOD_ALL [context]->write(1); 497 in_NB_INST_COMMIT_ALL [context]->write(1); 498 in_NB_INST_COMMIT_MEM [context]->write(1); 499 500 uint32_t port = rand()%_param->_nb_decod_unit; 501 502 in_DECOD_EVENT_CONTEXT_ID [port]->write(context); 503 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); 504 in_DECOD_EVENT_ADDRESS [port]->write(0x400); 505 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0400); 475 506 if (_param->_have_port_depth) 476 507 in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); … … 479 510 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 480 511 481 do 482 { 483 in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event); 484 485 SC_START(1); 486 } 487 while (not ( in_DECOD_EVENT_VAL [port]->read() and 488 out_DECOD_EVENT_ACK [port]->read())); 489 in_DECOD_EVENT_VAL [port]->write(0); 490 491 LABEL("spr (wait end)"); 492 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 493 494 SC_START(3); 495 512 in_DECOD_EVENT_VAL [port]->write(1); 513 514 SC_START(0); 515 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 516 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 0); 517 518 SC_START(1); 519 496 520 in_NB_INST_DECOD_ALL [context]->write(0); 497 521 in_NB_INST_COMMIT_ALL [context]->write(0); 498 522 in_NB_INST_COMMIT_MEM [context]->write(0); 499 500 SC_START(1);501 502 LABEL("spr (send decod)");503 TEST(Tcontrol_t, out_ CONTEXT_DECOD_ENABLE[context]->read(), 1);504 505 SC_START( 3);506 507 in_NB_INST_DECOD_ALL [context]->write(1);508 SC_START(1);509 510 LABEL("spr (wait end)");511 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 512 in_NB_INST_DECOD_ALL [context]->write(0);513 in_NB_INST_COMMIT_ALL [context]->write(1);514 515 SC_START(3);516 517 in_NB_INST_COMMIT_ALL [context]->write(0); 523 524 LABEL("spr_access (send decod)"); 525 SC_START(0); 526 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 527 TEST(Tcontrol_t, out_DECOD_EVENT_ACK [port] ->read(), 1); 528 529 SC_START(1); 530 531 in_DECOD_EVENT_VAL [port]->write(0); 532 in_NB_INST_COMMIT_ALL [context]->write(1); 533 534 LABEL("spr_access (wait end)"); 535 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 536 537 SC_START(3); 538 539 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); 540 in_NB_INST_COMMIT_ALL [context]->write(0); 541 518 542 SC_START(1); 519 543 TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); 520 544 } 521 545 522 if ( 1)546 if (test5) 523 547 { 524 548 SC_START(3); … … 610 634 } 611 635 612 if ( 1)636 if (test6) 613 637 { 614 638 SC_START(3); … … 697 721 } 698 722 699 if ( 1)723 if (test7) 700 724 { 701 725 SC_START(3); … … 791 815 } 792 816 793 if ( 1)817 if (test8) 794 818 { 795 819 SC_START(3); … … 885 909 } 886 910 887 if ( 1)911 if (test9) 888 912 { 889 913 SC_START(3); … … 979 1003 } 980 1004 981 if ( 1)1005 if (test10) 982 1006 { 983 1007 SC_START(3); … … 1073 1097 } 1074 1098 1075 if ( 1)1099 if (test11) 1076 1100 { 1077 1101 SC_START(3); … … 1167 1191 } 1168 1192 1169 if ( 1)1193 if (test12) 1170 1194 { 1171 1195 SC_START(3); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r98 r101 197 197 public : void transition (void); 198 198 public : void genMoore (void); 199 public : void genMealy_decod_event (void); 199 200 #endif 200 201 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r83 r101 29 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS , // wait end of event (miss (branch, load))32 31 CONTEXT_STATE_KO_MISS_ADDR , // update address manager 33 CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 34 CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 32 CONTEXT_STATE_KO_MISS_WAITEND , // wait end of event (miss (branch, load)) 33 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 34 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 35 35 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 36 36 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 37 37 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 38 38 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 39 39 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 40 40 CONTEXT_STATE_KO_CSYNC_FLUSH , 41 41 CONTEXT_STATE_KO_CSYNC_ADDR , 42 43 42 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 43 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 44 44 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 45 45 } context_state_t; … … 60 60 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 61 61 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS : return "context_state_ko_miss" ; break;63 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_ADDR : return "context_state_ko_miss_addr" ; break; 64 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 65 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 63 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_WAITEND : return "context_state_ko_miss_waitend"; break; 64 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 65 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 66 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 67 67 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 68 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 69 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 70 70 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 71 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 72 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 73 74 73 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 74 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 75 75 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 76 76 default : return "" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp
r88 r101 82 82 } 83 83 84 for (uint32_t i=0; i<_param->_nb_decod_unit; i++)85 {86 internal_DECOD_EVENT_ACK [i] = 1;87 PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]);88 }84 // for (uint32_t i=0; i<_param->_nb_decod_unit; i++) 85 // { 86 // internal_DECOD_EVENT_ACK [i] = 1; 87 // PORT_WRITE(out_DECOD_EVENT_ACK [i], internal_DECOD_EVENT_ACK [i]); 88 // } 89 89 90 90 internal_COMMIT_EVENT_ACK = 1; … … 112 112 dont_initialize (); 113 113 sensitive << (*(in_CLOCK)).neg(); // use internal register 114 115 # ifdef SYSTEMCASS_SPECIFIC 116 // List dependency information 117 # endif 118 119 log_printf(INFO,Context_State,FUNCTION,_("Method - genMealy_decod_event")); 120 121 SC_METHOD (genMealy_decod_event); 122 dont_initialize (); 123 sensitive << (*(in_CLOCK)).neg(); // use internal register 124 for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) 125 { 126 sensitive << (*(in_DECOD_EVENT_VAL [i])) // not necessary 127 << (*(in_DECOD_EVENT_TYPE [i])); 128 if (_param->_have_port_context_id) 129 sensitive << (*(in_DECOD_EVENT_CONTEXT_ID [i])); 130 } 131 for (uint32_t i=0; i<_param->_nb_context; ++i) 132 { 133 sensitive << (*(in_NB_INST_DECOD_ALL [i])) 134 << (*(in_NB_INST_COMMIT_ALL [i])) 135 << (*(in_NB_INST_COMMIT_MEM [i])); 136 } 114 137 115 138 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r97 r101 105 105 context_state_t state = reg_STATE [i]; 106 106 107 PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or 108 (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or 109 (state==CONTEXT_STATE_KO_SPR_ISSUE ))); 107 // PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK ) or 108 // (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or 109 // (state==CONTEXT_STATE_KO_SPR_ISSUE ))); 110 PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], (state==CONTEXT_STATE_OK)); 110 111 } 111 112 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r98 r101 35 35 { 36 36 // ------------------------------------------------------------------- 37 // -----[ next state ]------------------------------------------------ 38 // ------------------------------------------------------------------- 39 for (uint32_t i=0; i<_param->_nb_context; i++) 40 { 41 // uint32_t x = _param->_link_context_to_decod_unit [i]; 42 43 Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); 44 // Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); 45 46 context_state_t state = reg_STATE [i]; 47 48 switch (state) 49 { 50 case CONTEXT_STATE_OK : 51 { 52 // nothing, wait an event 53 break; 54 } 55 case CONTEXT_STATE_KO_EXCEP : 56 { 57 // Wait end of all instruction 58 if (inst_all == 0) 59 state = CONTEXT_STATE_KO_EXCEP_ADDR; 60 break; 61 } 62 case CONTEXT_STATE_KO_EXCEP_ADDR : 63 { 64 // nothing, wait the update of internal register (pc) 65 break; 66 } 67 case CONTEXT_STATE_KO_MISS_WAITEND : 68 { 69 // Wait end of all instruction 70 if (inst_all == 0) 71 72 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 73 state = CONTEXT_STATE_KO_MISS_ADDR; 74 break; 75 } 76 case CONTEXT_STATE_KO_EXCEP_SPR : 77 { 78 // nothing, wait the update of internal register (epcr, eear, sr, esr) 79 break; 80 } 81 case CONTEXT_STATE_KO_MISS_ADDR : 82 { 83 // nothing, wait the update of internal register (pc) 84 break; 85 } 86 // case CONTEXT_STATE_KO_PSYNC : 87 // { 88 // // Wait end of all instruction 89 // if (inst_all == 0) 90 // state = CONTEXT_STATE_KO_PSYNC_FLUSH; 91 // break; 92 // } 93 case CONTEXT_STATE_KO_PSYNC_FLUSH : 94 { 95 // nothing, wait end of flush (ifetch) 96 if (inst_all == 0) 97 // state = CONTEXT_STATE_KO_PSYNC_ADDR; 98 state = CONTEXT_STATE_OK; 99 100 break; 101 } 102 case CONTEXT_STATE_KO_PSYNC_ADDR : 103 { 104 // nothing, wait the pc write 105 break; 106 } 107 // case CONTEXT_STATE_KO_CSYNC : 108 // { 109 // // Wait end of all instruction 110 // if (inst_all == 0) 111 // state = CONTEXT_STATE_KO_CSYNC_FLUSH; 112 // break; 113 // } 114 case CONTEXT_STATE_KO_CSYNC_FLUSH : 115 { 116 // nothing, wait end of flush (all internal structure) 117 if (inst_all == 0) 118 state = CONTEXT_STATE_KO_CSYNC_ADDR; 119 break; 120 } 121 case CONTEXT_STATE_KO_CSYNC_ADDR : 122 { 123 // nothing, wait the pc write 124 break; 125 } 126 // case CONTEXT_STATE_KO_MSYNC : 127 // { 128 // // Wait end of memory instruction 129 // if (inst_mem == 0) 130 // state = CONTEXT_STATE_KO_MSYNC_ISSUE; 131 // break; 132 // } 133 // case CONTEXT_STATE_KO_MSYNC_ISSUE : 134 // { 135 // // Wait the msync issue 136 // if (inst_mem != 0) 137 // state = CONTEXT_STATE_KO_MSYNC_EXEC; 138 // break; 139 // } 140 case CONTEXT_STATE_KO_MSYNC_EXEC : 141 { 142 // Wait the end of msync 143 if (inst_all == 0) 144 state = CONTEXT_STATE_OK; 145 break; 146 } 147 // case CONTEXT_STATE_KO_SPR : 148 // { 149 // // Wait end of all instruction 150 // if (inst_all == 0) 151 // state = CONTEXT_STATE_KO_SPR_ISSUE; 152 // break; 153 // } 154 // case CONTEXT_STATE_KO_SPR_ISSUE : 155 // { 156 // // Wait the spr_access issue 157 // if (inst_all != 0) 158 // state = CONTEXT_STATE_KO_SPR_EXEC; 159 // break; 160 // } 161 case CONTEXT_STATE_KO_SPR_EXEC : 162 { 163 // Wait the spr_access execution 164 if (inst_all == 0) 165 state = CONTEXT_STATE_OK; 166 break; 167 } 168 169 default : 170 { 171 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); 172 } 173 } 174 reg_STATE [i] = state; 175 } 176 177 // ------------------------------------------------------------------- 37 178 // -----[ BRANCH_EVENT ]---------------------------------------------- 38 179 // ------------------------------------------------------------------- … … 57 198 58 199 // priority : miss > excep > spr/sync 59 uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0);200 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 60 201 uint8_t priority1 = 2; // miss 61 202 … … 71 212 { 72 213 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 73 reg_STATE [i] = CONTEXT_STATE_KO_MISS; 214 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_ADDR; 215 reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 74 216 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 75 217 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next … … 107 249 108 250 // miss > excep > spr/sync 109 uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);251 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 110 252 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 111 253 … … 120 262 if (is_valid) 121 263 { 264 log_printf(TRACE,Context_State,FUNCTION," * is_valid"); 265 122 266 // decod : 123 267 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) … … 130 274 case EVENT_TYPE_EXCEPTION : 131 275 { 276 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); 277 132 278 state_next = CONTEXT_STATE_KO_EXCEP; 133 279 … … 136 282 case EVENT_TYPE_SPR_ACCESS : 137 283 { 138 state_next = CONTEXT_STATE_KO_SPR ; 284 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); 285 286 // state_next = CONTEXT_STATE_KO_SPR ; 287 state_next = CONTEXT_STATE_KO_SPR_EXEC; 139 288 address++; // take next address 140 if (is_delay_slot)141 throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");289 // if (is_delay_slot) 290 // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 142 291 break; 143 292 } 144 293 case EVENT_TYPE_MSYNC : 145 294 { 146 state_next = CONTEXT_STATE_KO_MSYNC; 295 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); 296 297 // state_next = CONTEXT_STATE_KO_MSYNC; 298 state_next = CONTEXT_STATE_KO_MSYNC_EXEC; 147 299 address++; // take next address 148 if (is_delay_slot)149 throw ERRORMORPHEO(FUNCTION,"SPR accessin delay slot, not supported.\n");300 // if (is_delay_slot) 301 // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); 150 302 break; 151 303 } 152 304 case EVENT_TYPE_PSYNC : 153 305 { 154 state_next = CONTEXT_STATE_KO_PSYNC; 306 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); 307 308 // state_next = CONTEXT_STATE_KO_PSYNC; 309 state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; 155 310 address++; // take next address 156 311 if (is_delay_slot) 157 throw ERRORMORPHEO(FUNCTION," SPR accessin delay slot, not supported.\n");312 throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); 158 313 break; 159 314 } 160 315 case EVENT_TYPE_CSYNC : 161 316 { 162 state_next = CONTEXT_STATE_KO_CSYNC; 317 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); 318 319 // state_next = CONTEXT_STATE_KO_CSYNC; 320 state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; 163 321 address++; // take next address 164 322 if (is_delay_slot) 165 throw ERRORMORPHEO(FUNCTION," SPR accessin delay slot, not supported.\n");323 throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); 166 324 break; 167 325 } … … 210 368 211 369 // miss > excep > spr/sync 212 uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);370 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 213 371 uint8_t priority1 = 1; // exception 214 372 … … 277 435 278 436 // // miss > excep > spr/sync 279 // uint8_t priority0 = ( state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);437 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 280 438 // uint8_t priority1 = 2; // miss 281 439 … … 323 481 } 324 482 case CONTEXT_STATE_KO_MISS_ADDR : 483 // { 484 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 485 // break; 486 // } 325 487 case CONTEXT_STATE_KO_PSYNC_ADDR : 326 488 case CONTEXT_STATE_KO_CSYNC_ADDR : … … 357 519 reg_STATE [i] = CONTEXT_STATE_OK; 358 520 } 359 360 // -------------------------------------------------------------------361 // -----[ next state ]------------------------------------------------362 // -------------------------------------------------------------------363 for (uint32_t i=0; i<_param->_nb_context; i++)364 {365 // uint32_t x = _param->_link_context_to_decod_unit [i];366 367 Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);368 Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);369 370 context_state_t state = reg_STATE [i];371 372 switch (state)373 {374 case CONTEXT_STATE_OK :375 {376 // nothing, wait an event377 break;378 }379 case CONTEXT_STATE_KO_EXCEP :380 {381 // Wait end of all instruction382 if (inst_all == 0)383 state = CONTEXT_STATE_KO_EXCEP_ADDR;384 break;385 }386 case CONTEXT_STATE_KO_MISS :387 {388 // Wait end of all instruction389 if (inst_all == 0)390 state = CONTEXT_STATE_KO_MISS_ADDR;391 break;392 }393 case CONTEXT_STATE_KO_EXCEP_ADDR :394 {395 // nothing, wait the update of internal register (pc)396 break;397 }398 case CONTEXT_STATE_KO_EXCEP_SPR :399 {400 // nothing, wait the update of internal register (epcr, eear, sr, esr)401 break;402 }403 case CONTEXT_STATE_KO_MISS_ADDR :404 {405 // nothing, wait the update of internal register (pc)406 break;407 }408 case CONTEXT_STATE_KO_PSYNC :409 {410 // Wait end of all instruction411 if (inst_all == 0)412 // state = CONTEXT_STATE_KO_PSYNC_FLUSH;413 state = CONTEXT_STATE_KO_PSYNC_ADDR ;414 break;415 }416 // case CONTEXT_STATE_KO_PSYNC_FLUSH :417 // {418 // // nothing, wait end of flush (ifetch)419 // break;420 // }421 case CONTEXT_STATE_KO_PSYNC_ADDR :422 {423 // nothing, wait the pc write424 break;425 }426 case CONTEXT_STATE_KO_CSYNC :427 {428 // Wait end of all instruction429 if (inst_all == 0)430 state = CONTEXT_STATE_KO_CSYNC_ADDR ;431 // state = CONTEXT_STATE_KO_CSYNC_FLUSH;432 break;433 }434 // case CONTEXT_STATE_KO_CSYNC_FLUSH :435 // {436 // // nothing, wait end of flush (all internal structure)437 // break;438 // }439 case CONTEXT_STATE_KO_CSYNC_ADDR :440 {441 // nothing, wait the pc write442 break;443 }444 case CONTEXT_STATE_KO_MSYNC :445 {446 // Wait end of memory instruction447 if (inst_mem == 0)448 state = CONTEXT_STATE_KO_MSYNC_ISSUE;449 break;450 }451 case CONTEXT_STATE_KO_MSYNC_ISSUE :452 {453 // Wait the msync issue454 if (inst_mem != 0)455 state = CONTEXT_STATE_KO_MSYNC_EXEC;456 break;457 }458 case CONTEXT_STATE_KO_MSYNC_EXEC :459 {460 // Wait the end of msync461 if (inst_mem == 0)462 state = CONTEXT_STATE_OK;463 break;464 }465 case CONTEXT_STATE_KO_SPR :466 {467 // Wait end of all instruction468 if (inst_all == 0)469 state = CONTEXT_STATE_KO_SPR_ISSUE;470 break;471 }472 case CONTEXT_STATE_KO_SPR_ISSUE :473 {474 // Wait the spr_access issue475 if (inst_all != 0)476 state = CONTEXT_STATE_KO_SPR_EXEC;477 break;478 }479 case CONTEXT_STATE_KO_SPR_EXEC :480 {481 // Wait the spr_access execution482 if (inst_all == 0)483 state = CONTEXT_STATE_OK;484 break;485 }486 487 default :488 {489 throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));490 }491 }492 reg_STATE [i] = state;493 }494 521 495 522 for (uint32_t i=0; i<_param->_nb_context; ++i)
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