Ignore:
Timestamp:
Feb 11, 2009, 12:03:25 AM (15 years ago)
Author:
rosiere
Message:

1) Fix test in Direction_Glue for Conditionnal Branch
2) Fix Instruction Address Compute

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

    r101 r107  
    3535        reg_PC_NEXT          = 0x100>>2;
    3636        reg_PC_NEXT_IS_DS_TAKE                  = 0;
    37         reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1;
    38         for (uint32_t i=1; i<_param->_nb_instruction; i++)
     37        uint32_t index = reg_PC_NEXT % _param->_nb_instruction;
     38        for (uint32_t i=0; i<_param->_nb_instruction; i++)
    3939        reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
     40        reg_PC_NEXT_INSTRUCTION_ENABLE [index]  = 1;
    4041        reg_PC_NEXT_INST_IFETCH_PTR             = 0;
    4142        reg_PC_NEXT_BRANCH_STATE                = 0;
     
    182183//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
    183184           
    184             reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
    185             for (uint32_t i=1; i<_param->_nb_instruction; i++)
    186               reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
     185            // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
     186            uint32_t index = reg_PC_NEXT % _param->_nb_instruction;
     187            for (uint32_t i=0; i<_param->_nb_instruction; i++)
     188            reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
     189            reg_PC_NEXT_INSTRUCTION_ENABLE [index]  = 1;
    187190
    188191            reg_PC_NEXT_NEXT_VAL                    = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL);
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