Changeset 105 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Timestamp:
- Feb 5, 2009, 12:18:31 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r101 r105 73 73 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 74 74 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); 75 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); 75 76 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 76 77 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 155 156 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ); 156 157 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS ); 158 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 157 159 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ); 158 160 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); … … 214 216 215 217 const bool test1 = true; 216 const bool test2 = true;218 const bool test2 = false; 217 219 const bool test3 = true; 218 220 const bool test4 = true; … … 925 927 in_COMMIT_EVENT_ADDRESS ->write(0xa00); 926 928 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); 929 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0); 927 930 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); 928 931 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); … … 1019 1022 in_COMMIT_EVENT_ADDRESS ->write(0xd00); 1020 1023 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); 1024 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0); 1021 1025 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); 1022 1026 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); … … 1113 1117 in_COMMIT_EVENT_ADDRESS ->write(0xa00); 1114 1118 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); 1119 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1); 1115 1120 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); 1116 1121 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); … … 1207 1212 in_COMMIT_EVENT_ADDRESS ->write(0xd00); 1208 1213 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); 1214 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1); 1209 1215 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); 1210 1216 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); … … 1325 1331 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ); 1326 1332 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ); 1333 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 1327 1334 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ); 1328 1335 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r101 r105 91 91 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_IS_DELAY_SLOT ; 92 92 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS ; 93 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 93 94 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; 94 95 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r101 r105 25 25 typedef enum 26 26 { 27 CONTEXT_STATE_OK , // none event 28 CONTEXT_STATE_KO_EXCEP , // wait end of event (exception) 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS_ADDR , // update address manager 32 CONTEXT_STATE_KO_MISS_WAITEND , // wait end of event (miss (branch, load)) 33 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 34 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 35 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 36 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 37 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 38 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 39 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 40 CONTEXT_STATE_KO_CSYNC_FLUSH , 41 CONTEXT_STATE_KO_CSYNC_ADDR , 42 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 43 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 44 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 27 CONTEXT_STATE_OK , // none event 28 CONTEXT_STATE_KO_EXCEP , // wait end of event (exception) 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS_BRANCH_ADDR , // update address manager 32 CONTEXT_STATE_KO_MISS_BRANCH_WAITEND, // wait end of event (miss branch) 33 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 34 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) 35 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 36 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 37 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 38 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 39 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 40 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 41 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 42 CONTEXT_STATE_KO_CSYNC_FLUSH , 43 CONTEXT_STATE_KO_CSYNC_ADDR , 44 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 45 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 46 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 45 47 } context_state_t; 46 48 … … 56 58 switch (x) 57 59 { 58 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK : return "context_state_ok" ; break; 59 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP : return "context_state_ko_excep" ; break; 60 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 61 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_ADDR : return "context_state_ko_miss_addr" ; break; 63 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_WAITEND : return "context_state_ko_miss_waitend"; break; 64 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 65 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 67 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 70 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 73 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 74 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 75 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 60 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK : return "context_state_ok" ; break; 61 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP : return "context_state_ko_excep" ; break; 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 63 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 64 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 65 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break; 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; 67 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; 68 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 69 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 71 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 73 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 74 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 75 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 76 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 77 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 78 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 79 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 76 80 default : return "" ; break; 77 81 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r98 r105 95 95 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); 96 96 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 97 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); 97 98 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 98 99 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r98 r105 53 53 DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1); 54 54 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address); 55 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,_param->_size_instruction_address); 55 56 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); 56 57 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r101 r105 31 31 context_state_t state = reg_STATE [i]; 32 32 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or 34 (state == CONTEXT_STATE_KO_MISS_ADDR ) or 35 (state == CONTEXT_STATE_KO_PSYNC_ADDR) or 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or 34 (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or 35 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 36 (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or 36 37 (state == CONTEXT_STATE_KO_CSYNC_ADDR)); 37 38 … … 40 41 Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); 41 42 Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; 42 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);43 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ ADDR) and (reg_EVENT_IS_DS_TAKE [i]);43 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); 44 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); 44 45 // excep : address exception 45 46 // miss : address delay_slot, and address dest … … 51 52 switch (state) 52 53 { 53 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 54 case CONTEXT_STATE_KO_MISS_ADDR : (type = EVENT_TYPE_MISS_SPECULATION ); break; 55 case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; 56 case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; 57 default : (type = EVENT_TYPE_NONE ); break; 54 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 55 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; 56 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; 57 case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; 58 case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; 59 default : (type = EVENT_TYPE_NONE ); break; 58 60 } 59 61 // (type = EVENT_TYPE_SPR_ACCESS ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r101 r105 65 65 break; 66 66 } 67 case CONTEXT_STATE_KO_MISS_ WAITEND :67 case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : 68 68 { 69 69 // Wait end of all instruction … … 71 71 72 72 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 73 state = CONTEXT_STATE_KO_MISS_ADDR; 73 state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 74 break; 75 } 76 case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : 77 { 78 // Wait end of all instruction 79 if (inst_all == 0) 80 state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; 81 74 82 break; 75 83 } … … 79 87 break; 80 88 } 81 case CONTEXT_STATE_KO_MISS_ADDR : 89 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : 90 { 91 // nothing, wait the update of internal register (pc) 92 break; 93 } 94 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 82 95 { 83 96 // nothing, wait the update of internal register (pc) … … 198 211 199 212 // priority : miss > excep > spr/sync 200 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);213 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 201 214 uint8_t priority1 = 2; // miss 202 215 … … 212 225 { 213 226 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 214 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_ ADDR;215 reg_STATE [i] = CONTEXT_STATE_KO_MISS_ WAITEND; //@@@ TODO : make MISS fast (miss decod)227 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 228 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod) 216 229 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 217 230 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next … … 249 262 250 263 // miss > excep > spr/sync 251 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);264 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 252 265 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 253 266 … … 258 271 bool is_valid = ((state == CONTEXT_STATE_OK) or 259 272 (depth1< depth0) or 260 ((depth1==depth0) and (priority1> priority0)));273 ((depth1==depth0) and (priority1>=priority0))); 261 274 262 275 if (is_valid) … … 325 338 } 326 339 case EVENT_TYPE_NONE : 327 case EVENT_TYPE_MISS_SPECULATION : 328 case EVENT_TYPE_BRANCH_NO_ACCURATE : 340 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 341 case EVENT_TYPE_LOAD_MISS_SPECULATION : 342 // case EVENT_TYPE_BRANCH_NO_ACCURATE : 329 343 default : 330 344 { … … 359 373 Tdepth_t depth_max = _param->_array_size_depth [context]; 360 374 361 // 362 // 375 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 376 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 363 377 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 364 378 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); … … 368 382 369 383 // miss > excep > spr/sync 370 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);371 uint8_t priority1 = 1; // exception384 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 385 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 372 386 373 387 // is_valid = can modify local information … … 377 391 bool is_valid = ((state == CONTEXT_STATE_OK) or 378 392 (depth1< depth0) or 379 ((depth1==depth0) and (priority1> priority0)));393 ((depth1==depth0) and (priority1>=priority0))); 380 394 381 395 if (is_valid) … … 386 400 switch (type) 387 401 { 388 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 389 case EVENT_TYPE_SPR_ACCESS : 390 case EVENT_TYPE_MSYNC : 391 case EVENT_TYPE_PSYNC : 392 case EVENT_TYPE_CSYNC : 393 case EVENT_TYPE_NONE : 394 case EVENT_TYPE_MISS_SPECULATION : 395 case EVENT_TYPE_BRANCH_NO_ACCURATE : 402 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 403 case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;} 404 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 405 case EVENT_TYPE_SPR_ACCESS : 406 case EVENT_TYPE_MSYNC : 407 case EVENT_TYPE_PSYNC : 408 case EVENT_TYPE_CSYNC : 409 case EVENT_TYPE_NONE : 410 // case EVENT_TYPE_BRANCH_NO_ACCURATE : 396 411 default : 397 412 { … … 402 417 reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); 403 418 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); 404 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;419 reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 405 420 reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); 406 421 reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 407 422 reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); 408 //reg_EVENT_IS_DS_TAKE [context] = 0;423 reg_EVENT_IS_DS_TAKE [context] = 0; 409 424 reg_EVENT_DEPTH [context] = depth; 410 425 } … … 435 450 436 451 // // miss > excep > spr/sync 437 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);452 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 438 453 // uint8_t priority1 = 2; // miss 439 454 … … 444 459 // bool is_valid = ((state == CONTEXT_STATE_OK) or 445 460 // (depth1< depth0) or 446 // ((depth1==depth0) and (priority1> priority0)));461 // ((depth1==depth0) and (priority1>=priority0))); 447 462 448 463 // if (is_valid) … … 480 495 break; 481 496 } 482 case CONTEXT_STATE_KO_MISS_ ADDR:497 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: 483 498 // { 484 499 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 485 500 // break; 486 501 // } 502 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 487 503 case CONTEXT_STATE_KO_PSYNC_ADDR : 488 504 case CONTEXT_STATE_KO_CSYNC_ADDR :
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