Changeset 106 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit
- Timestamp:
- Feb 9, 2009, 11:55:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r88 r106 79 79 80 80 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) 81 log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); 81 { 82 uint32_t limit = 4; 83 84 log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); 85 86 for (uint32_t i=0; i<_param->_nb_bank; ++i) 87 { 88 uint32_t j=0; 89 for (std::list<Tgeneral_address_t>::iterator it=_gpr_list->begin(); 90 it!=_gpr_list->end(); 91 ) 92 { 93 std::string str = ""; 94 95 for (uint32_t x=0; x<limit; x++) 96 { 97 if (it==_gpr_list->end()) 98 break; 99 else 100 str+=toString("GPR[%.4d][%.4d] : %.5d | ",i,j,*it); 101 ++it; 102 ++j; 103 } 104 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 105 } 106 } 82 107 83 for (uint32_t i=0; i<_param->_nb_bank; ++i) 108 for (uint32_t i=0; i<_param->_nb_bank; ++i) 109 { 110 uint32_t j=0; 111 for (std::list<Tspecial_address_t>::iterator it=_spr_list->begin(); 112 it!=_spr_list->end(); 113 ) 114 { 115 std::string str = ""; 116 117 for (uint32_t x=0; x<limit; x++) 118 { 119 if (it==_spr_list->end()) 120 break; 121 else 122 str+=toString("SPR[%.4d][%.4d] : %.5d | ",i,j,*it); 123 ++it; 124 ++j; 125 } 126 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 127 } 128 } 129 } 130 #endif 131 132 #ifdef DEBUG_TEST 133 if (1) 84 134 { 85 uint32_t j=0;86 for (std::list<Tgeneral_address_t>::iterator it=_gpr_list->begin();87 it!=_gpr_list->end();88 ++it)135 for (std::list<Tgeneral_address_t>::iterator it1=_gpr_list->begin(); 136 it1!=_gpr_list->end(); 137 ++it1 138 ) 89 139 { 90 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); 91 ++j; 140 std::list<Tgeneral_address_t>::iterator it2 = it1; 141 142 it2 ++; 143 while (it2 != _gpr_list->end()) 144 { 145 if (*it1 == *it2) 146 throw ERRORMORPHEO (FUNCTION,toString(_("In free list, Same GPR (%d)"),*it1)); 147 it2 ++; 148 } 149 } 150 151 for (std::list<Tspecial_address_t>::iterator it1=_spr_list->begin(); 152 it1!=_spr_list->end(); 153 ++it1 154 ) 155 { 156 std::list<Tspecial_address_t>::iterator it2 = it1; 157 158 it2 ++; 159 while (it2 != _spr_list->end()) 160 { 161 if (*it1 == *it2) 162 throw ERRORMORPHEO (FUNCTION,toString(_("In free list, Same SPR (%d)"),*it1)); 163 it2 ++; 164 } 92 165 } 93 166 } 94 for (uint32_t i=0; i<_param->_nb_bank; ++i) 95 { 96 uint32_t j=0; 97 for (std::list<Tspecial_address_t>::iterator it=_spr_list->begin(); 98 it!=_spr_list->end(); 99 ++it) 100 { 101 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); 102 ++j; 103 } 104 } 167 #endif 105 168 106 #endif107 169 } 108 170 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp
r104 r106 245 245 in_INSERT_WRITE_RE [i]->write(rand() % 2); 246 246 in_INSERT_NUM_REG_RD_LOG [i]->write((rand() % (_param->_nb_general_register_logic-1))+1); 247 in_INSERT_NUM_REG_RE_LOG [i]->write( rand() % _param->_nb_special_register_logic );248 in_INSERT_NUM_REG_RD_PHY [i]->write( rand() % _param->_nb_general_register);249 in_INSERT_NUM_REG_RE_PHY [i]->write( rand() % _param->_nb_special_register);247 in_INSERT_NUM_REG_RE_LOG [i]->write( rand() % _param->_nb_special_register_logic ); 248 in_INSERT_NUM_REG_RD_PHY [i]->write((rand() % (_param->_nb_general_register -1))+1); 249 in_INSERT_NUM_REG_RE_PHY [i]->write( rand() % _param->_nb_special_register ); 250 250 } 251 251 … … 285 285 if (in_INSERT_VAL [i]->read() and out_INSERT_ACK [i]->read()) 286 286 { 287 // ERROR BECAUSE write same register 287 288 if (in_INSERT_WRITE_RD [i]->read() == 1) 288 289 rat_gpr[front_end_id][context_id][in_INSERT_NUM_REG_RD_LOG[i]->read()] = in_INSERT_NUM_REG_RD_PHY[i]->read(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
r104 r106 154 154 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 155 155 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 156 sensitive << (*(in_RETIRE_EVENT_STATE [i][j])); 156 sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) 157 << (*(in_RETIRE_EVENT_STATE [i][j])); 157 158 158 159 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp
r104 r106 30 30 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 31 31 { 32 // An event occure 33 bool no_event = not (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) and (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); 32 34 for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) 33 internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] ;35 internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] and no_event; 34 36 for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) 35 internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] ;37 internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] and no_event; 36 38 } 37 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
r104 r106 64 64 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 65 65 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 66 67 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); 68 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); 66 69 67 70 // Test if write 71 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",PORT_READ(in_INSERT_WRITE_RD [i])); 68 72 if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1) 69 rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); 73 { 74 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",PORT_READ(in_INSERT_NUM_REG_RD_PHY [i])); 75 rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); 76 } 77 78 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",PORT_READ(in_INSERT_WRITE_RE [i])); 70 79 if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1) 71 rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); 80 { 81 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",PORT_READ(in_INSERT_NUM_REG_RE_PHY [i])); 82 rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); 83 } 72 84 } 73 85 … … 109 121 Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); 110 122 123 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 124 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 125 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); 126 111 127 if (event_state != EVENT_STATE_NO_EVENT) 112 128 { 113 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);114 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id);115 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state);116 117 129 // Test if write and have not a previous update 118 130 if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) … … 150 162 151 163 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) 152 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); 153 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 154 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 155 { 156 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); 157 158 for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) 159 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); 160 161 for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) 162 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); 163 } 164 { 165 uint32_t limit = 4; 166 167 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); 168 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 169 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 170 { 171 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); 172 173 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) 174 { 175 std::string str = ""; 176 for (uint32_t x=0; x<limit; x++) 177 { 178 uint32_t index = k+x; 179 if (index >= _param->_nb_general_register_logic) 180 break; 181 else 182 str+=toString("GPR[%.4d] - %.5d %.1d | ",index,rat_gpr[i][j][index],rat_gpr_update_table[i][j][index]); 183 } 184 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 185 } 186 187 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 188 { 189 std::string str = ""; 190 191 for (uint32_t x=0; x<limit; x++) 192 { 193 uint32_t index = k+x; 194 if (index >= _param->_nb_special_register_logic) 195 break; 196 else 197 str+=toString("SPR[%.4d] - %.5d %.1d | ",index,rat_spr[i][j][index],rat_spr_update_table[i][j][index]); 198 } 199 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 200 } 201 } 202 } 203 #endif 204 205 #ifdef DEBUG_TEST 206 if (1) 207 { 208 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 209 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 210 { 211 for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x) 212 for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) 213 if (rat_gpr[i][j][x] == rat_gpr[i][j][y]) 214 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr[%d][%d][%d] == rat_gpr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr[i][j][x])); 215 for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x) 216 for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) 217 if (rat_spr[i][j][x] == rat_spr[i][j][y]) 218 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr[%d][%d][%d] == rat_spr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr[i][j][x])); 219 } 220 221 } 164 222 #endif 165 223 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
r88 r106 49 49 if (PORT_READ(in_INSERT_VAL[i]) and internal_INSERT_ACK[i]) 50 50 { 51 log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); 52 51 53 if (PORT_READ(in_INSERT_READ_RA [i])) 52 54 { 53 55 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); 56 57 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 58 54 59 uint32_t bank = num_reg >> _param->_shift_gpr; 55 60 uint32_t reg = num_reg & _param->_mask_gpr ; … … 60 65 { 61 66 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); 67 68 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); 69 62 70 uint32_t bank = num_reg >> _param->_shift_gpr; 63 71 uint32_t reg = num_reg & _param->_mask_gpr ; … … 68 76 { 69 77 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); 78 79 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 80 70 81 uint32_t bank = num_reg >> _param->_shift_spr; 71 82 uint32_t reg = num_reg & _param->_mask_spr ; … … 76 87 { 77 88 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); 89 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg : %d",num_reg); 91 78 92 uint32_t bank = num_reg >> _param->_shift_gpr; 79 93 uint32_t reg = num_reg & _param->_mask_gpr ; … … 84 98 { 85 99 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); 100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg : %d",num_reg); 102 86 103 uint32_t bank = num_reg >> _param->_shift_spr; 87 104 uint32_t reg = num_reg & _param->_mask_spr ; … … 96 113 if (PORT_READ(in_RETIRE_VAL[i]) and internal_RETIRE_ACK[i]) 97 114 { 115 log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); 116 98 117 if (PORT_READ(in_RETIRE_READ_RA [i])) 99 118 { 100 119 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); 120 121 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 122 101 123 uint32_t bank = num_reg >> _param->_shift_gpr; 102 124 uint32_t reg = num_reg & _param->_mask_gpr ; … … 107 129 { 108 130 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); 131 132 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RD - num_reg : %d",num_reg); 133 109 134 uint32_t bank = num_reg >> _param->_shift_gpr; 110 135 uint32_t reg = num_reg & _param->_mask_gpr ; … … 115 140 { 116 141 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); 142 143 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 144 117 145 uint32_t bank = num_reg >> _param->_shift_spr; 118 146 uint32_t reg = num_reg & _param->_mask_spr ; … … 123 151 { 124 152 Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RD_PHY_OLD [i]); 153 154 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - restore_old : %d",restore_old); 155 125 156 { 126 157 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); 158 159 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_old : %d",num_reg); 160 127 161 uint32_t bank = num_reg >> _param->_shift_gpr; 128 162 uint32_t reg = num_reg & _param->_mask_gpr ; … … 131 165 { 132 166 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 167 168 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_new : %d",num_reg); 169 133 170 uint32_t bank = num_reg >> _param->_shift_gpr; 134 171 uint32_t reg = num_reg & _param->_mask_gpr ; … … 140 177 { 141 178 Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RE_PHY_OLD [i]); 179 180 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - restore_old : %d",restore_old); 181 142 182 { 143 183 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); 184 185 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); 186 144 187 uint32_t bank = num_reg >> _param->_shift_spr; 145 188 uint32_t reg = num_reg & _param->_mask_spr ; … … 148 191 { 149 192 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 193 194 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); 195 150 196 uint32_t bank = num_reg >> _param->_shift_spr; 151 197 uint32_t reg = num_reg & _param->_mask_spr ;
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