Changeset 106
- Timestamp:
- Feb 9, 2009, 11:55:26 PM (16 years ago)
- Location:
- trunk
- Files:
-
- 1 deleted
- 42 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r104 r106 18 18 namespace load_store_unit { 19 19 20 template <typename T> 21 T swapBytes (T data, uint32_t size_data, uint32_t size_access) 22 { 23 uint64_t x = static_cast<uint64_t>(data); 24 25 // switch (size_data) 26 // { 27 // case 2 : // 16 bits 28 // { 29 // switch (size_access) 30 // { 31 // case 2 : 32 // { 33 // x = ((((x>> 8)&0xff) << 0) | 34 // (((x>> 0)&0xff) << 8) ); 35 // break; 36 // } 37 // default : 38 // { 39 // break; 40 // } 41 // } 42 // break; 43 // } 44 // case 4 : // 32 bits 45 // { 46 // switch (size_access) 47 // { 48 // case 2 : 49 // { 50 // x = ((((x>> 8)&0xff) << 0) | 51 // (((x>> 0)&0xff) << 8) | 52 // (((x>>24)&0xff) << 16) | 53 // (((x>>16)&0xff) << 24) ); 54 // break; 55 // } 56 // case 4 : 57 // { 58 // x = ((((x>>24)&0xff) << 0) | 59 // (((x>>16)&0xff) << 8) | 60 // (((x>> 8)&0xff) << 16) | 61 // (((x>> 0)&0xff) << 24) ); 62 // break; 63 // } 64 // default : 65 // { 66 // break; 67 // } 68 // } 69 // break; 70 // } 71 // case 8 : // 64 bits 72 // { 73 // switch (size_access) 74 // { 75 // case 2 : 76 // { 77 // x = ((((x>> 8)&0xff) << 0) | 78 // (((x>> 0)&0xff) << 8) | 79 // (((x>>24)&0xff) << 16) | 80 // (((x>>16)&0xff) << 24) | 81 // (((x>>40)&0xff) << 32) | 82 // (((x>>32)&0xff) << 40) | 83 // (((x>>56)&0xff) << 48) | 84 // (((x>>48)&0xff) << 56) ); 85 // break; 86 // } 87 // case 4 : 88 // { 89 // x = ((((x>>24)&0xff) << 0) | 90 // (((x>>16)&0xff) << 8) | 91 // (((x>> 8)&0xff) << 16) | 92 // (((x>> 0)&0xff) << 24) | 93 // (((x>>56)&0xff) << 32) | 94 // (((x>>48)&0xff) << 40) | 95 // (((x>>40)&0xff) << 48) | 96 // (((x>>32)&0xff) << 56) ); 97 // break; 98 // } 99 // case 8 : 100 // { 101 // x = ((((x>>56)&0xff) << 0) | 102 // (((x>>48)&0xff) << 8) | 103 // (((x>>40)&0xff) << 16) | 104 // (((x>>32)&0xff) << 24) | 105 // (((x>>24)&0xff) << 32) | 106 // (((x>>16)&0xff) << 40) | 107 // (((x>> 8)&0xff) << 48) | 108 // (((x>> 0)&0xff) << 56) ); 109 // break; 110 // } 111 // default : 112 // { 113 // break; 114 // } 115 // } 116 // break; 117 // } 118 // default : 119 // { 120 // break; 121 // } 122 // } 123 124 125 uint64_t y=0; 126 127 for (uint32_t i=0; i<size_data; i+=size_access) 128 { 129 uint32_t offset = i<<3; 130 131 switch (size_access) 132 { 133 case 1 : 134 { 135 y = x; 136 break; 137 } 138 case 2 : 139 { 140 y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) | 141 (((x>>( 0+offset))&0xff) << ( 8+offset)) ); 142 break; 143 } 144 case 4 : 145 { 146 y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) | 147 (((x>>(16+offset))&0xff) << ( 8+offset)) | 148 (((x>>( 8+offset))&0xff) << (16+offset)) | 149 (((x>>( 0+offset))&0xff) << (24+offset)) ); 150 break; 151 } 152 case 8 : 153 { 154 y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) | 155 (((x>>(48+offset))&0xff) << ( 8+offset)) | 156 (((x>>(40+offset))&0xff) << (16+offset)) | 157 (((x>>(32+offset))&0xff) << (24+offset)) | 158 (((x>>(24+offset))&0xff) << (32+offset)) | 159 (((x>>(16+offset))&0xff) << (40+offset)) | 160 (((x>>( 8+offset))&0xff) << (48+offset)) | 161 (((x>>( 0+offset))&0xff) << (56+offset)) ); 162 break; 163 } 164 default : 165 { 166 break; 167 } 168 } 169 } 170 171 return static_cast<T>(y); 172 } 173 174 template <typename T> 175 T swapBits (T data, uint32_t size_data, uint32_t size_access) 176 { 177 uint8_t x = static_cast<uint8_t>(data); 178 179 uint8_t y=0; 180 181 for (uint32_t i=0; i<size_data; i+=size_access) 182 { 183 uint32_t offset = i; 184 185 switch (size_access) 186 { 187 case 1 : 188 { 189 y = x; 190 break; 191 } 192 case 2 : 193 { 194 y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) | 195 (((x>>( 0+offset))&0x1) << ( 1+offset)) ); 196 break; 197 } 198 case 4 : 199 { 200 y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) | 201 (((x>>( 2+offset))&0x1) << ( 1+offset)) | 202 (((x>>( 1+offset))&0x1) << ( 2+offset)) | 203 (((x>>( 0+offset))&0x1) << ( 3+offset)) ); 204 break; 205 } 206 case 8 : 207 { 208 y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) | 209 (((x>>( 6+offset))&0x1) << ( 1+offset)) | 210 (((x>>( 5+offset))&0x1) << ( 2+offset)) | 211 (((x>>( 4+offset))&0x1) << ( 3+offset)) | 212 (((x>>( 3+offset))&0x1) << ( 4+offset)) | 213 (((x>>( 2+offset))&0x1) << ( 5+offset)) | 214 (((x>>( 1+offset))&0x1) << ( 6+offset)) | 215 (((x>>( 0+offset))&0x1) << ( 7+offset)) ); 216 break; 217 } 218 default : 219 { 220 break; 221 } 222 } 223 } 224 225 return static_cast<T>(y); 226 } 20 227 21 228 #undef FUNCTION … … 83 290 84 291 log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); 292 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); 293 85 294 if (index_store == reg_STORE_QUEUE_PTR_READ) 86 295 { … … 148 357 149 358 // Read data 150 Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; 151 Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; 152 153 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (before): 0x%.8x",load_data); 154 log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (before): 0x%.8x",store_data); 359 bool is_big_endian = true; 360 361 Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; 362 Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; 363 Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte; 364 Tcontrol_t check_hit = _load_queue [index_load ]._check_hit; 365 uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3; 366 uint32_t store_size_access = memory_size(_store_queue[index_store]._operation)>>3; 367 368 log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian); 369 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data : 0x%.8x",load_data); 370 log_printf(TRACE,Load_store_unit,FUNCTION," * store_data : 0x%.8x",store_data); 371 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); 372 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %d",check_hit); 373 374 log_printf(TRACE,Load_store_unit,FUNCTION," * load_size_access : %d",load_size_access ); 375 log_printf(TRACE,Load_store_unit,FUNCTION," * store_size_access : %d",store_size_access); 376 377 if (is_big_endian) 378 { 379 // swap in little endian 380 load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); 381 store_data = swapBytes<Tgeneral_data_t >(store_data , _param->_size_general_data>>3,store_size_access); 382 check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); 383 384 385 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 1) : 0x%.8x",load_data); 386 log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (swap 1) : 0x%.8x",store_data); 387 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 1) : %x",check_hit_byte); 388 } 155 389 156 390 uint32_t store_nb_byte = (1<<memory_access(_store_queue[index_store]._operation)); … … 160 394 uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte; 161 395 162 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); 163 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); 164 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",_load_queue[index_load]._check_hit); 165 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",_load_queue[index_load]._check_hit_byte); 396 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); 397 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); 398 399 // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load]._operation)); 400 401 // uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb); 402 // uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte; 403 404 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min); 405 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max); 406 407 // for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++) 408 // { 409 // // Make a mask 410 // uint32_t num_store_byte = num_load_byte; 411 412 413 166 414 // The bypass is checked byte per byte 167 415 // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed. 168 bool is_big_endian = true;169 170 416 for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++) 171 417 { 172 418 // Make a mask 173 uint32_t num_load_byte; 174 175 if (is_big_endian) 176 { 177 // sd 0 : 0 1 2 3 4 5 6 7 178 // ld 0 : 0 1 2 3 4 5 6 7 >> 0 179 // lw 0 : 0 1 2 3 >> 0 -4 180 // lw 4 : 4 5 6 7 >> 32 +4 181 // lh 0 : 0 1 >> 0 -6 182 // lh 2 : 2 3 >> 16 -2 183 // lh 4 : 4 5 >> 32 +2 184 // lh 6 : 6 7 >> 48 +6 185 // lb 0 : 0 >> 0 -7 186 // lb 1 : 1 >> 8 -5 187 // lb 2 : 2 >> 16 -3 188 // lb 3 : 3 >> 24 -1 189 // lb 4 : 4 >> 32 +1 190 // lb 5 : 5 >> 40 +3 191 // lb 6 : 6 >> 48 +5 192 // lb 7 : 7 >> 56 +7 193 194 // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) 195 196 // store duplicate = all store access can be see as full size_data store 197 uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation)); 198 199 // log_printf(TRACE,Load_store_unit,FUNCTION," * num_store_byte : %d",num_store_byte); 200 // log_printf(TRACE,Load_store_unit,FUNCTION," * size_general_data>>3 : %d",(_param->_size_general_data>>3)); 201 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); 202 // log_printf(TRACE,Load_store_unit,FUNCTION," * x = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*(num_store_byte/load_nb_byte+1)) = %d+%d-%d*%d = %d" 203 // , (_param->_size_general_data>>3) 204 // , load_nb_byte 205 // , 2*load_nb_byte 206 // ,((num_store_byte/load_nb_byte)+1) 207 // ,((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1))); 419 uint32_t num_load_byte = num_store_byte; 420 421 // if (is_big_endian) 422 // { 423 // // sd 0 : 0 1 2 3 4 5 6 7 424 // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 425 // // lw 0 : 0 1 2 3 >> 0 -4 426 // // lw 4 : 4 5 6 7 >> 32 +4 427 // // lh 0 : 0 1 >> 0 -6 428 // // lh 2 : 2 3 >> 16 -2 429 // // lh 4 : 4 5 >> 32 +2 430 // // lh 6 : 6 7 >> 48 +6 431 // // lb 0 : 0 >> 0 -7 432 // // lb 1 : 1 >> 8 -5 433 // // lb 2 : 2 >> 16 -3 434 // // lb 3 : 3 >> 24 -1 435 // // lb 4 : 4 >> 32 +1 436 // // lb 5 : 5 >> 40 +3 437 // // lb 6 : 6 >> 48 +5 438 // // lb 7 : 7 >> 56 +7 439 440 // // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) 441 442 // // store duplicate = all store access can be see as full size_data store 443 // // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation)); 444 445 // // int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); 446 447 // // num_load_byte =num_store_byte+diff; 448 449 // // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); 450 // // log_printf(TRACE,Load_store_unit,FUNCTION," * diff : %d",diff); 451 452 453 // num_load_byte = num_store_byte; 454 // } 455 // else 456 // { 457 // // sd 0 : 0 1 2 3 4 5 6 7 458 // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 459 // // lw 0 : 4 5 6 7 >> 0 460 // // lw 4 : 0 1 2 3 >> 32 461 // // lh 0 : 6 7 >> 0 462 // // lh 2 : 4 5 >> 16 463 // // lh 4 : 2 3 >> 32 464 // // lh 6 : 0 1 >> 48 465 // // lb 0 : 7 >> 0 466 // // lb 1 : 6 >> 8 467 // // lb 2 : 5 >> 16 468 // // lb 3 : 4 >> 24 469 // // lb 4 : 3 >> 32 470 // // lb 5 : 2 >> 40 471 // // lb 6 : 1 >> 48 472 // // lb 7 : 0 >> 56 208 473 209 210 num_load_byte =num_store_byte+((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); 211 } 212 else 213 { 214 // sd 0 : 0 1 2 3 4 5 6 7 215 // ld 0 : 0 1 2 3 4 5 6 7 >> 0 216 // lw 0 : 4 5 6 7 >> 0 217 // lw 4 : 0 1 2 3 >> 32 218 // lh 0 : 6 7 >> 0 219 // lh 2 : 4 5 >> 16 220 // lh 4 : 2 3 >> 32 221 // lh 6 : 0 1 >> 48 222 // lb 0 : 7 >> 0 223 // lb 1 : 6 >> 8 224 // lb 2 : 5 >> 16 225 // lb 3 : 4 >> 24 226 // lb 4 : 3 >> 32 227 // lb 5 : 2 >> 40 228 // lb 6 : 1 >> 48 229 // lb 7 : 0 >> 56 230 231 num_load_byte = num_store_byte; 232 } 233 474 // num_load_byte = num_store_byte; 475 // } 476 234 477 uint32_t mask = 1<<num_load_byte; 235 478 … … 241 484 // * they have not a previous bypass with an another store 242 485 // * it's a valid request of load 243 if (( _load_queue[index_load]._check_hit_byte&mask)==0)486 if ((check_hit_byte&mask)==0) 244 487 { 245 488 // Note : Store is duplicate = all store access can be see as full size_data store 246 489 247 490 uint32_t num_store_bit_min = num_store_byte<<3; //*8 248 // 491 // uint32_t num_store_bit_max = num_store_bit_min+8-1; 249 492 uint32_t num_load_bit_min = num_load_byte <<3; //*8 250 493 uint32_t num_load_bit_max = num_load_bit_min+8-1; … … 259 502 mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min)); 260 503 261 _load_queue[index_load]._check_hit_byte |= mask;262 _load_queue[index_load]._check_hit = 1;504 check_hit_byte |= mask; 505 check_hit = 1; 263 506 change_state = true; 264 507 … … 267 510 } 268 511 269 _load_queue[index_load]._rdata = load_data; 512 if (is_big_endian) 513 { 514 // swap in little endian 515 load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); 516 check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); 517 518 519 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 2) : 0x%.8x",load_data); 520 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 2) : %x",check_hit_byte); 521 } 522 523 _load_queue[index_load]._rdata = load_data; 524 _load_queue[index_load]._check_hit_byte = check_hit_byte; 525 _load_queue[index_load]._check_hit = check_hit; 526 270 527 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); 271 528 272 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x", _load_queue[index_load]._check_hit);273 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x", _load_queue[index_load]._check_hit_byte);529 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",check_hit); 530 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); 274 531 275 532 log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); … … 295 552 { 296 553 log_printf(TRACE,Load_store_unit,FUNCTION," * next"); 554 log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); 297 555 // if (_load_queue[index_load]._store_queue_ptr_write == 0) 298 556 // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; … … 312 570 { 313 571 log_printf(TRACE,Load_store_unit,FUNCTION," * change_state"); 572 log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check); 573 574 log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load]._state).c_str()); 314 575 315 576 switch (_load_queue[index_load]._state) 316 577 { 317 case LOAD_QUEUE_WAIT_CHECK : _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; break; 578 case LOAD_QUEUE_WAIT_CHECK : 579 { 580 if (end_check) 581 _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; 582 break; 583 } 318 584 case LOAD_QUEUE_COMMIT_CHECK : 319 585 { … … 321 587 _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; 322 588 else 323 _load_queue[index_load]._state = LOAD_QUEUE_CHECK; 589 _load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end 324 590 break; 325 591 } … … 328 594 if (end_check) 329 595 _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; 596 330 597 // check find a bypass. A speculative load have been committed : report a speculation miss. 331 if (_load_queue[index_load]._check_hit != 0) 598 if ((_load_queue[index_load]._check_hit != 0)// and 599 // (_load_queue[index_load]._write_rd == 0) 600 ) 332 601 { 333 602 _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; … … 339 608 default : break; 340 609 } 341 log_printf(TRACE,Load_store_unit,FUNCTION," * new state : %d",_load_queue[index_load]._state);610 log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); 342 611 log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); 343 612 } … … 712 981 713 982 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); 983 log_printf(TRACE,Load_store_unit,FUNCTION," * packet_id : %d" , packet_id>>1); 714 984 log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); 715 985 log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); … … 719 989 packet_id >>= 1; 720 990 721 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id);991 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD"); 722 992 723 724 993 #ifdef DEBUG_TEST 725 994 if (not have_dcache_rsp(_load_queue [packet_id]._operation)) … … 754 1023 { 755 1024 log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); 756 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : % d.",_load_queue [packet_id]._state);1025 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %s",toString(_load_queue [packet_id]._state).c_str()); 757 1026 758 1027 // FIXME : convention : if bus error, the cache return the fautive address ! -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg
r98 r106 3 3 1 1 +1 # nb_decod_unit 4 4 1 1 +1 # nb_inst_branch_complete 5 0 0 +1 # size_depth[0] [nb_context]5 1 1 +1 # nb_inst_branch_speculated [0] [nb_context] 6 6 32 32 +1 # size_general_data 7 7 1 1 +1 # size_inst_decod [0] [nb_decod_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg
r98 r106 3 3 1 1 *4 # nb_decod_unit 4 4 1 4 *4 # nb_inst_branch_complete 5 0 2 +1 # size_depth[0] [nb_context]5 1 4 *2 # nb_inst_branch_speculated [0] [nb_context] 6 6 32 32 +1 # size_general_data 7 7 1 4 *4 # size_inst_decod [0] [nb_decod_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg
r98 r106 3 3 4 4 *4 # nb_decod_unit 4 4 2 2 *4 # nb_inst_branch_complete 5 4 4 +1 # size_depth[0] [nb_context]6 2 2 +1 # size_depth[1] [nb_context]7 1 1 +1 # size_depth[2] [nb_context]8 0 0 +1 # size_depth[3] [nb_context]9 4 4 +1 # size_depth[4] [nb_context]10 2 2 +1 # size_depth[5] [nb_context]11 1 1 +1 # size_depth[6] [nb_context]12 0 0 +1 # size_depth[7] [nb_context]5 6 6 +1 # nb_inst_branch_speculated [0] [nb_context] 6 3 3 +1 # nb_inst_branch_speculated [1] [nb_context] 7 2 2 +1 # nb_inst_branch_speculated [2] [nb_context] 8 1 1 +1 # nb_inst_branch_speculated [3] [nb_context] 9 8 8 +1 # nb_inst_branch_speculated [4] [nb_context] 10 4 4 +1 # nb_inst_branch_speculated [5] [nb_context] 11 2 2 +1 # nb_inst_branch_speculated [6] [nb_context] 12 1 1 +1 # nb_inst_branch_speculated [7] [nb_context] 13 13 32 32 +1 # size_general_data 14 14 4 4 *4 # size_inst_decod [0] [nb_decod_unit] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp
r98 r106 17 17 err (_(" * nb_decod_unit (uint32_t)\n")); 18 18 err (_(" * nb_inst_branch_complete (uint32_t)\n")); 19 err (_(" * size_depth[nb_context] (uint32_t)\n"));19 err (_(" * nb_inst_branch_speculated [nb_context] (uint32_t)\n")); 20 20 err (_(" * size_general_data (uint32_t)\n")); 21 21 err (_(" * size_inst_decod [nb_decod_unit] (uint32_t)\n")); … … 48 48 usage (argc, argv); 49 49 50 uint32_t * _ size_depth= new uint32_t [_nb_context];50 uint32_t * _nb_inst_branch_speculated = new uint32_t [_nb_context]; 51 51 for (uint32_t i=0; i<_nb_context; i++) 52 _ size_depth[i] = fromString<uint32_t>(argv[x++]);52 _nb_inst_branch_speculated [i] = fromString<uint32_t>(argv[x++]); 53 53 54 54 uint32_t _size_general_data = fromString<uint32_t>(argv[x++]); … … 69 69 _nb_decod_unit , 70 70 _nb_inst_branch_complete , 71 _ size_depth,71 _nb_inst_branch_speculated , 72 72 _size_general_data , 73 73 _size_inst_decod , … … 87 87 } 88 88 89 delete [] _ size_depth;89 delete [] _nb_inst_branch_speculated; 90 90 delete [] _size_inst_decod; 91 91 delete [] _link_context_to_decod_unit; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r105 r106 275 275 for (uint32_t i=0; i<_param->_nb_context; i++) 276 276 if (_param->_have_port_depth) 277 in_DEPTH_MIN [i]->write(( _param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i]));277 in_DEPTH_MIN [i]->write((log2(_param->_nb_inst_branch_speculated[i])==0)?0:(i%log2(_param->_nb_inst_branch_speculated[i]))); 278 278 279 279 uint32_t context = rand()%_param->_nb_context; … … 295 295 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); 296 296 if (_param->_have_port_depth) 297 in_DECOD_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));297 in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 298 298 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC); 299 299 … … 350 350 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); 351 351 if (_param->_have_port_depth) 352 in_DECOD_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));352 in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 353 353 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); 354 354 … … 428 428 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0300); 429 429 if (_param->_have_port_depth) 430 in_DECOD_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));430 in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 431 431 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); 432 432 … … 507 507 in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdead0400); 508 508 if (_param->_have_port_depth) 509 in_DECOD_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));509 in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 510 510 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS); 511 511 … … 559 559 // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 560 560 // if (_param->_have_port_depth) 561 // in_BRANCH_COMPLETE_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));561 // in_BRANCH_COMPLETE_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 562 562 // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); 563 563 // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); … … 580 580 581 581 if (_param->_have_port_depth) 582 in_BRANCH_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));582 in_BRANCH_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 583 583 in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400); 584 584 in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500); … … 649 649 // in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); 650 650 // if (_param->_have_port_depth) 651 // in_BRANCH_COMPLETE_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));651 // in_BRANCH_COMPLETE_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 652 652 // in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); 653 653 // in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); … … 669 669 uint32_t port = context; 670 670 671 in_BRANCH_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));671 in_BRANCH_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context+1)%log2(_param->_nb_inst_branch_speculated[context]))); 672 672 in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600); 673 673 in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700); … … 736 736 in_DECOD_EVENT_CONTEXT_ID [port]->write(context); 737 737 if (_param->_have_port_depth) 738 in_DECOD_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));738 in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); 739 739 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 740 740 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); … … 830 830 in_DECOD_EVENT_CONTEXT_ID [port]->write(context); 831 831 if (_param->_have_port_depth) 832 in_DECOD_EVENT_DEPTH [port]->write(( _param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));832 in_DECOD_EVENT_DEPTH [port]->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); 833 833 in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); 834 834 in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1); … … 922 922 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 923 923 if (_param->_have_port_depth) 924 in_COMMIT_EVENT_DEPTH ->write(( _param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));924 in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); 925 925 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 926 926 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); … … 1017 1017 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 1018 1018 if (_param->_have_port_depth) 1019 in_COMMIT_EVENT_DEPTH ->write(( _param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));1019 in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); 1020 1020 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 1021 1021 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); … … 1112 1112 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 1113 1113 if (_param->_have_port_depth) 1114 in_COMMIT_EVENT_DEPTH ->write(( _param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));1114 in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); 1115 1115 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 1116 1116 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); … … 1207 1207 in_COMMIT_EVENT_CONTEXT_ID ->write(context); 1208 1208 if (_param->_have_port_depth) 1209 in_COMMIT_EVENT_DEPTH ->write(( _param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));1209 in_COMMIT_EVENT_DEPTH ->write((log2(_param->_nb_inst_branch_speculated[context])==0)?0:((context)%log2(_param->_nb_inst_branch_speculated[context]))); 1210 1210 in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); 1211 1211 in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h
r98 r106 27 27 public : uint32_t _nb_decod_unit ; 28 28 public : uint32_t _nb_inst_branch_complete ; 29 public : uint32_t * _ array_size_depth; //[nb_context]29 public : uint32_t * _nb_inst_branch_speculated ; //[nb_context] 30 30 //public : uint32_t * _size_depth ; //[nb_context] 31 31 //public : uint32_t _size_general_data ; … … 38 38 uint32_t nb_decod_unit, 39 39 uint32_t nb_inst_branch_complete, 40 uint32_t * size_depth,40 uint32_t * nb_inst_branch_speculated, 41 41 uint32_t size_general_data, 42 42 uint32_t * size_nb_inst_decod, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r105 r106 196 196 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); 197 197 198 // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n"));199 200 198 context_state_t state = reg_STATE [i]; 201 199 … … 203 201 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 204 202 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; 205 Tdepth_t depth_max = _param->_ array_size_depth[i];203 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; 206 204 207 //Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));208 //Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));209 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));210 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));205 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 206 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 207 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 208 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 211 209 212 210 // priority : miss > excep > spr/sync 213 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 211 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 212 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 213 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 214 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 214 215 uint8_t priority1 = 2; // miss 215 216 … … 217 218 // if context_state_ok : yes 218 219 // if context_state_ko : test the depth, and the priority of event 219 220 220 bool is_valid = ((state == CONTEXT_STATE_OK) or 221 221 (depth1< depth0) or 222 222 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 223 224 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 225 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 226 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 227 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 228 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 229 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 230 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 231 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 232 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 223 233 224 234 if (is_valid) … … 251 261 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 252 262 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 253 Tdepth_t depth_max = _param->_ array_size_depth[context];263 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; 254 264 255 //Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));256 //Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));257 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));258 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));265 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 266 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 267 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 268 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 259 269 260 270 context_state_t state = reg_STATE [context]; … … 262 272 263 273 // miss > excep > spr/sync 264 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 274 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 275 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 276 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 277 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 265 278 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 266 279 … … 272 285 (depth1< depth0) or 273 286 ((depth1==depth0) and (priority1>=priority0))); 287 288 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 289 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 290 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 291 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 292 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 293 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 294 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 295 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 296 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 274 297 275 298 if (is_valid) … … 371 394 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 372 395 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 373 Tdepth_t depth_max = _param->_ array_size_depth[context];396 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; 374 397 375 //Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));376 //Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));377 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));378 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));398 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 399 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 400 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 401 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 379 402 380 403 context_state_t state = reg_STATE [context]; … … 382 405 383 406 // miss > excep > spr/sync 384 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 407 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or 408 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 409 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or 410 (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 385 411 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 386 412 … … 392 418 (depth1< depth0) or 393 419 ((depth1==depth0) and (priority1>=priority0))); 420 421 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 422 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 423 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 424 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 425 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 426 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 427 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 428 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 429 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 394 430 395 431 if (is_valid) … … 427 463 428 464 // ------------------------------------------------------------------- 429 // -----[ BRANCH_COMPLETE ]-------------------------------------------430 // -------------------------------------------------------------------431 432 // for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)433 // if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i])434 // {435 // log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i);436 // if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))437 // {438 // Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;439 // Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;440 // Tdepth_t depth_cur = reg_EVENT_DEPTH [context];441 // Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;442 // Tdepth_t depth_max = _param->_array_size_depth [context];443 444 // // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));445 // // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));446 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));447 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));448 449 // context_state_t state = reg_STATE [context];450 451 // // miss > excep > spr/sync452 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);453 // uint8_t priority1 = 2; // miss454 455 // // is_valid = can modify local information456 // // if context_state_ok : yes457 // // if context_state_ko : test the depth, and the priority of envent458 459 // bool is_valid = ((state == CONTEXT_STATE_OK) or460 // (depth1< depth0) or461 // ((depth1==depth0) and (priority1>=priority0)));462 463 // if (is_valid)464 // {465 // // commit466 // Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]);467 // reg_STATE [context] = CONTEXT_STATE_KO_MISS;468 // reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT469 // reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]);470 // reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence471 // //reg_EVENT_ADDRESS_EEAR [context];472 // reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;473 // reg_EVENT_IS_DELAY_SLOT [context] = take;474 // reg_EVENT_IS_DS_TAKE [context] = take;475 // reg_EVENT_DEPTH [context] = depth;476 // }477 // }478 // }479 480 // -------------------------------------------------------------------481 465 // -----[ EVENT ]----------------------------------------------------- 482 466 // ------------------------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp
r98 r106 22 22 uint32_t nb_decod_unit, 23 23 uint32_t nb_inst_branch_complete, 24 uint32_t * size_depth,24 uint32_t * nb_inst_branch_speculated, 25 25 uint32_t size_general_data, 26 26 uint32_t * size_nb_inst_decod, … … 34 34 _nb_decod_unit = nb_decod_unit ; 35 35 _nb_inst_branch_complete = nb_inst_branch_complete ; 36 _ array_size_depth = size_depth;36 _nb_inst_branch_speculated = nb_inst_branch_speculated ; 37 37 // _size_general_data = size_general_data ; 38 38 // _size_nb_inst_decod = size_nb_inst_decod ; … … 45 45 { 46 46 _size_context_id = log2(_nb_context); 47 _size_depth = log2(max<uint32_t>( size_depth,_nb_context));47 _size_depth = log2(max<uint32_t>(nb_inst_branch_speculated,_nb_context)); 48 48 _size_general_data = size_general_data; 49 49 _size_instruction_address = size_general_data-2; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp
r105 r106 85 85 else 86 86 { 87 // C usume the instruction (to erase)87 // Consume the instruction (to erase) 88 88 internal_DECOD_OUT_ACK [i] = 1; 89 89 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
r101 r106 144 144 // * BTB hit and the branchement is the PC current and it's the last slot. 145 145 // -> next pc must be the delay slot 146 if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alorspc_next is the destination of branchement146 if ((not pc_current_is_ds_take) and // if pc_current is ds_take, then pc_next is the destination of branchement 147 147 (address_src_lsb == (_param->_nb_instruction [context]-1))) 148 148 { … … 173 173 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); 174 174 175 // use none unit (dir, upt and ras) 175 // use none unit (dir and ras) 176 use_upt = true; 176 177 direction = true; 177 178 pc_next = address_dest; … … 324 325 ); 325 326 327 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_{ val, ack} : %d, %d", btb_val, btb_ack); 328 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * dir_{use, val, ack} : %d, %d, %d",use_dir,dir_val, dir_ack); 329 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * ras_{use, val, ack} : %d, %d, %d",use_ras,ras_val, ras_ack); 330 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_{use, val, ack} : %d, %d, %d",use_upt,upt_val, upt_ack); 331 332 326 333 // pc_next - is previously computed 327 334 // branch_state - is previously computed -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r105 r106 1424 1424 (upt_top [context] != out_DEPTH_MAX [context]->read())) 1425 1425 SC_START(1); 1426 1427 1426 } 1428 1427 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r105 r106 47 47 UPDATE_PREDICTION_STATE_KO , // this branch is a miss prediction 48 48 UPDATE_PREDICTION_STATE_EVENT , // previous branch is a miss prediction 49 UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer 50 UPDATE_PREDICTION_STATE_END_KO_WAIT_END , // branch is updated, don't update pointer 49 UPDATE_PREDICTION_STATE_END , // update pointer 50 // UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer 51 // UPDATE_PREDICTION_STATE_END_KO_WAIT_END , // branch is updated, don't update pointer 51 52 UPDATE_PREDICTION_STATE_END_KO // branch is updated, don't update pointer 52 53 } upt_state_t; … … 153 154 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_KO : return "ko" ; break; 154 155 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; 155 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; 156 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO_WAIT_END: return "end_ko_wait_end" ; break; 156 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END : return "end" ; break; 157 // case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; 158 // case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO_WAIT_END: return "end_ko_wait_end" ; break; 157 159 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO : return "end_ko" ; break; 158 160 default : return "" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r105 r106 168 168 private : uint32_t * reg_UFPT_UPDATE ; //[nb_context] 169 169 private : uint32_t * reg_UFPT_NB_NEED_UPDATE ; //[nb_context] 170 private : uint32_t * reg_UFPT_NB_UPDATE ; //[nb_context] 170 171 171 172 private : upt_entry_t ** reg_UPDATE_PREDICTION_TABLE ; //[nb_context][size_upt_queue] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r105 r106 197 197 ALLOC1(reg_UFPT_UPDATE ,uint32_t ,_param->_nb_context); 198 198 ALLOC1(reg_UFPT_NB_NEED_UPDATE ,uint32_t ,_param->_nb_context); 199 ALLOC1(reg_UFPT_NB_UPDATE ,uint32_t ,_param->_nb_context); 199 200 200 201 ALLOC2(reg_UPDATE_PREDICTION_TABLE ,upt_entry_t ,_param->_nb_context,_param->_size_upt_queue[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r105 r106 150 150 DELETE1(reg_UFPT_UPDATE ,_param->_nb_context); 151 151 DELETE1(reg_UFPT_NB_NEED_UPDATE ,_param->_nb_context); 152 DELETE1(reg_UFPT_NB_UPDATE ,_param->_nb_context); 152 153 153 154 DELETE2(reg_UPDATE_PREDICTION_TABLE ,_param->_nb_context,_param->_size_upt_queue[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r105 r106 61 61 bool retire_ras_from_ufpt [_param->_nb_context]; // event ufpt -> restore RAS, else update upt 62 62 bool retire_ras_from_upt [_param->_nb_context]; // event upt -> restore RAS, else restore others structure 63 // 63 // bool have_event [_param->_nb_context]; 64 64 bool ufpt_update [_param->_nb_context]; 65 65 bool upt_update [_param->_nb_context]; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r105 r106 39 39 reg_UFPT_UPDATE [i] = 0; 40 40 reg_UFPT_NB_NEED_UPDATE [i] = 0; 41 reg_UFPT_NB_UPDATE [i] = 0; 41 42 42 43 for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) … … 92 93 { 93 94 uint32_t bottom = reg_UPT_BOTTOM [i]; 94 bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); 95 bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); 95 bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END); 96 // bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); 97 // bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); 96 98 // event_state_t event_state = reg_EVENT_STATE [i]; 97 99 98 100 // Test if state is end 99 // if ((end_ok or end_ko) and 100 // ((event_state != EVENT_STATE_UPDATE_CONTEXT) and 101 // (event_state != EVENT_STATE_WAIT_END_EVENT))) 102 if (end_ok or end_ko) 101 // if (end_ok or end_ko) 102 if (end) 103 103 { 104 104 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); 105 105 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); 106 107 106 // Free slot 108 107 reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; … … 110 109 // Update pointer 111 110 reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; 112 111 113 112 if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i]) 114 113 reg_UPT_EMPTY [i] = true; // free a slot … … 118 117 119 118 if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) 120 // if (end_ko) // free121 119 { 122 120 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); … … 129 127 reg_UPT_EMPTY [i] = false; 130 128 } 129 131 130 } 132 131 } 133 132 } 133 134 134 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)"); 135 135 … … 450 450 // if free a slot, also all queue is updated 451 451 // Last slot ? 452 if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 452 // if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 453 if ((--reg_UFPT_NB_UPDATE [context])==0) 453 454 switch (reg_EVENT_STATE [context]) 454 455 { … … 472 473 473 474 reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; 474 475 475 476 476 // Update pointer 477 477 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); … … 531 531 else 532 532 { 533 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); 534 535 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; 536 533 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); 534 // reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; 535 536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); 537 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; 537 538 538 539 #ifdef STATISTICS … … 650 651 reg_EVENT_STATE [i] = EVENT_STATE_OK; 651 652 reg_IS_ACCURATE [i] = true; 652 653 // Tdepth_t depth = reg_UPT_TOP [i]; 654 655 #ifdef DEBUG_TEST 656 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) 657 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 653 654 Tdepth_t depth = reg_EVENT_UPT_PTR [i]; 655 656 if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO) 657 { 658 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth); 659 660 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END; 661 } 662 663 #ifdef DEBUG_TEST 664 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) 665 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 658 666 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO) 659 667 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 660 668 #endif 661 662 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth);663 664 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO;665 669 670 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); 671 672 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 673 666 674 break; 667 675 } … … 685 693 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 686 694 687 688 #ifdef DEBUG_TEST 689 if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)690 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 691 #endif 692 693 // flush all slot after the event 694 for (uint32_t j=depth;695 j!=top; 696 j=(j+1)%_param->_size_upt_queue[i])697 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;698 699 // test full :700 if (full)701 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;695 // Test empty 696 if (not reg_UPT_EMPTY [i]) 697 { 698 #ifdef DEBUG_TEST 699 if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 700 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 701 #endif 702 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 703 704 // flush all slot after the event 705 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 706 j!=top; 707 j=(j+1)%_param->_size_upt_queue[i]) 708 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 709 } 702 710 703 711 // reg_UPT_BOTTOM [i]; … … 802 810 { 803 811 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 804 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 805 812 { 813 reg_UFPT_NB_UPDATE [i] ++; 814 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 815 } 816 806 817 // TOP is next write slot : last slot is TOP-1 807 818 uint32_t top = reg_UFPT_TOP [i]; 808 reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;809 810 // reg_UFPT_BOTTOM [i];811 // reg_UFPT_TOP [i];819 reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; 820 821 // reg_UFPT_BOTTOM [i]; 822 // reg_UFPT_TOP [i]; 812 823 } 813 824 … … 853 864 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]); 854 865 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 866 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); 855 867 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) 856 868 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s", -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h
r95 r106 80 80 //public : uint32_t _size_context_id ; 81 81 //public : uint32_t _size_address ; 82 public : uint32_t * _array_size_depth ;//[nb_context] 82 83 public : uint32_t * _array_size_nb_inst_decod ;//[nb_decod_unit] 83 public : uint32_t * _array_size_depth ;//[nb_context]84 84 //public : uint32_t _max_size_depth ; 85 85 //public : uint32_t * _size_ifetch_queue_ptr ;//[nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
r95 r106 100 100 // _size_context_id = log2(_nb_context); 101 101 uint32_t size_instruction_address = size_general_data - 2; 102 102 103 103 _array_size_depth = new uint32_t [_nb_context]; 104 104 for (uint32_t i=0; i<_nb_context; i++) 105 105 _array_size_depth [i] = log2(_upt_size_queue[i]); 106 106 107 107 _array_size_nb_inst_decod = new uint32_t [_nb_decod_unit]; 108 108 for (uint32_t i=0; i<_nb_decod_unit; i++) … … 221 221 _nb_decod_unit, 222 222 _nb_inst_branch_complete, 223 _ array_size_depth,223 _upt_size_queue, 224 224 size_instruction_address, 225 225 _array_size_nb_inst_decod, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r105 r106 364 364 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 365 365 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 366 367 // if (entry->address_next != reg_PC_NEXT [front_end_id][context_id]) 368 // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); 366 369 } 367 370 … … 606 609 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); 607 610 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); 608 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x - %d %d",reg_PC_CURRENT [i][j], reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]);609 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x ",reg_PC_NEXT [i][j]);611 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 612 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 610 613 } 611 614 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r88 r106 79 79 80 80 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) 81 log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); 81 { 82 uint32_t limit = 4; 83 84 log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); 85 86 for (uint32_t i=0; i<_param->_nb_bank; ++i) 87 { 88 uint32_t j=0; 89 for (std::list<Tgeneral_address_t>::iterator it=_gpr_list->begin(); 90 it!=_gpr_list->end(); 91 ) 92 { 93 std::string str = ""; 94 95 for (uint32_t x=0; x<limit; x++) 96 { 97 if (it==_gpr_list->end()) 98 break; 99 else 100 str+=toString("GPR[%.4d][%.4d] : %.5d | ",i,j,*it); 101 ++it; 102 ++j; 103 } 104 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 105 } 106 } 82 107 83 for (uint32_t i=0; i<_param->_nb_bank; ++i) 108 for (uint32_t i=0; i<_param->_nb_bank; ++i) 109 { 110 uint32_t j=0; 111 for (std::list<Tspecial_address_t>::iterator it=_spr_list->begin(); 112 it!=_spr_list->end(); 113 ) 114 { 115 std::string str = ""; 116 117 for (uint32_t x=0; x<limit; x++) 118 { 119 if (it==_spr_list->end()) 120 break; 121 else 122 str+=toString("SPR[%.4d][%.4d] : %.5d | ",i,j,*it); 123 ++it; 124 ++j; 125 } 126 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 127 } 128 } 129 } 130 #endif 131 132 #ifdef DEBUG_TEST 133 if (1) 84 134 { 85 uint32_t j=0;86 for (std::list<Tgeneral_address_t>::iterator it=_gpr_list->begin();87 it!=_gpr_list->end();88 ++it)135 for (std::list<Tgeneral_address_t>::iterator it1=_gpr_list->begin(); 136 it1!=_gpr_list->end(); 137 ++it1 138 ) 89 139 { 90 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); 91 ++j; 140 std::list<Tgeneral_address_t>::iterator it2 = it1; 141 142 it2 ++; 143 while (it2 != _gpr_list->end()) 144 { 145 if (*it1 == *it2) 146 throw ERRORMORPHEO (FUNCTION,toString(_("In free list, Same GPR (%d)"),*it1)); 147 it2 ++; 148 } 149 } 150 151 for (std::list<Tspecial_address_t>::iterator it1=_spr_list->begin(); 152 it1!=_spr_list->end(); 153 ++it1 154 ) 155 { 156 std::list<Tspecial_address_t>::iterator it2 = it1; 157 158 it2 ++; 159 while (it2 != _spr_list->end()) 160 { 161 if (*it1 == *it2) 162 throw ERRORMORPHEO (FUNCTION,toString(_("In free list, Same SPR (%d)"),*it1)); 163 it2 ++; 164 } 92 165 } 93 166 } 94 for (uint32_t i=0; i<_param->_nb_bank; ++i) 95 { 96 uint32_t j=0; 97 for (std::list<Tspecial_address_t>::iterator it=_spr_list->begin(); 98 it!=_spr_list->end(); 99 ++it) 100 { 101 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); 102 ++j; 103 } 104 } 167 #endif 105 168 106 #endif107 169 } 108 170 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp
r104 r106 245 245 in_INSERT_WRITE_RE [i]->write(rand() % 2); 246 246 in_INSERT_NUM_REG_RD_LOG [i]->write((rand() % (_param->_nb_general_register_logic-1))+1); 247 in_INSERT_NUM_REG_RE_LOG [i]->write( rand() % _param->_nb_special_register_logic );248 in_INSERT_NUM_REG_RD_PHY [i]->write( rand() % _param->_nb_general_register);249 in_INSERT_NUM_REG_RE_PHY [i]->write( rand() % _param->_nb_special_register);247 in_INSERT_NUM_REG_RE_LOG [i]->write( rand() % _param->_nb_special_register_logic ); 248 in_INSERT_NUM_REG_RD_PHY [i]->write((rand() % (_param->_nb_general_register -1))+1); 249 in_INSERT_NUM_REG_RE_PHY [i]->write( rand() % _param->_nb_special_register ); 250 250 } 251 251 … … 285 285 if (in_INSERT_VAL [i]->read() and out_INSERT_ACK [i]->read()) 286 286 { 287 // ERROR BECAUSE write same register 287 288 if (in_INSERT_WRITE_RD [i]->read() == 1) 288 289 rat_gpr[front_end_id][context_id][in_INSERT_NUM_REG_RD_LOG[i]->read()] = in_INSERT_NUM_REG_RD_PHY[i]->read(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp
r104 r106 154 154 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 155 155 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 156 sensitive << (*(in_RETIRE_EVENT_STATE [i][j])); 156 sensitive << (*(in_RETIRE_EVENT_VAL [i][j])) 157 << (*(in_RETIRE_EVENT_STATE [i][j])); 157 158 158 159 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp
r104 r106 30 30 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 31 31 { 32 // An event occure 33 bool no_event = not (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) and (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)); 32 34 for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) 33 internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] ;35 internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k] and no_event; 34 36 for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) 35 internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] ;37 internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k] and no_event; 36 38 } 37 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
r104 r106 64 64 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; 65 65 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; 66 67 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); 68 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); 66 69 67 70 // Test if write 71 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",PORT_READ(in_INSERT_WRITE_RD [i])); 68 72 if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1) 69 rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); 73 { 74 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",PORT_READ(in_INSERT_NUM_REG_RD_PHY [i])); 75 rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); 76 } 77 78 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",PORT_READ(in_INSERT_WRITE_RE [i])); 70 79 if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1) 71 rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); 80 { 81 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",PORT_READ(in_INSERT_NUM_REG_RE_PHY [i])); 82 rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); 83 } 72 84 } 73 85 … … 109 121 Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); 110 122 123 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); 124 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); 125 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); 126 111 127 if (event_state != EVENT_STATE_NO_EVENT) 112 128 { 113 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);114 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id);115 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state);116 117 129 // Test if write and have not a previous update 118 130 if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) … … 150 162 151 163 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) 152 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); 153 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 154 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 155 { 156 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); 157 158 for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) 159 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); 160 161 for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) 162 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); 163 } 164 { 165 uint32_t limit = 4; 166 167 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); 168 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 169 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 170 { 171 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); 172 173 for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) 174 { 175 std::string str = ""; 176 for (uint32_t x=0; x<limit; x++) 177 { 178 uint32_t index = k+x; 179 if (index >= _param->_nb_general_register_logic) 180 break; 181 else 182 str+=toString("GPR[%.4d] - %.5d %.1d | ",index,rat_gpr[i][j][index],rat_gpr_update_table[i][j][index]); 183 } 184 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 185 } 186 187 for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) 188 { 189 std::string str = ""; 190 191 for (uint32_t x=0; x<limit; x++) 192 { 193 uint32_t index = k+x; 194 if (index >= _param->_nb_special_register_logic) 195 break; 196 else 197 str+=toString("SPR[%.4d] - %.5d %.1d | ",index,rat_spr[i][j][index],rat_spr_update_table[i][j][index]); 198 } 199 log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); 200 } 201 } 202 } 203 #endif 204 205 #ifdef DEBUG_TEST 206 if (1) 207 { 208 for (uint32_t i=0; i<_param->_nb_front_end; ++i) 209 for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 210 { 211 for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x) 212 for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) 213 if (rat_gpr[i][j][x] == rat_gpr[i][j][y]) 214 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr[%d][%d][%d] == rat_gpr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr[i][j][x])); 215 for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x) 216 for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) 217 if (rat_spr[i][j][x] == rat_spr[i][j][y]) 218 throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr[%d][%d][%d] == rat_spr[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr[i][j][x])); 219 } 220 221 } 164 222 #endif 165 223 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
r88 r106 49 49 if (PORT_READ(in_INSERT_VAL[i]) and internal_INSERT_ACK[i]) 50 50 { 51 log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); 52 51 53 if (PORT_READ(in_INSERT_READ_RA [i])) 52 54 { 53 55 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); 56 57 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 58 54 59 uint32_t bank = num_reg >> _param->_shift_gpr; 55 60 uint32_t reg = num_reg & _param->_mask_gpr ; … … 60 65 { 61 66 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); 67 68 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); 69 62 70 uint32_t bank = num_reg >> _param->_shift_gpr; 63 71 uint32_t reg = num_reg & _param->_mask_gpr ; … … 68 76 { 69 77 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); 78 79 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 80 70 81 uint32_t bank = num_reg >> _param->_shift_spr; 71 82 uint32_t reg = num_reg & _param->_mask_spr ; … … 76 87 { 77 88 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); 89 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg : %d",num_reg); 91 78 92 uint32_t bank = num_reg >> _param->_shift_gpr; 79 93 uint32_t reg = num_reg & _param->_mask_gpr ; … … 84 98 { 85 99 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); 100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg : %d",num_reg); 102 86 103 uint32_t bank = num_reg >> _param->_shift_spr; 87 104 uint32_t reg = num_reg & _param->_mask_spr ; … … 96 113 if (PORT_READ(in_RETIRE_VAL[i]) and internal_RETIRE_ACK[i]) 97 114 { 115 log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); 116 98 117 if (PORT_READ(in_RETIRE_READ_RA [i])) 99 118 { 100 119 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); 120 121 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 122 101 123 uint32_t bank = num_reg >> _param->_shift_gpr; 102 124 uint32_t reg = num_reg & _param->_mask_gpr ; … … 107 129 { 108 130 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); 131 132 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RD - num_reg : %d",num_reg); 133 109 134 uint32_t bank = num_reg >> _param->_shift_gpr; 110 135 uint32_t reg = num_reg & _param->_mask_gpr ; … … 115 140 { 116 141 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); 142 143 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 144 117 145 uint32_t bank = num_reg >> _param->_shift_spr; 118 146 uint32_t reg = num_reg & _param->_mask_spr ; … … 123 151 { 124 152 Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RD_PHY_OLD [i]); 153 154 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - restore_old : %d",restore_old); 155 125 156 { 126 157 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); 158 159 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_old : %d",num_reg); 160 127 161 uint32_t bank = num_reg >> _param->_shift_gpr; 128 162 uint32_t reg = num_reg & _param->_mask_gpr ; … … 131 165 { 132 166 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 167 168 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg_new : %d",num_reg); 169 133 170 uint32_t bank = num_reg >> _param->_shift_gpr; 134 171 uint32_t reg = num_reg & _param->_mask_gpr ; … … 140 177 { 141 178 Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RE_PHY_OLD [i]); 179 180 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - restore_old : %d",restore_old); 181 142 182 { 143 183 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); 184 185 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); 186 144 187 uint32_t bank = num_reg >> _param->_shift_spr; 145 188 uint32_t reg = num_reg & _param->_mask_spr ; … … 148 191 { 149 192 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 193 194 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new : %d",num_reg); 195 150 196 uint32_t bank = num_reg >> _param->_shift_spr; 151 197 uint32_t reg = num_reg & _param->_mask_spr ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_genMealy_read.cpp
r81 r106 15 15 namespace registerfile_monolithic { 16 16 17 #undef FUNCTION 18 #define FUNCTION "RegisterFile_Monolithic::genMealy_read" 17 19 void RegisterFile_Monolithic::genMealy_read (void) 18 20 { 19 log_printf(FUNC,RegisterFile,"genMealy_read","Begin"); 21 log_begin(RegisterFile_Monolithic,FUNCTION); 22 log_function(RegisterFile_Monolithic,FUNCTION,_name.c_str()); 20 23 21 24 for (uint32_t i=0; i<_param->_nb_port_read; i++) … … 31 34 Tdata_t data = reg_DATA[address]; 32 35 33 log_printf(TRACE,RegisterFile, "genMealy_read","[%d] -> %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));36 log_printf(TRACE,RegisterFile,FUNCTION," * [%d] -> %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 34 37 35 38 // Write in registerFile … … 38 41 else 39 42 { 40 //log_printf(TRACE,RegisterFile, "genMealy_read","Read [%d] : No transaction",i);43 //log_printf(TRACE,RegisterFile,FUNCTION,"Read [%d] : No transaction",i); 41 44 PORT_WRITE(out_READ_DATA[i],0); 42 45 } … … 60 63 data = reg_DATA[address]; 61 64 62 log_printf(TRACE,RegisterFile, "genMealy_read","[%d] -> %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));65 log_printf(TRACE,RegisterFile,FUNCTION," * [%d] -> %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 63 66 } 64 67 else 65 68 { 66 //log_printf(TRACE,RegisterFile, "genMealy_read","Read [%d] : No transaction",i);69 //log_printf(TRACE,RegisterFile,FUNCTION,"Read [%d] : No transaction",i); 67 70 data = 0; 68 71 } … … 71 74 } 72 75 73 log_printf(FUNC,RegisterFile,"genMealy_read","End"); 74 76 log_end(RegisterFile_Monolithic,FUNCTION); 75 77 }; 76 78 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp
r101 r106 14 14 namespace registerfile { 15 15 namespace registerfile_monolithic { 16 17 #undef FUNCTION 18 #define FUNCTION "RegisterFile_Monolithic::transition" 16 19 void RegisterFile_Monolithic::transition (void) 17 20 { 18 log_printf(FUNC,RegisterFile,"transition","Begin"); 21 log_begin(RegisterFile_Monolithic,FUNCTION); 22 log_function(RegisterFile_Monolithic,FUNCTION,_name.c_str()); 19 23 20 24 if (_param->_have_init_value and (PORT_READ(in_NRESET) == 0)) … … 38 42 Tdata_t data = PORT_READ(in_WRITE_DATA [i]); 39 43 40 log_printf(TRACE,RegisterFile, "transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));44 log_printf(TRACE,RegisterFile,FUNCTION," * [%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 41 45 42 46 // Write in registerFile … … 59 63 Tdata_t data = PORT_READ(in_READ_WRITE_WDATA [i]); 60 64 61 log_printf(TRACE,RegisterFile, "transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));65 log_printf(TRACE,RegisterFile,FUNCTION," * [%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 62 66 63 67 // Write in registerFile … … 82 86 #endif 83 87 88 #if defined(DEBUG_RegisterFile_Monolithic) and DEBUG_RegisterFile_Monolithic and (DEBUG >= DEBUG_TRACE) 89 { 90 log_printf(TRACE,RegisterFile,FUNCTION," * Dump RegisterFile"); 91 92 uint32_t limit = 4; 93 94 for (uint32_t i=0; i<_param->_nb_word; i+=limit) 95 { 96 std::string str = ""; 97 98 for (uint32_t j=0; j<limit; j++) 99 { 100 uint32_t index = i+j; 101 if (index >= _param->_nb_word) 102 break; 103 else 104 str+=toString("[%.4d] %.8x ",index,reg_DATA[index]); 105 } 106 107 log_printf(TRACE,RegisterFile,FUNCTION," %s",str.c_str()); 108 } 109 } 110 #endif 111 84 112 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 85 113 end_cycle(); 86 114 #endif 87 log_printf(FUNC,RegisterFile,"transition","End"); 115 116 log_end(RegisterFile_Monolithic,FUNCTION); 88 117 }; 89 118 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_read" 19 21 void RegisterFile_Multi_Banked::full_crossbar_genMealy_read (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 26 bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; … … 32 35 bool ack = false; 33 36 34 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","read[%d] : %d",i,val);37 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * read [%d] : %d",i,val); 35 38 36 39 if (val == true) … … 43 46 address = 0; 44 47 45 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* address : %d",address);48 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); 46 49 Taddress_t bank = address_bank (address); 47 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* bank : %d",bank );50 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); 48 51 49 52 // Search loop … … 59 62 Taddress_t num_reg = address_num_reg (address); 60 63 61 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* num_reg : %d",num_reg);62 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* bank_port : %d",j);64 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); 65 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j); 63 66 64 67 Tdata_t data = reg_DATA[bank][num_reg]; 65 68 66 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* data : %d",data);69 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * data : %d",data); 67 70 68 71 PORT_WRITE(out_READ_DATA [i], data); … … 77 80 } 78 81 79 log_ printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_read","End");82 log_end(RegisterFile_Multi_Banked,FUNCTION); 80 83 }; 81 84 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_write" 19 21 void RegisterFile_Multi_Banked::full_crossbar_genMealy_write (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 26 bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; … … 32 35 bool ack = false; 33 36 34 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_write","write[%d] : %d",i,val);37 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * write [%d] : %d",i,val); 35 38 36 39 if (val == true) … … 43 46 else 44 47 address = 0; 45 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_write","* address : %d",address);48 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); 46 49 Taddress_t bank = address_bank (address); 47 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_write","* bank : %d",bank );50 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); 48 51 49 52 // Search loop … … 60 63 Taddress_t num_reg = address_num_reg (address); 61 64 62 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_write","* num_reg : %d",num_reg);63 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_write","* bank_port : %d",j );65 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); 66 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j ); 64 67 65 68 internal_WRITE_NUM_REG [i] = num_reg; … … 77 80 } 78 81 79 log_ printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_genMealy_write","End");82 log_end(RegisterFile_Multi_Banked,FUNCTION); 80 83 }; 81 84 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_full_crossbar_transition.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::full_crossbar_genMealy_transition" 19 21 void RegisterFile_Multi_Banked::full_crossbar_transition (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_transition","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 log_ printf(FUNC,RegisterFile_Multi_Banked,"full_crossbar_transition","End");26 log_end(RegisterFile_Multi_Banked,FUNCTION); 24 27 }; 25 28 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_read.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::genMealy_read" 19 21 void RegisterFile_Multi_Banked::genMealy_read (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_read","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 26 // call function pointer 24 27 (this->*function_genMealy_read) (); 25 28 26 27 log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_read","End"); 29 log_end(RegisterFile_Multi_Banked,FUNCTION); 28 30 }; 29 31 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_genMealy_write.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::genMealy_write" 19 21 void RegisterFile_Multi_Banked::genMealy_write (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"genMealy_write","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 26 // call function pointer 24 27 (this->*function_genMealy_write) (); 25 28 26 log_ printf(FUNC,RegisterFile_Multi_Banked,"genMealy_write","End");29 log_end(RegisterFile_Multi_Banked,FUNCTION); 27 30 }; 28 31 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::partial_crossbar_genMealy_read" 19 21 void RegisterFile_Multi_Banked::partial_crossbar_genMealy_read (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_read","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 26 bool read_port_use [_param->_nb_bank][_param->_nb_port_read_by_bank]; … … 32 35 bool ack = false; 33 36 34 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","read[%d] : %d",i,val);37 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * read [%d] : %d",i,val); 35 38 36 39 if (val == true) … … 42 45 else 43 46 address = 0; 44 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* address : %d",address);47 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); 45 48 Taddress_t bank = address_bank (address); 46 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* bank : %d",bank );49 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); 47 50 48 51 // // Search loop … … 61 64 Taddress_t num_reg = address_num_reg (address); 62 65 63 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* num_reg : %d",num_reg);64 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* bank_port : %d",j);66 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); 67 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j); 65 68 66 69 Tdata_t data = reg_DATA[bank][num_reg]; 67 70 68 log_printf(TRACE,RegisterFile_Multi_Banked, "full_crossbar_genMealy_read","* data : %d",data);71 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * data : %d",data); 69 72 70 73 PORT_WRITE(out_READ_DATA [i], data); … … 79 82 } 80 83 81 log_ printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_read","End");84 log_end(RegisterFile_Multi_Banked,FUNCTION); 82 85 }; 83 86 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::partial_crossbar_genMealy_write" 19 21 void RegisterFile_Multi_Banked::partial_crossbar_genMealy_write (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 26 bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank]; … … 31 34 bool ack = false; 32 35 33 log_printf(TRACE,RegisterFile_Multi_Banked, "partial_crossbar_genMealy_write","write[%d] : %d",i,val);36 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * write [%d] : %d",i,val); 34 37 35 38 if (val == true) … … 42 45 else 43 46 address = 0; 44 log_printf(TRACE,RegisterFile_Multi_Banked, "partial_crossbar_genMealy_write","* address : %d",address);47 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * address : %d",address); 45 48 Taddress_t bank = address_bank (address); 46 log_printf(TRACE,RegisterFile_Multi_Banked, "partial_crossbar_genMealy_write","* bank : %d",bank );49 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank : %d",bank ); 47 50 48 51 // // Search loop … … 61 64 Taddress_t num_reg = address_num_reg (address); 62 65 63 log_printf(TRACE,RegisterFile_Multi_Banked, "partial_crossbar_genMealy_write","* num_reg : %d",num_reg);64 log_printf(TRACE,RegisterFile_Multi_Banked, "partial_crossbar_genMealy_write","* bank_port : %d",j );66 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * num_reg : %d",num_reg); 67 log_printf(TRACE,RegisterFile_Multi_Banked,FUNCTION," * bank_port : %d",j ); 65 68 66 69 internal_WRITE_NUM_REG [i] = num_reg; … … 79 82 } 80 83 81 log_ printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","End");84 log_end(RegisterFile_Multi_Banked,FUNCTION); 82 85 }; 83 86 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_transition.cpp
r81 r106 17 17 18 18 19 #undef FUNCTION 20 #define FUNCTION "RegisterFile_Multi_Banked::partial_crossbar_transition" 19 21 void RegisterFile_Multi_Banked::partial_crossbar_transition (void) 20 22 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_transition","Begin"); 23 log_begin(RegisterFile_Multi_Banked,FUNCTION); 24 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 25 23 log_ printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_transition","End");26 log_end(RegisterFile_Multi_Banked,FUNCTION); 24 27 }; 25 28 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_transition.cpp
r81 r106 16 16 namespace registerfile_multi_banked { 17 17 18 18 #undef FUNCTION 19 #define FUNCTION "RegisterFile_Multi_Banked::transition" 19 20 void RegisterFile_Multi_Banked::transition (void) 20 21 { 21 log_printf(FUNC,RegisterFile_Multi_Banked,"transition","Begin"); 22 log_begin(RegisterFile_Multi_Banked,FUNCTION); 23 log_function(RegisterFile_Multi_Banked,FUNCTION,_name.c_str()); 22 24 23 25 // call function pointer … … 35 37 } 36 38 39 #if defined(DEBUG_RegisterFile_Multi_Banked) and DEBUG_RegisterFile_Multi_Banked and (DEBUG >= DEBUG_TRACE) 40 { 41 log_printf(TRACE,RegisterFile,FUNCTION," * Dump RegisterFile"); 42 43 uint32_t limit = 4; 44 45 for (uint32_t i=0; i<_param->_nb_bank; i++) 46 { 47 48 log_printf(TRACE,RegisterFile,FUNCTION," Bank %d",i); 49 50 for (uint32_t j=0; j<_param->_nb_word_by_bank; j+=limit) 51 { 52 std::string str = ""; 53 54 for (uint32_t k=0; k<limit; k++) 55 { 56 uint32_t index = j+k; 57 if (index >= _param->_nb_word) 58 break; 59 else 60 str+=toString("[%.4d] %.8x ",index,reg_DATA[i][index]); 61 } 62 63 log_printf(TRACE,RegisterFile,FUNCTION," %s",str.c_str()); 64 } 65 } 66 } 67 #endif 68 37 69 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 38 70 end_cycle(); 39 71 #endif 40 72 41 log_ printf(FUNC,RegisterFile_Multi_Banked,"transition","End");73 log_end(RegisterFile_Multi_Banked,FUNCTION); 42 74 }; 43 75 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r105 r106 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION "10 5"12 #define MORPHEO_REVISION "106" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY "0 5"15 #define MORPHEO_DATE_DAY "09" 16 16 #define MORPHEO_DATE_MONTH "02" 17 17 #define MORPHEO_DATE_YEAR "2009" -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg
r105 r106 76 76 <parameter name="nb_inst_branch_decod" value="1" /> 77 77 <parameter name="nb_inst_branch_update" value="1" /> 78 <parameter name="btb_size_queue" value=" 1" />78 <parameter name="btb_size_queue" value="4" /> 79 79 <parameter name="btb_associativity" value="1" /> 80 80 <parameter name="btb_size_counter" value="2" /> 81 <parameter name="btb_victim_scheme" value=" 1" />82 <parameter name="dir_predictor_scheme" value=" 3" />81 <parameter name="btb_victim_scheme" value="3" /> 82 <parameter name="dir_predictor_scheme" value="1" /> 83 83 84 84 <predictor id="0"> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r105 r106 15 15 <parameter name="statistics_period" value="0" /> 16 16 17 <parameter name="simulation_nb_cycle" value=" 100000" />17 <parameter name="simulation_nb_cycle" value="50000" /> 18 18 <parameter name="simulation_nb_instruction" value="0" /> 19 19 … … 24 24 25 25 <parameter name="debug_level" value="0" /> 26 <parameter name="debug_cycle_start" value=" 0" />27 <parameter name="debug_cycle_stop" value=" 200" />26 <parameter name="debug_cycle_start" value="800" /> 27 <parameter name="debug_cycle_stop" value="1000" /> 28 28 <parameter name="debug_have_log_file" value="0" /> 29 29 -
trunk/Softwares/Test/Test_046/src/sys/crt0.s
r102 r106 39 39 l.ori r1, r1, lo(_stack) 40 40 41 l.movhi r2, hi(0x000000 10) /* iteration */42 l.ori r2, r2, lo(0x000000 10)41 l.movhi r2, hi(0x0000002) /* iteration */ 42 l.ori r2, r2, lo(0x0000002) 43 43 44 44 l.movhi r3, hi(0xdeadbeef) /* data */
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