Changeset 107
- Timestamp:
- Feb 11, 2009, 12:03:25 AM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 19 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r105 r107 67 67 (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) 68 68 { 69 predict_val [i] = false;69 // predict_val [i] = false; 70 70 71 71 Tcontext_t x = it->grp; … … 106 106 107 107 instruction_decod (_decod_instruction, _decod_param[x]); 108 109 log_printf(TRACE,Decod,FUNCTION," * address_next : %.8x (%.8x)",_decod_instruction->_address_next,(_decod_instruction->_address_next<<2)); 108 110 } 109 111 else … … 167 169 { 168 170 log_printf(TRACE,Decod,FUNCTION," * type is branch"); 171 log_printf(TRACE,Decod,FUNCTION," * predict_val : %d",ifetch_ack [x][y]); 169 172 log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i])); 170 173 171 174 log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); 172 175 log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); 173 176 174 177 predict_val [i] = ifetch_ack [x][y] // and decod_val [i] 175 178 ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp
r88 r107 29 29 xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); 30 30 xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod )); xml.singleton_end(); 31 xml.singleton_begin("nb_branch_speculated "); xml.attribut("value",toString(_nb_branch_speculated )); xml.singleton_end();32 31 // xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); 33 32 xml.singleton_begin("nb_context_select "); xml.attribut("value",toString(_nb_context_select )); xml.singleton_end(); … … 43 42 xml. balise_open_end(); 44 43 xml. singleton_begin("nb_inst_fetch "); xml.attribut("value",toString(_nb_inst_fetch [i])); xml.singleton_end(); 44 xml. singleton_begin("nb_branch_speculated "); xml.attribut("value",toString(_nb_branch_speculated [i])); xml.singleton_end(); 45 45 xml. balise_close(); 46 46 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
r101 r107 267 267 LABEL(" * address wait : %.8x",a_addr); 268 268 269 TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr );269 TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr-a_addr%_param->_nb_instruction); 270 270 for (uint32_t i=0; i<_param->_nb_instruction; i++) 271 271 TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp
r101 r107 30 30 internal_ADDRESS_VAL = reg_PC_ACCESS_VAL; 31 31 32 PORT_WRITE(out_ADDRESS_VAL ,internal_ADDRESS_VAL ); 33 PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS ,reg_PC_ACCESS ); 32 PORT_WRITE(out_ADDRESS_VAL ,internal_ADDRESS_VAL ); 33 // Align pc on instruction packet address. 34 PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS ,reg_PC_ACCESS - (reg_PC_ACCESS%_param->_nb_instruction)); 34 35 if (_param->_have_port_inst_ifetch_ptr) 35 36 PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR ,reg_PC_ACCESS_INST_IFETCH_PTR ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
r101 r107 35 35 reg_PC_NEXT = 0x100>>2; 36 36 reg_PC_NEXT_IS_DS_TAKE = 0; 37 reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1;38 for (uint32_t i= 1; i<_param->_nb_instruction; i++)37 uint32_t index = reg_PC_NEXT % _param->_nb_instruction; 38 for (uint32_t i=0; i<_param->_nb_instruction; i++) 39 39 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 40 reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; 40 41 reg_PC_NEXT_INST_IFETCH_PTR = 0; 41 42 reg_PC_NEXT_BRANCH_STATE = 0; … … 182 183 // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; 183 184 184 reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. 185 for (uint32_t i=1; i<_param->_nb_instruction; i++) 186 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 185 // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. 186 uint32_t index = reg_PC_NEXT % _param->_nb_instruction; 187 for (uint32_t i=0; i<_param->_nb_instruction; i++) 188 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 189 reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; 187 190 188 191 reg_PC_NEXT_NEXT_VAL = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp
r88 r107 92 92 93 93 // detect new branch !!! insert in branch target buffer 94 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); 95 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); 96 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); 94 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); 95 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * miss_pred : %d",miss_pred); 96 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); 97 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); 97 98 98 99 Tcounter_t accurate_new = 0; … … 106 107 // * in all case : is valid in this step 107 108 Tcounter_t accurate_old = reg_BTB[num_bank][num_entry]._accurate; 109 110 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * accurate_old : %d",accurate_old); 111 108 112 // hit : increase accurate 109 113 // miss : decrease accurate 110 Tcounter_taccurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old);114 accurate_new = (miss_pred)?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); 111 115 112 116 // test if accurate go to the threshold 113 117 if ((accurate_old >= _param->_accurate_limit) and 114 118 (accurate_new < _param->_accurate_limit)) 115 accurate_new = 0; 119 { 120 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * decrease downto the accurate_limid (%d)",_param->_accurate_limit); 121 accurate_new = 0; 122 } 116 123 117 124 //reg_BTB[num_bank][num_entry]._val : no update because hit … … 135 142 // reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); 136 143 // reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); 137 144 // reg_BTB[num_bank][num_entry]._address_dest_val = 0; 138 145 } 139 146 … … 144 151 // reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); 145 152 // } 153 154 log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * accurate_new : %d",accurate_new); 155 146 156 reg_BTB[num_bank][num_entry]._val = 1; 147 157 reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp
r88 r107 92 92 PORT_WRITE(out_PREDICT_ACK [i], 1); 93 93 94 // constant direction : never / always94 // constant direction : never / always 95 95 switch (_param->_predictor_scheme) 96 96 { … … 166 166 167 167 # ifdef SYSTEMCASS_SPECIFIC 168 // List dependency information169 for (uint32_t i=0; i<_param->_nb_inst_predict; i++)170 {171 172 switch (_param->_predictor_scheme)173 {174 case PREDICTOR_STATIC :175 {176 (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_STATIC [i]));177 178 break;179 }180 case PREDICTOR_LAST_TAKE :181 {182 (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_LAST_TAKE [i]));183 184 break;185 }186 case PREDICTOR_COUNTER :187 case PREDICTOR_LOCAL :188 case PREDICTOR_GLOBAL :189 case PREDICTOR_META :190 case PREDICTOR_CUSTOM :191 {192 (*(out_PREDICT_ACK [i])) (*(in_PREDICT_PREDICTOR_ACK [i]));193 (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_HISTORY [i]));194 (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_DIRECTION [i]));195 (*(out_PREDICT_PREDICTOR_VAL [i])) (*(in_PREDICT_VAL [i]));196 (*(out_PREDICT_PREDICTOR_ADDRESS_SRC [i])) (*(in_PREDICT_ADDRESS_SRC [i]));197 198 break;199 }200 default :201 {202 break;203 }204 }205 }168 // // List dependency information 169 // for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 170 // { 171 172 // switch (_param->_predictor_scheme) 173 // { 174 // case PREDICTOR_STATIC : 175 // { 176 // (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_STATIC [i])); 177 178 // break; 179 // } 180 // case PREDICTOR_LAST_TAKE : 181 // { 182 // (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_LAST_TAKE [i])); 183 184 // break; 185 // } 186 // case PREDICTOR_COUNTER : 187 // case PREDICTOR_LOCAL : 188 // case PREDICTOR_GLOBAL : 189 // case PREDICTOR_META : 190 // case PREDICTOR_CUSTOM : 191 // { 192 // (*(out_PREDICT_ACK [i])) (*(in_PREDICT_PREDICTOR_ACK [i])); 193 // (*(out_PREDICT_HISTORY [i])) (*(in_PREDICT_PREDICTOR_HISTORY [i])); 194 // (*(out_PREDICT_DIRECTION [i])) (*(in_PREDICT_PREDICTOR_DIRECTION [i])); 195 // (*(out_PREDICT_PREDICTOR_VAL [i])) (*(in_PREDICT_VAL [i])); 196 // (*(out_PREDICT_PREDICTOR_ADDRESS_SRC [i])) (*(in_PREDICT_ADDRESS_SRC [i])); 197 198 // break; 199 // } 200 // default : 201 // { 202 // break; 203 // } 204 // } 205 // } 206 206 # endif 207 207 } … … 222 222 223 223 # ifdef SYSTEMCASS_SPECIFIC 224 // List dependency information225 for (uint32_t i=0; i<_param->_nb_inst_update; i++)226 {227 (*(out_UPDATE_PREDICTOR_VAL [i])) (*(in_UPDATE_VAL [i]));228 (*(out_UPDATE_ACK [i])) (*(in_UPDATE_PREDICTOR_ACK [i]));229 (*(out_UPDATE_PREDICTOR_ADDRESS [i])) (*(in_UPDATE_ADDRESS [i]));230 (*(out_UPDATE_PREDICTOR_HISTORY [i])) (*(in_UPDATE_HISTORY [i]));231 (*(out_UPDATE_PREDICTOR_DIRECTION [i])) (*(in_UPDATE_DIRECTION [i]));232 }224 // // List dependency information 225 // for (uint32_t i=0; i<_param->_nb_inst_update; i++) 226 // { 227 // (*(out_UPDATE_PREDICTOR_VAL [i])) (*(in_UPDATE_VAL [i])); 228 // (*(out_UPDATE_ACK [i])) (*(in_UPDATE_PREDICTOR_ACK [i])); 229 // (*(out_UPDATE_PREDICTOR_ADDRESS [i])) (*(in_UPDATE_ADDRESS [i])); 230 // (*(out_UPDATE_PREDICTOR_HISTORY [i])) (*(in_UPDATE_HISTORY [i])); 231 // (*(out_UPDATE_PREDICTOR_DIRECTION [i])) (*(in_UPDATE_DIRECTION [i])); 232 // } 233 233 # endif 234 234 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_predict.cpp
r81 r107 23 23 void Direction_Glue::genMealy_predict (void) 24 24 { 25 log_printf(FUNC,Direction_Glue,FUNCTION,"Begin"); 25 log_begin(Direction_Glue,FUNCTION); 26 log_function(Direction_Glue,FUNCTION,_name.c_str()); 26 27 27 28 // constant direction : never / always 28 switch (_param->_predictor_scheme)29 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 29 30 { 30 case PREDICTOR_STATIC : 31 { 32 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 33 PORT_WRITE(out_PREDICT_DIRECTION [i], PORT_READ(in_PREDICT_STATIC [i])); 34 35 break; 36 } 37 case PREDICTOR_LAST_TAKE : 38 { 39 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 40 PORT_WRITE(out_PREDICT_DIRECTION [i], PORT_READ(in_PREDICT_LAST_TAKE [i])); 31 log_printf(TRACE,Direction_Glue,FUNCTION," * PREDICT [%d]",i); 41 32 42 break; 43 } 44 case PREDICTOR_COUNTER : 45 case PREDICTOR_LOCAL : 46 case PREDICTOR_GLOBAL : 47 case PREDICTOR_META : 48 case PREDICTOR_CUSTOM : 49 { 50 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 51 { 52 // not use : 53 // in_PREDICT_LAST_TAKE 54 // in_PREDICT_STATIC 33 Tcontrol_t direction; 34 35 switch (_param->_predictor_scheme) 36 { 37 // defined as constant in Direction_Glue.cpp 38 // case PREDICTOR_NEVER_TAKE : 39 // { 40 // direction = 0; 41 // break; 42 // } 43 // case PREDICTOR_ALWAYS_TAKE : 44 // { 45 // direction = 1; 46 // break; 47 // } 48 case PREDICTOR_STATIC : 49 { 50 direction = PORT_READ(in_PREDICT_STATIC [i]); 51 break; 52 } 53 case PREDICTOR_LAST_TAKE : 54 { 55 direction = PORT_READ(in_PREDICT_LAST_TAKE [i]); 56 break; 57 } 58 case PREDICTOR_COUNTER : 59 case PREDICTOR_LOCAL : 60 case PREDICTOR_GLOBAL : 61 case PREDICTOR_META : 62 case PREDICTOR_CUSTOM : 63 { 64 // not use : 65 // in_PREDICT_LAST_TAKE 66 // in_PREDICT_STATIC 67 68 direction = PORT_READ(in_PREDICT_PREDICTOR_DIRECTION [i]); 55 69 56 70 PORT_WRITE(out_PREDICT_PREDICTOR_VAL [i], PORT_READ(in_PREDICT_VAL [i])); … … 58 72 PORT_WRITE(out_PREDICT_PREDICTOR_ADDRESS_SRC [i], PORT_READ(in_PREDICT_ADDRESS_SRC [i])); 59 73 PORT_WRITE(out_PREDICT_HISTORY [i], PORT_READ(in_PREDICT_PREDICTOR_HISTORY [i])); 60 PORT_WRITE(out_PREDICT_DIRECTION [i], PORT_READ(in_PREDICT_PREDICTOR_DIRECTION [i])); 61 } 74 75 break; 76 } 77 default : 78 { 79 ERRORMORPHEO(FUNCTION,"No valid predictor scheme"); 80 break; 81 } 82 } 83 84 log_printf(TRACE,Direction_Glue,FUNCTION," * direction : %d",direction); 62 85 63 break; 64 } 65 default : 66 { 67 ERRORMORPHEO(FUNCTION,"No valid predictor scheme"); 68 break; 69 } 86 PORT_WRITE(out_PREDICT_DIRECTION [i], direction); 70 87 } 71 88 72 73 74 log_printf(FUNC,Direction_Glue,FUNCTION,"End"); 89 log_end(Direction_Glue,FUNCTION); 75 90 }; 76 91 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_update.cpp
r81 r107 23 23 void Direction_Glue::genMealy_update (void) 24 24 { 25 log_printf(FUNC,Direction_Glue,FUNCTION,"Begin"); 25 log_begin(Direction_Glue,FUNCTION); 26 log_function(Direction_Glue,FUNCTION,_name.c_str()); 26 27 27 28 for (uint32_t i=0; i<_param->_nb_inst_update; i++) … … 34 35 } 35 36 36 log_ printf(FUNC,Direction_Glue,FUNCTION,"End");37 log_end(Direction_Glue,FUNCTION); 37 38 }; 38 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp
r98 r107 50 50 uint32_t port = 0; 51 51 for (uint32_t i=0; i<_param->_nb_inst_decod[decod_unit]; i++) 52 { 53 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d]",decod_unit,i); 54 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * val : %d",PORT_READ(in_DECOD_VAL [decod_unit][i])); 55 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * port : %d",port); 56 52 57 // Test if decod_unit have detected a branch 53 58 if ((port>=_param->_nb_inst_branch_decod) or 54 59 (PORT_READ(in_DECOD_VAL [decod_unit][i]) == 0)) 55 60 { 56 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d]: not valid",decod_unit,i);61 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d] : not valid",decod_unit,i); 57 62 ack [i] = false; 58 63 } … … 74 79 Tcontrol_t miss_decod = (branch_state == BRANCH_STATE_NONE); 75 80 76 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d] :valid",decod_unit,i);81 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD [%d][%d] : valid",decod_unit,i); 77 82 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch_state : %d",branch_state); 78 83 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * match_inst_ifetch_ptr : %d",match_inst_ifetch_ptr); … … 246 251 PORT_WRITE(out_DECOD_UPT_UPDATE_PREDICTION_ID [port],depth); 247 252 248 port ++; 253 port ++; // have find port 249 254 } 255 } 250 256 251 257 // Write output 252 253 258 for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) 254 259 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
r106 r107 117 117 // if pc_current is a delay slot, then pc_previous is a branchement instruction, also hit must be set. 118 118 // else : an another branch instruction have eject this branch : can't accurate 119 Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); 120 Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); 119 Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); 120 Tcontrol_t is_accurate = not (pc_current_is_ds_take and not hit); 121 Tcontrol_t btb_is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]); 121 122 122 123 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit : %d" ,hit); 123 124 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); 125 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_is_accurate : %d" ,btb_is_accurate); 124 126 125 127 // STEP (3) : Test if BTB find a branch instruction in the packet … … 158 160 else 159 161 { 162 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is not in the last slot of the packet"); 163 160 164 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 161 165 Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); … … 166 170 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src ,address_src <<2); 167 171 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x (0x%.8x)",address_dest,address_dest<<2); 168 172 169 173 switch (condition) 170 174 { … … 178 182 pc_next = address_dest; 179 183 branch_state = BRANCH_STATE_NSPEC_TAKE; 184 // is_accurate &= btb_is_accurate; 185 180 186 break; 181 187 } … … 190 196 pc_next = address_dest; 191 197 branch_state = BRANCH_STATE_NSPEC_TAKE; 198 // is_accurate &= btb_is_accurate; 199 192 200 break; 193 201 } … … 201 209 // Test direction 202 210 direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same 203 if (direction = 1)211 if (direction == 1) 204 212 { 205 213 branch_state = BRANCH_STATE_SPEC_TAKE; … … 211 219 pc_next = address_src+2; // +1 = delay slot 212 220 } 221 222 // is_accurate &= btb_is_accurate; 213 223 break; 214 224 } … … 223 233 pc_next = address_dest; 224 234 branch_state = BRANCH_STATE_SPEC_TAKE; 235 is_accurate &= btb_is_accurate; 236 225 237 break; 226 238 } … … 235 247 pc_next = address_dest; 236 248 branch_state = BRANCH_STATE_NSPEC_TAKE; 249 is_accurate &= btb_is_accurate; 250 237 251 break; 238 252 } … … 244 258 push = false; 245 259 direction = true; 246 pc_next = PORT_READ(in_PREDICT_RAS_ ADDRESS_POP [i]);260 pc_next = PORT_READ(in_PREDICT_RAS_HIT [i])?PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]):address_dest; 247 261 branch_state = BRANCH_STATE_SPEC_TAKE; 262 is_accurate &= (PORT_READ(in_PREDICT_RAS_HIT [i]) or btb_is_accurate); // if miss - prediction is not accurate 263 248 264 break; 249 265 } … … 255 271 } 256 272 273 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * direction : %d",direction); 274 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch_state : %d",branch_state); 275 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next : %.8x",pc_next); 276 257 277 if (use_dir) 258 278 { … … 270 290 PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); 271 291 PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 272 273 is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate274 292 } 275 293 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp
r100 r107 363 363 in_UPDATE_VAL [port3]->write(1); 364 364 in_UPDATE_FLUSH[port3]->write(1); 365 in_UPDATE_PUSH [port3]->write(0); 365 366 for (uint32_t i=0; i<_param->_nb_context; i++) 366 367 for (uint32_t j=0; j<_param->_size_queue[i]/2; j++) … … 582 583 LABEL("Update FLUSH"); 583 584 in_UPDATE_VAL [port3]->write(1); 585 in_UPDATE_PUSH [port3]->write(0); 584 586 in_UPDATE_FLUSH[port3]->write(1); 585 587 for (uint32_t i=0; i<_param->_nb_context; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
r100 r107 237 237 if (flush) 238 238 { 239 Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 240 Tptr_t value = (push)?1:0; 241 239 242 // All pointer is set at 0 240 reg_TOP [context_id] = 0;243 reg_TOP [context_id] = value; 241 244 // reg_BOTTOM [context_id] = 0; 242 reg_NB_ELT [context_id] = 0;243 244 reg_PREDICT_TOP [context_id] = 0;245 reg_NB_ELT [context_id] = value; 246 247 reg_PREDICT_TOP [context_id] = value; 245 248 // reg_PREDICT_BOTTOM [context_id] = 0; 246 reg_PREDICT_NB_ELT [context_id] = 0; 249 reg_PREDICT_NB_ELT [context_id] = value; 250 251 if (push) 252 { 253 // reinsert push value 254 reg_stack [context_id][0]._address = PORT_READ(in_UPDATE_ADDRESS [i]); 255 } 247 256 } 248 257 else … … 313 322 // previous is push, now must be pop 314 323 315 // Test if the stack is empty 316 if (nb_elt_old>0) // ??324 // Test if the stack is empty (if previous flush) 325 if (nb_elt_old>0) 317 326 { 318 327 top_new = (top_old==0)?(_param->_size_queue[context_id]-1):(top_old-1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r106 r107 1005 1005 request.address_dest = 0x21071981+i; 1006 1006 request.address_good = request.address_dest; 1007 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 1007 request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK: 1008 BRANCH_CONDITION_FLAG_SET; 1008 1009 1009 1010 have_ras |= (update_ras(request.condition)); … … 1451 1452 request.address_dest = rand(); 1452 1453 1453 request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET; 1454 request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK: 1455 BRANCH_CONDITION_FLAG_SET; 1454 1456 1455 1457 request.take = 1; … … 1597 1599 request.address_dest = rand(); 1598 1600 request.address_good = request.address_dest; 1599 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 1601 request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK: 1602 BRANCH_CONDITION_FLAG_SET; 1600 1603 1601 1604 have_ufpt_ras |= (update_ras(request.condition)); … … 2157 2160 request.address_dest = rand(); 2158 2161 2159 request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET; 2162 request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK: 2163 BRANCH_CONDITION_FLAG_SET; 2160 2164 2161 2165 request.take = 1; … … 2303 2307 request.address_dest = rand(); 2304 2308 request.address_good = request.address_dest; 2305 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 2309 request.condition = // (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK: 2310 BRANCH_CONDITION_FLAG_SET; 2306 2311 2307 2312 have_ufpt_ras |= (update_ras(request.condition)); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r106 r107 175 175 Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK ) or 176 176 (state == UPDATE_PREDICTION_STATE_KO )); 177 Tcontrol_t state_is_event = ((state == UPDATE_PREDICTION_STATE_KO ) or178 (state == UPDATE_PREDICTION_STATE_EVENT)// or177 // Tcontrol_t state_is_event = ((state == UPDATE_PREDICTION_STATE_KO ) or 178 // (state == UPDATE_PREDICTION_STATE_EVENT)// or 179 179 // ((have_event[context])?(state == UPDATE_PREDICTION_STATE_OK):false) 180 );181 182 Tcontrol_t state_is_event_update = state_is_event and need_update(condition);183 Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition);180 // ); 181 182 // Tcontrol_t state_is_event_update = state_is_event and need_update(condition); 183 // Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition); 184 184 185 185 if (retire_ras_from_upt [context]) 186 186 { 187 val = state_is_event_update; 188 val_without_ack = state_is_event_no_update; 187 // val = state_is_event_update; 188 // val_without_ack = state_is_event_no_update; 189 val = ((state == UPDATE_PREDICTION_STATE_KO ) or 190 ((state == UPDATE_PREDICTION_STATE_EVENT) and need_update(condition))); 191 val_without_ack = ((state == UPDATE_PREDICTION_STATE_EVENT) and not need_update(condition)); 189 192 } 190 193 else … … 205 208 ras_flush = (state == UPDATE_PREDICTION_STATE_KO); // miss prediction, RAS is corrupted 206 209 ras_push = push_ras(condition); 207 ras_address = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; 210 // If corrupt, RAS must be flushed. 211 // Also, if instruction l.jal, l.jalr, push addr+2 (delay slot), else (no flush) restore RAS 212 ras_address = (ras_flush)?(reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src+2):reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; 208 213 ras_index = reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras; 209 214 ras_prediction_ifetch = ifetch; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r106 r107 422 422 423 423 // In all case : update good_take 424 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; 424 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; 425 426 // Write address_dest if need read register 427 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 428 429 if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or 430 (condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or 431 (condition == BRANCH_CONDITION_READ_STACK ) ) 432 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; 425 433 } 426 434 … … 599 607 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i); 600 608 601 #ifdef DEBUG_TEST 602 if (reg_EVENT_STATE [i] != EVENT_STATE_UPDATE_CONTEXT) 603 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 604 #endif 605 606 // Change state 607 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i); 608 609 reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT; 609 // if different : an other branch is occured 610 if (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT) 611 { 612 // Change state 613 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i); 614 615 reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT; 616 } 610 617 } 611 618 … … 866 873 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); 867 874 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) 868 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x%.4d - %s",875 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s", 869 876 j, 870 877 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition, 871 878 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src, 879 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2, 872 880 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest, 881 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2, 873 882 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take, 874 883 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate, 875 884 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history, 876 885 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras, 886 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2, 877 887 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras, 878 888 toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str() … … 886 896 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 887 897 for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) 888 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x%.4d - %s",898 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8d %.8x (%.8x) %.4d - %s", 889 899 j, 890 900 reg_UPDATE_PREDICTION_TABLE [i][j]._condition, 891 901 reg_UPDATE_PREDICTION_TABLE [i][j]._address_src, 902 reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2, 892 903 reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest, 904 reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2, 893 905 reg_UPDATE_PREDICTION_TABLE [i][j]._last_take, 894 906 reg_UPDATE_PREDICTION_TABLE [i][j]._good_take, … … 896 908 reg_UPDATE_PREDICTION_TABLE [i][j]._history, 897 909 reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras, 910 reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2, 898 911 reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras, 899 912 toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str() -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r106 r107 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION "10 6"12 #define MORPHEO_REVISION "107" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY " 09"15 #define MORPHEO_DATE_DAY "11" 16 16 #define MORPHEO_DATE_MONTH "02" 17 17 #define MORPHEO_DATE_YEAR "2009" -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg
r106 r107 5 5 <thread id="0"> 6 6 <parameter name="size_ifetch_queue" value="4" /> 7 <parameter name="nb_inst_fetch" value=" 1" />7 <parameter name="nb_inst_fetch" value="2" /> 8 8 <parameter name="ras_size_queue" value="4" /> 9 9 <parameter name="upt_size_queue" value="4" /> … … 80 80 <parameter name="btb_size_counter" value="2" /> 81 81 <parameter name="btb_victim_scheme" value="3" /> 82 <parameter name="dir_predictor_scheme" value=" 1" />82 <parameter name="dir_predictor_scheme" value="3" /> 83 83 84 84 <predictor id="0"> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r106 r107 24 24 25 25 <parameter name="debug_level" value="0" /> 26 <parameter name="debug_cycle_start" value=" 800" />27 <parameter name="debug_cycle_stop" value=" 1000" />26 <parameter name="debug_cycle_start" value="310" /> 27 <parameter name="debug_cycle_stop" value="350" /> 28 28 <parameter name="debug_have_log_file" value="0" /> 29 29
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