Changeset 108 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp

Timestamp:

Feb 12, 2009, 12:55:06 PM (15 years ago)

Author:

rosiere

Message:

1) decod_queue : add reg_LAST_SLOT.
2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not)
3) Context State / UPT : Branch miss and Load miss in same cycle.
4) Free List : Bank is on LSB not MSB.
5) Platforms : move data

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp

@@ -33 +33 @@
         Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR      ) or
                                        (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or
+                                       (state == CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR) or
                                        (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR  ) or
                                        (state == CONTEXT_STATE_KO_PSYNC_ADDR      ) or 
@@ -53 +54 @@
           {
           case CONTEXT_STATE_KO_EXCEP_ADDR      : (type = EVENT_TYPE_EXCEPTION              ); break;
+          case CONTEXT_STATE_KO_MISS_BRANCH_AND_LOAD_ADDR: 
           case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break;
           case CONTEXT_STATE_KO_MISS_LOAD_ADDR  : (type = EVENT_TYPE_LOAD_MISS_SPECULATION  ); break;