Changeset 108 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer

Timestamp:

Feb 12, 2009, 12:55:06 PM (15 years ago)

Author:

rosiere

Message:

1) decod_queue : add reg_LAST_SLOT.
2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not)
3) Context State / UPT : Branch miss and Load miss in same cycle.
4) Free List : Bank is on LSB not MSB.
5) Platforms : move data

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer

Files:

• Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp (modified) (4 diffs)
• Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp (modified) (1 diff)
• src/Branch_Target_Buffer_allocation.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp

@@ -28 +28 @@
       {
         log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"  * PREDICT [%d]",i);
+
+        Tcontrol_t val          = PORT_READ(in_PREDICT_VAL          [i]);
+        Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]);
+        Tcontrol_t sort_val     = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL   [i]):true;
+        Tcontrol_t victim_ack   = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true;
+
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * val          : %d",val         );
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * register_ack : %d",register_ack);
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * sort_val     : %d",sort_val    );
+        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * victim_ack   : %d",victim_ack  );
+        
         Tptr_t          index       = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0;
-        Tcontrol_t      hit         = PORT_READ(in_PREDICT_REGISTER_HIT         [i][index]);
+        Tcontrol_t      hit         = // (_param->_have_port_victim)?sort_val:
+                                      PORT_READ(in_PREDICT_REGISTER_HIT [i][index]);
         Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]);
 
@@ -44 +56 @@
         PORT_WRITE(out_PREDICT_IS_ACCURATE  [i],PORT_READ(in_PREDICT_REGISTER_IS_ACCURATE   [i][index]));
 
-        Tcontrol_t val          = PORT_READ(in_PREDICT_VAL          [i]);
-        Tcontrol_t register_ack = PORT_READ(in_PREDICT_REGISTER_ACK [i]);
-        Tcontrol_t sort_val     = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL   [i]):true;
-        Tcontrol_t victim_ack   = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true;
-
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * val          : %d",val         );
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * register_ack : %d",register_ack);
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * sort_val     : %d",sort_val    );
-        log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION,"    * victim_ack   : %d",victim_ack  );
-        
         PORT_WRITE(out_PREDICT_ACK            [i], (
 //                                                  val          and 
                                                     register_ack and
-                                                    sort_val     and
+//                                                  sort_val     and
                                                     victim_ack
                                                     ));
@@ -63 +65 @@
                                                     val          and 
 //                                                  register_ack and
-                                                    sort_val     and
+//                                                  sort_val     and
                                                     victim_ack
                                                     ));
@@ -71 +73 @@
         PORT_WRITE(out_PREDICT_VICTIM_VAL     [i], (
                                                     val          and 
-                                                    register_ack and
-                                                    sort_val     // and
+                                                    register_ack // and
+//                                                  sort_val     and
 //                                                  victim_ack
                                                     ));

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp

@@ -54 +54 @@
             //  * context is the same
             //  * address_src must be higher that the address, because the address lower is previous the current pc.
+            //  * prediction is no accurate is address_dest is not valid.
             PORT_WRITE(out_PREDICT_HIT          [i][j],hit);
             PORT_WRITE(out_PREDICT_ADDRESS_SRC  [i][j],reg_BTB[num_bank][j]._address_src );

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp

@@ -224 +224 @@
                                        dest,"out_PREDICT_"+toString(i)+"_"+toString(j)+"_ADDRESS_SRC");
 
-              // out_OUTPUT_VAL     -> glue
-              // out_OUTPUT_INDEX   -> glue
-              // out_OUTPUT_ADDRESS -> no exist
             }
-        }
+
+          // 1 output
+          // out_OUTPUT_VAL     -> glue
+          // out_OUTPUT_INDEX   -> glue
+          // out_OUTPUT_ADDRESS -> no exist
+        }
 
         //================================================================