- Timestamp:
- Feb 12, 2009, 12:55:06 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine
- Files:
-
- 36 edited
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Commit_unit/SelfTest/config_min.cfg (modified) (1 diff)
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Commit_unit/SelfTest/config_mono_rename_unit.cfg (modified) (1 diff)
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Commit_unit/SelfTest/src/main.cpp (modified) (4 diffs)
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Commit_unit/SelfTest/src/test.cpp (modified) (6 diffs)
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Commit_unit/include/Commit_unit.h (modified) (2 diffs)
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Commit_unit/include/Parameters.h (modified) (1 diff)
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Commit_unit/include/Types.h (modified) (1 diff)
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Commit_unit/src/Commit_unit_allocation.cpp (modified) (2 diffs)
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Commit_unit/src/Commit_unit_deallocation.cpp (modified) (2 diffs)
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Commit_unit/src/Commit_unit_transition.cpp (modified) (12 diffs)
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Commit_unit/src/Parameters.cpp (modified) (2 diffs)
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Issue_queue/src/Parameters_msg_error.cpp (modified) (1 diff)
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Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h (modified) (1 diff)
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Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp (modified) (2 diffs)
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Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp (modified) (2 diffs)
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Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp (modified) (1 diff)
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Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (modified) (11 diffs)
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Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp (modified) (2 diffs)
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Rename_unit/Rename_select/SelfTest/src/test.cpp (modified) (10 diffs)
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Rename_unit/Rename_select/include/Rename_select.h (modified) (3 diffs)
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Rename_unit/Rename_select/src/Rename_select.cpp (modified) (3 diffs)
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Rename_unit/Rename_select/src/Rename_select_allocation.cpp (modified) (3 diffs)
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Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (modified) (4 diffs)
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Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (modified) (1 diff)
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Rename_unit/SelfTest/src/test.cpp (modified) (6 diffs)
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Rename_unit/include/Rename_unit.h (modified) (2 diffs)
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Rename_unit/src/Rename_unit_allocation.cpp (modified) (5 diffs)
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Rename_unit/src/Rename_unit_deallocation.cpp (modified) (2 diffs)
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SelfTest/configuration.cfg (modified) (1 diff)
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SelfTest/src/main.cpp (modified) (4 diffs)
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SelfTest/src/test.cpp (modified) (6 diffs)
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include/OOO_Engine.h (modified) (2 diffs)
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include/Parameters.h (modified) (1 diff)
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src/OOO_Engine_allocation.cpp (modified) (7 diffs)
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src/OOO_Engine_deallocation.cpp (modified) (2 diffs)
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src/Parameters.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg
r88 r108 11 11 1 1 +1 # nb_inst_branch_complete 12 12 0 0 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] 13 1 1 +1 # size_nb_inst_decod 13 14 32 32 +1 # size_general_data 14 15 1 1 +1 # size_store_queue_ptr -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg
r88 r108 11 11 1 1 +1 # nb_inst_branch_complete 12 12 0 0 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] 13 1 1 +1 # size_nb_inst_decod 13 14 32 32 +1 # size_general_data 14 15 1 1 +1 # size_store_queue_ptr -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp
r88 r108 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 1 510 #define NB_PARAMS 16 11 11 12 12 void usage (int argc, char * argv[]) … … 25 25 err (_(" * nb_inst_branch_complete (uint32_t )\n")); 26 26 err (_(" * nb_branch_speculated [nb_front_end][nb_context] (uint32_t )\n")); 27 err (_(" * size_nb_inst_decod (uint32_t )\n")); 27 28 err (_(" * size_general_data (uint32_t )\n")); 28 29 err (_(" * size_store_queue_ptr (uint32_t )\n")); … … 88 89 } 89 90 91 uint32_t _size_nb_inst_decod = fromString<uint32_t >(argv[x++]); 90 92 uint32_t _size_general_data = fromString<uint32_t >(argv[x++]); 91 93 uint32_t _size_store_queue_ptr = fromString<uint32_t >(argv[x++]); … … 112 114 _nb_inst_branch_complete , 113 115 _nb_branch_speculated , 116 _size_nb_inst_decod , 114 117 _size_general_data , 115 118 _size_store_queue_ptr , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r105 r108 68 68 ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 69 69 ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 70 #ifdef DEBUG 71 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 #endif 70 73 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ," in_INSERT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 71 74 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 167 170 ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,"out_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); 168 171 ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,"out_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); 172 ALLOC2_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); 169 173 ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); 170 174 ALLOC2_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); … … 206 210 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 207 211 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 212 #ifdef DEBUG 213 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 214 #endif 208 215 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 209 216 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 317 324 INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 318 325 INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); 326 INSTANCE2_SC_SIGNAL(_Commit_unit, in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 319 327 320 328 if (_param->_have_port_depth) … … 617 625 DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 618 626 DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 627 #ifdef DEBUG 628 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 629 #endif 619 630 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 620 631 DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 714 725 DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 715 726 DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); 727 DELETE2_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 716 728 DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); 717 729 DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r105 r108 83 83 public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] 84 84 public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] 85 #ifdef DEBUG 86 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] 87 #endif 85 88 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS_NEXT ;//[nb_rename_unit][nb_inst_insert] 86 89 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] … … 195 198 public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] 196 199 public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] 200 public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] 197 201 198 202 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h
r88 r108 81 81 uint32_t nb_inst_branch_complete , 82 82 uint32_t ** nb_branch_speculated , 83 uint32_t size_nb_inst_decod , 83 84 uint32_t size_general_data , 84 85 uint32_t size_store_queue_ptr , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r105 r108 90 90 public : Tspecial_data_t flags ; 91 91 public : Tcontrol_t no_sequence ; 92 public : Tcontrol_t speculative ; 92 93 //public : Tgeneral_data_t data_commit ; // branch's destination 94 #ifdef DEBUG 95 public : Taddress_t address ; 96 #endif 93 97 public : Taddress_t address_next ; 94 98 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r105 r108 71 71 _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 #ifdef DEBUG 74 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 #endif 73 76 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 77 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 216 219 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); 217 220 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); 221 _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end, _param->_nb_context[it1]); 218 222 } 219 223 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r105 r108 39 39 DELETE2_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 40 40 DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 41 #ifdef DEBUG 42 DELETE2_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 43 #endif 41 44 DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 42 45 DELETE2_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); … … 143 146 DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); 144 147 DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); 148 DELETE2_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_decod); 145 149 146 150 DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r106 r108 77 77 case EVENT_STATE_WAITEND : 78 78 { 79 if (reg_NB_INST_COMMIT_ALL [i][j] == 0) 79 Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j]; 80 if (nb_inst_all == 0) 80 81 { 81 82 reg_EVENT_STATE [i][j] = EVENT_STATE_END; … … 163 164 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 164 165 entry->no_sequence = type == TYPE_BRANCH; 166 entry->speculative = true; 167 #ifdef DEBUG 168 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 169 #endif 165 170 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); 166 171 … … 173 178 // other -> wait end of instruction 174 179 // * OTHER 175 if (exception == EXCEPTION_NONE) 176 { 177 Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); 178 // no_execute : l.j, l.nop, l.rfe 179 180 log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); 181 182 switch (type) 183 { 184 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} 185 case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} 186 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 187 } 188 } 189 else 190 { 191 // Have an exception : wait head of ROB 192 193 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 194 195 entry->state = ROB_END_EXCEPTION_WAIT_HEAD; 196 } 180 181 // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 182 183 // log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 184 185 // if (flush) 186 // { 187 // entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute 188 // } 189 // else 190 { 191 if (exception == EXCEPTION_NONE) 192 { 193 Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); 194 // no_execute : l.j, l.nop, l.rfe 195 196 log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); 197 198 switch (type) 199 { 200 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} 201 case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} 202 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 203 } 204 } 205 else 206 { 207 // Have an exception : wait head of ROB 208 209 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 210 211 entry->state = ROB_END_EXCEPTION_WAIT_HEAD; 212 } 213 } 197 214 198 215 // Push in rob … … 351 368 Ttype_t type = entry->type ; 352 369 353 if ((state == ROB_END_OK ) or // LOAD_MISS370 if ((state == ROB_END_OK ) or 354 371 // (state == ROB_END_KO ) or 355 (state == ROB_END_BRANCH_MISS) //or356 // (state == ROB_END_LOAD_MISS )or372 (state == ROB_END_BRANCH_MISS) or 373 (state == ROB_END_LOAD_MISS )// or 357 374 // (state == ROB_END_MISS ) or 358 375 // (state == ROB_END_EXCEPTION ) … … 468 485 // =====[ EVENT ]===================================================== 469 486 // =================================================================== 470 { 471 // Not yet implemented 472 } 487 // for (uint32_t i=0; i < _param->_nb_front_end; ++i) 488 // for (uint32_t j=0; j < _param->_nb_context[i]; ++j) 489 // if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) 490 // { 491 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); 492 493 // reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); 494 // reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? 495 // reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); 496 // reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); 497 // // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); 498 // } 473 499 474 500 // =================================================================== … … 505 531 506 532 bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 507 508 Tcontrol_t is_valid = (( (depth == depth_min)or509 depth_full or510 ((depth_min <= depth_max)?511 ((depth >= depth_min) and (depth <=depth_max)):512 ((depth >= depth_min) or (depth <=depth_max))))533 bool speculative = entry->speculative and not (depth == depth_min); 534 Tcontrol_t is_valid = ((not speculative or 535 (speculative and (depth_full or // all is valid 536 ((depth_min <= depth_max)? // test if depth is overflow 537 ((depth >= depth_min) and (depth <=depth_max)): 538 ((depth >= depth_min) or (depth <=depth_max)))))) 513 539 and not flush); 514 540 … … 532 558 case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 533 559 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 560 case ROB_END_BRANCH_MISS : 534 561 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 562 case ROB_END_LOAD_MISS_UPDATE : 563 case ROB_END_LOAD_MISS : 535 564 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 536 565 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 537 566 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 538 567 case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 568 case ROB_END_OK : 539 569 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 570 case ROB_END_KO : 540 571 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 572 case ROB_END_EXCEPTION_UPDATE : 573 case ROB_END_EXCEPTION : 541 574 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 542 575 … … 548 581 // can't have miss speculation 549 582 case ROB_STORE_HEAD_OK : 550 case ROB_END_OK :551 case ROB_END_KO :552 case ROB_END_BRANCH_MISS :553 case ROB_END_LOAD_MISS_UPDATE :554 case ROB_END_LOAD_MISS :555 case ROB_END_EXCEPTION_UPDATE :556 case ROB_END_EXCEPTION :557 583 default : 558 584 { 559 throw ERRORMORPHEO(FUNCTION, _("Miss Speculation : Invalide state.\n"));585 throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); 560 586 break; 561 587 } … … 566 592 // test if instruction is not speculative 567 593 //------------------------------------------------------ 568 if (entry->depth == depth_min) 594 entry->speculative = speculative; 595 // if (entry->depth == depth_min) 596 if (not speculative) 569 597 { 570 598 switch (state) … … 574 602 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 575 603 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} 576 default : {break;} 604 default : {break;} // else, no change 577 605 } 578 606 } … … 587 615 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 588 616 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 589 default : {break;} 617 default : {break;} // else, no change 590 618 } 591 619 } … … 599 627 // =================================================================== 600 628 601 log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); 602 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); 603 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); 604 605 for (uint32_t i=0; i<_param->_nb_front_end; i++) 606 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 629 #ifdef STATISTICS 630 for (uint32_t i=0; i<_param->_nb_bank; i++) 631 if (usage_is_set(_usage,USE_STATISTICS)) 632 *(_stat_bank_nb_inst [i]) += _rob[i].size(); 633 #endif 634 635 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) 636 { 637 log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); 638 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); 639 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); 640 641 for (uint32_t i=0; i<_param->_nb_front_end; i++) 642 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 643 { 644 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d]",i,j); 645 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); 646 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); 647 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); 648 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); 649 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 650 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 651 } 652 653 for (uint32_t i=0; i<_param->_nb_bank; i++) 607 654 { 608 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); 609 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); 610 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); 611 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 612 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 655 uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; 656 657 log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); 658 659 uint32_t x=0; 660 for (std::list<entry_t*>::iterator it=_rob[num_bank].begin(); 661 it!=_rob[num_bank].end(); 662 it++) 663 { 664 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 665 x, 666 (*it)->front_end_id , 667 (*it)->context_id , 668 (*it)->rename_unit_id , 669 (*it)->depth , 670 (*it)->type , 671 (*it)->operation , 672 (*it)->is_delay_slot , 673 (*it)->use_store_queue , 674 (*it)->store_queue_ptr_write , 675 (*it)->use_load_queue , 676 (*it)->load_queue_ptr_write , 677 toString((*it)->state).c_str() , 678 (*it)->ptr ); 679 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 680 (*it)->read_ra , 681 (*it)->num_reg_ra_log , 682 (*it)->num_reg_ra_phy , 683 (*it)->read_rb , 684 (*it)->num_reg_rb_log , 685 (*it)->num_reg_rb_phy , 686 (*it)->read_rc , 687 (*it)->num_reg_rc_log , 688 (*it)->num_reg_rc_phy , 689 (*it)->write_rd , 690 (*it)->num_reg_rd_log , 691 (*it)->num_reg_rd_phy_old , 692 (*it)->num_reg_rd_phy_new , 693 (*it)->write_re , 694 (*it)->num_reg_re_log , 695 (*it)->num_reg_re_phy_old , 696 (*it)->num_reg_re_phy_new ); 697 698 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", 699 (*it)->exception_use , 700 (*it)->exception , 701 (*it)->flags , 702 (*it)->no_sequence , 703 (*it)->speculative , 704 (*it)->address , 705 (*it)->address<<2 , 706 (*it)->address_next , 707 (*it)->address_next<<2 708 ); 709 710 x++; 711 } 613 712 } 614 615 for (uint32_t i=0; i<_param->_nb_bank; i++) 616 { 617 log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); 618 619 #ifdef STATISTICS 620 if (usage_is_set(_usage,USE_STATISTICS)) 621 *(_stat_bank_nb_inst [i]) += _rob[i].size(); 622 #endif 623 624 uint32_t x=0; 625 for (std::list<entry_t*>::iterator it=_rob[i].begin(); 626 it!=_rob[i].end(); 627 it++) 628 { 629 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 630 x, 631 (*it)->front_end_id , 632 (*it)->context_id , 633 (*it)->rename_unit_id , 634 (*it)->depth , 635 (*it)->type , 636 (*it)->operation , 637 // (*it)->address , 638 // (*it)->address << 2 , 639 (*it)->is_delay_slot , 640 (*it)->use_store_queue , 641 (*it)->store_queue_ptr_write , 642 (*it)->use_load_queue , 643 (*it)->load_queue_ptr_write , 644 toString((*it)->state).c_str() , 645 (*it)->ptr ); 646 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 647 (*it)->read_ra , 648 (*it)->num_reg_ra_log , 649 (*it)->num_reg_ra_phy , 650 (*it)->read_rb , 651 (*it)->num_reg_rb_log , 652 (*it)->num_reg_rb_phy , 653 (*it)->read_rc , 654 (*it)->num_reg_rc_log , 655 (*it)->num_reg_rc_phy , 656 (*it)->write_rd , 657 (*it)->num_reg_rd_log , 658 (*it)->num_reg_rd_phy_old , 659 (*it)->num_reg_rd_phy_new , 660 (*it)->write_re , 661 (*it)->num_reg_re_log , 662 (*it)->num_reg_re_phy_old , 663 (*it)->num_reg_re_phy_new ); 664 665 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x (%.8x)", 666 (*it)->exception_use , 667 (*it)->exception , 668 (*it)->flags , 669 (*it)->no_sequence , 670 (*it)->address_next , 671 (*it)->address_next<<2 672 ); 673 674 x++; 675 } 676 } 713 } 714 #endif 715 716 #ifdef DEBUG_TEST 717 { 718 uint32_t x=reg_NUM_BANK_HEAD; 719 if (not _rob[x].empty()) 720 { 721 entry_t * entry = _rob [x].front(); 722 723 if (false 724 // or (entry->state == ROB_EMPTY ) 725 // or (entry->state == ROB_BRANCH_WAIT_END ) 726 // or (entry->state == ROB_BRANCH_COMPLETE ) 727 // or (entry->state == ROB_STORE_WAIT_HEAD_OK ) 728 // //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) 729 // or (entry->state == ROB_STORE_HEAD_OK ) 730 // or (entry->state == ROB_STORE_HEAD_KO ) 731 // or (entry->state == ROB_OTHER_WAIT_END ) 732 // or (entry->state == ROB_MISS_WAIT_END ) 733 // or (entry->state == ROB_END_OK_SPECULATIVE ) 734 or (entry->state == ROB_END_OK ) 735 // or (entry->state == ROB_END_KO_SPECULATIVE ) 736 // or (entry->state == ROB_END_KO ) 737 // or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) 738 or (entry->state == ROB_END_BRANCH_MISS ) 739 // or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) 740 // or (entry->state == ROB_END_LOAD_MISS_UPDATE ) 741 or (entry->state == ROB_END_LOAD_MISS ) 742 // or (entry->state == ROB_END_MISS ) 743 // or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) 744 // or (entry->state == ROB_END_EXCEPTION_UPDATE ) 745 // or (entry->state == ROB_END_EXCEPTION ) 746 ) 747 if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) 748 throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"), 749 entry->address, 750 entry->front_end_id, 751 entry->context_id, 752 reg_PC_CURRENT[entry->front_end_id][entry->context_id])); 753 } 754 } 755 #endif 677 756 678 757 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp
r88 r108 31 31 uint32_t nb_inst_branch_complete , 32 32 uint32_t ** nb_branch_speculated , 33 uint32_t size_nb_inst_decod , 33 34 uint32_t size_general_data , 34 35 uint32_t size_store_queue_ptr , … … 93 94 _size_depth = max<uint32_t>(_array_size_depth,_nb_front_end,_nb_context); 94 95 _size_nb_inst_commit = log2(_size_queue)+1; 96 _size_nb_inst_decod = size_nb_inst_decod; 95 97 96 98 _have_port_front_end_id = _size_front_end_id > 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
r97 r108 27 27 28 28 if (not is_multiple(_size_queue, _nb_bank)) 29 test.error(toString(_("nb_bank must be a multiple of size_queue.\n")));29 test.error(toString(_("nb_bank (%d) must be a multiple of size_queue (%d).\n"),_nb_bank,_size_queue)); 30 30 31 31 if (not is_multiple(_nb_bank, _nb_inst_issue)) 32 test.error(toString(_("nb_inst_issue must be a multiple of nb_bank.\n")));32 test.error(toString(_("nb_inst_issue (%d) must be a multiple of nb_bank (%d) .\n"),_nb_inst_issue,_nb_bank)); 33 33 34 34 if (_nb_rename_unit_select > _nb_rename_unit) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h
r82 r108 89 89 90 90 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 private : uint32_t internal_BANK_PRIORITY;91 private : uint32_t reg_BANK_PRIORITY; 92 92 93 93 private : Tcontrol_t * internal_POP_ACK ; //[nb_pop] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp
r88 r108 28 28 for (uint32_t i=0; i<_param->_nb_pop; i++) 29 29 { 30 uint32_t offset = i*_param->_nb_bank_by_pop; 30 log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 31 32 uint32_t offset = i*_param->_nb_bank_by_pop; 31 33 32 34 // GPR 33 35 bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 34 36 37 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 38 35 39 if (not gpr_ack) 36 40 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 37 41 { 38 uint32_t bank = offset+((j+internal_BANK_PRIORITY)%_param->_nb_bank_by_pop); 42 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop 43 ); 44 45 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 39 46 40 47 if (not _gpr_list[bank].empty()) 41 48 { 42 49 // find 50 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 51 43 52 gpr_ack = true; 44 53 internal_POP_GPR_BANK [i] = bank; 45 54 PORT_WRITE(out_POP_GPR_NUM_REG [i], 46 //(bank << _param->_shift) | 55 //(bank << _param->_shift) | // only in VHDL 47 56 _gpr_list[bank].front()); 48 57 … … 54 63 bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 55 64 65 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 66 56 67 if (not spr_ack) 57 68 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 58 69 { 59 uint32_t bank = offset+((j+internal_BANK_PRIORITY)%_param->_nb_bank_by_pop); 70 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop 71 ); 72 73 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 60 74 61 75 if (not _spr_list[bank].empty()) 62 76 { 63 77 // find 78 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); 79 64 80 spr_ack = true; 65 81 internal_POP_SPR_BANK [i] = bank; 66 82 PORT_WRITE(out_POP_SPR_NUM_REG [i], 67 //(bank << _param->_shift) | 83 //(bank << _param->_shift) | // only in VHDL 68 84 _spr_list[bank].front()); 69 85 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp
r88 r108 26 26 log_function(Free_List_unit,FUNCTION,_name.c_str()); 27 27 28 // bank conflit 28 29 bool bank_use [_param->_nb_bank]; 29 30 for (uint32_t i=0; i<_param->_nb_bank; i++) … … 32 33 for (uint32_t i=0; i<_param->_nb_push; i++) 33 34 { 35 log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH [%d]",i); 36 34 37 bool gpr_ack = not PORT_READ(in_PUSH_GPR_VAL[i]); 38 39 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_PUSH_GPR_VAL[i])); 35 40 36 41 if (not gpr_ack) 37 42 { 38 // num_bank : MSB 39 uint32_t bank = PORT_READ(in_PUSH_GPR_NUM_REG[i]) >> _param->_bank_gpr_size_slot; 43 // // num_bank : MSB 44 // uint32_t bank = PORT_READ(in_PUSH_GPR_NUM_REG[i]) >> _param->_bank_gpr_size_slot; 45 // num_bank : LSB 46 uint32_t bank = PORT_READ(in_PUSH_GPR_NUM_REG[i]) & _param->_mask_gpr; 40 47 41 48 if (not bank_use [bank]) 42 49 { 50 log_printf(TRACE,Free_List_unit,FUNCTION," * find "); 51 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 52 43 53 // find 44 54 gpr_ack = true; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp
r88 r108 36 36 if (not spr_ack) 37 37 { 38 // num_bank : MSB 39 uint32_t bank = PORT_READ(in_PUSH_SPR_NUM_REG[i]) >> _param->_bank_spr_size_slot; 38 // // num_bank : MSB 39 // uint32_t bank = PORT_READ(in_PUSH_SPR_NUM_REG[i]) >> _param->_bank_spr_size_slot; 40 // num_bank : LSB 41 uint32_t bank = PORT_READ(in_PUSH_SPR_NUM_REG[i]) & _param->_mask_spr; 40 42 41 43 if (not bank_use [bank]) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r106 r108 28 28 if (PORT_READ(in_NRESET) == 0) 29 29 { 30 internal_BANK_PRIORITY = 0;30 reg_BANK_PRIORITY = 0; 31 31 for (uint32_t i=0; i<_param->_nb_bank; i++) 32 32 { … … 59 59 { 60 60 log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH_GPR[%d]",i); 61 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",internal_PUSH_GPR_BANK[i]); 62 log_printf(TRACE,Free_List_unit,FUNCTION," * num_reg : %d",PORT_READ(in_PUSH_GPR_NUM_REG [i])); 61 63 62 _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(//_param->_mask_gpr & 63 PORT_READ(in_PUSH_GPR_NUM_REG [i])); 64 _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(PORT_READ(in_PUSH_GPR_NUM_REG [i])); 64 65 } 65 66 // ================================================== … … 70 71 { 71 72 log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH_SPR[%d]",i); 73 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",internal_PUSH_SPR_BANK[i]); 74 log_printf(TRACE,Free_List_unit,FUNCTION," * num_reg : %d",PORT_READ(in_PUSH_SPR_NUM_REG [i])); 72 75 73 _spr_list [internal_PUSH_SPR_BANK[i]].push_back(//_param->_mask_spr & 74 PORT_READ(in_PUSH_SPR_NUM_REG [i])); 76 _spr_list [internal_PUSH_SPR_BANK[i]].push_back(PORT_READ(in_PUSH_SPR_NUM_REG [i])); 75 77 } 76 78 77 if (_param->_priority == PRIORITY_ROUND_ROBIN)78 internal_BANK_PRIORITY = (internal_BANK_PRIORITY+1)%_param->_nb_bank_by_pop;79 if (_param->_priority == PRIORITY_ROUND_ROBIN) 80 reg_BANK_PRIORITY = (reg_BANK_PRIORITY+1)%_param->_nb_bank_by_pop; 79 81 80 82 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) … … 83 85 84 86 log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); 85 86 87 for (uint32_t i=0; i<_param->_nb_bank; ++i) 87 88 { 89 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR [%d] - NB_ELT : %d",i,_gpr_list[i].size()); 90 88 91 uint32_t j=0; 89 for (std::list<Tgeneral_address_t>::iterator it=_gpr_list ->begin();90 it!=_gpr_list ->end();92 for (std::list<Tgeneral_address_t>::iterator it=_gpr_list[i].begin(); 93 it!=_gpr_list[i].end(); 91 94 ) 92 95 { … … 95 98 for (uint32_t x=0; x<limit; x++) 96 99 { 97 if (it==_gpr_list ->end())100 if (it==_gpr_list[i].end()) 98 101 break; 99 102 else … … 108 111 for (uint32_t i=0; i<_param->_nb_bank; ++i) 109 112 { 113 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR [%d] - NB_ELT : %d",i,_spr_list[i].size()); 114 110 115 uint32_t j=0; 111 for (std::list<Tspecial_address_t>::iterator it=_spr_list ->begin();112 it!=_spr_list ->end();116 for (std::list<Tspecial_address_t>::iterator it=_spr_list[i].begin(); 117 it!=_spr_list[i].end(); 113 118 ) 114 119 { … … 117 122 for (uint32_t x=0; x<limit; x++) 118 123 { 119 if (it==_spr_list ->end())124 if (it==_spr_list[i].end()) 120 125 break; 121 126 else … … 132 137 #ifdef DEBUG_TEST 133 138 if (1) 139 for (uint32_t i=0; i<_param->_nb_bank; ++i) 134 140 { 135 for (std::list<Tgeneral_address_t>::iterator it1=_gpr_list ->begin();136 it1!=_gpr_list ->end();141 for (std::list<Tgeneral_address_t>::iterator it1=_gpr_list[i].begin(); 142 it1!=_gpr_list[i].end(); 137 143 ++it1 138 144 ) … … 141 147 142 148 it2 ++; 143 while (it2 != _gpr_list ->end())149 while (it2 != _gpr_list[i].end()) 144 150 { 145 151 if (*it1 == *it2) … … 149 155 } 150 156 151 for (std::list<Tspecial_address_t>::iterator it1=_spr_list ->begin();152 it1!=_spr_list ->end();157 for (std::list<Tspecial_address_t>::iterator it1=_spr_list[i].begin(); 158 it1!=_spr_list[i].end(); 153 159 ++it1 154 160 ) … … 157 163 158 164 it2 ++; 159 while (it2 != _spr_list ->end())165 while (it2 != _spr_list[i].end()) 160 166 { 161 167 if (*it1 == *it2) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp
r88 r108 52 52 _bank_gpr_size_slot = size_general_register-log2(nb_bank); 53 53 54 _mask_gpr = gen_mask<Tgeneral_address_t> ( _bank_gpr_size_slot);54 _mask_gpr = gen_mask<Tgeneral_address_t> (log2(nb_bank)); 55 55 56 56 uint32_t spr_nb_slot = nb_special_register - nb_thread*_nb_special_register_logic; … … 59 59 _bank_spr_size_slot = size_special_register-log2(nb_bank); 60 60 61 _mask_spr = gen_mask<Tspecial_address_t> ( _bank_spr_size_slot);61 _mask_spr = gen_mask<Tspecial_address_t> (log2(nb_bank)); 62 62 63 63 if (is_toplevel) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp
r105 r108 59 59 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 61 #ifdef DEBUG 62 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 63 #endif 61 64 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 62 65 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 84 87 ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); 85 88 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); 89 #ifdef DEBUG 90 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_rename); 91 #endif 86 92 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS_NEXT ,"out_RENAME_OUT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_inst_rename); 87 93 ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); … … 99 105 ALLOC1_SC_SIGNAL(out_RENAME_OUT_EXCEPTION_USE,"out_RENAME_OUT_EXCEPTION_USE",Texception_t ,_param->_nb_inst_rename); 100 106 ALLOC1_SC_SIGNAL(out_RENAME_OUT_EXCEPTION ,"out_RENAME_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_rename); 107 108 ALLOC2_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_front_end,_param->_nb_context[it1]); 101 109 102 110 /******************************************************** … … 121 129 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 122 130 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 131 #ifdef DEBUG 132 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 133 #endif 123 134 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 124 135 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 149 160 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename); 150 161 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IS_DELAY_SLOT,_param->_nb_inst_rename); 162 #ifdef DEBUG 163 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS ,_param->_nb_inst_rename); 164 #endif 151 165 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS_NEXT ,_param->_nb_inst_rename); 152 166 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename); … … 165 179 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_EXCEPTION ,_param->_nb_inst_rename); 166 180 181 INSTANCE2_SC_SIGNAL(_Rename_select, in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); 182 167 183 msg(_("<%s> : Start Simulation ............\n"),name.c_str()); 168 184 … … 194 210 SC_START(5); 195 211 in_NRESET->write(1); 212 213 for (uint32_t i=0; i<_param->_nb_front_end; i++) 214 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 215 in_RETIRE_EVENT_STATE [i][j]->write(EVENT_STATE_NO_EVENT); 196 216 197 217 LABEL("Loop of Test"); … … 329 349 delete [] in_RENAME_IN_NO_EXECUTE ; 330 350 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 351 #ifdef DEBUG 352 delete [] in_RENAME_IN_ADDRESS ; 353 #endif 331 354 delete [] in_RENAME_IN_ADDRESS_NEXT ; 332 355 delete [] in_RENAME_IN_HAS_IMMEDIAT ; … … 354 377 delete [] out_RENAME_OUT_NO_EXECUTE ; 355 378 delete [] out_RENAME_OUT_IS_DELAY_SLOT; 379 #ifdef DEBUG 380 delete [] out_RENAME_OUT_ADDRESS ; 381 #endif 356 382 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 357 383 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; … … 369 395 delete [] out_RENAME_OUT_EXCEPTION_USE; 370 396 delete [] out_RENAME_OUT_EXCEPTION ; 397 398 DELETE2_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1]); 371 399 #endif 372 400 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h
r105 r108 76 76 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 78 #ifdef DEBUG 79 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] 80 #endif 78 81 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 79 82 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 102 105 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] 103 106 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] 107 #ifdef DEBUG 108 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename] 109 #endif 104 110 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS_NEXT ;//[nb_inst_rename] 105 111 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] … … 117 123 public : SC_OUT(Texception_t ) ** out_RENAME_OUT_EXCEPTION_USE;//[nb_inst_rename] 118 124 public : SC_OUT(Texception_t ) ** out_RENAME_OUT_EXCEPTION ;//[nb_inst_rename] 125 126 // ~~~~~[ Interface "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 public : SC_IN (Tevent_state_t ) *** in_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] 119 128 120 129 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp
r105 r108 97 97 << (*(in_RENAME_IN_NO_EXECUTE [i][j])) 98 98 << (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])) 99 #ifdef DEBUG 100 << (*(in_RENAME_IN_ADDRESS [i][j])) 101 #endif 99 102 << (*(in_RENAME_IN_ADDRESS_NEXT [i][j])) 100 103 << (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])) … … 119 122 sensitive << (*(in_RENAME_IN_DEPTH [i][j])); 120 123 } 124 125 // for (uint32_t i=0; i<_param->_nb_front_end; i++) 126 // for (uint32_t j=0; j<_param->_nb_context [i]; j++) 127 // sensitive << (*(in_RETIRE_EVENT_STATE [i][j])); 128 121 129 for (uint32_t i=0; i<_param->_nb_inst_rename; i++) 122 130 sensitive << (*(in_RENAME_OUT_ACK [i])); … … 163 171 (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_VAL [i][j])); 164 172 (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])); 173 #ifdef DEBUG 174 (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_VAL [i][j])); 175 (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_ADDRESS [i][j])); 176 #endif 165 177 (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_VAL [i][j])); 166 178 (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_ADDRESS_NEXT [i][j])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp
r105 r108 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 #ifdef DEBUG 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 #endif 71 74 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 75 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 102 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 103 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 104 #ifdef DEBUG 105 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); 106 #endif 101 107 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 102 108 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); … … 114 120 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); 115 121 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 122 } 123 124 // ~~~~~[ Interface : "retire_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 125 { 126 ALLOC2_INTERFACE("retire_event", IN,NORTH, _("Retire event"), _param->_nb_front_end, _param->_nb_context[it1]); 127 128 _ALLOC2_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state, _param->_nb_front_end, _param->_nb_context[it1]); 116 129 } 117 130 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp
r105 r108 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 40 41 delete [] in_RENAME_IN_NO_EXECUTE ; 41 42 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 43 #ifdef DEBUG 44 delete [] in_RENAME_IN_ADDRESS ; 45 #endif 42 46 delete [] in_RENAME_IN_ADDRESS_NEXT ; 43 47 delete [] in_RENAME_IN_HAS_IMMEDIAT ; … … 66 70 delete [] out_RENAME_OUT_TYPE ; 67 71 delete [] out_RENAME_OUT_OPERATION ; 72 #ifdef DEBUG 73 delete [] out_RENAME_OUT_ADDRESS ; 74 #endif 68 75 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 69 76 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; … … 80 87 delete [] out_RENAME_OUT_NUM_REG_RE ; 81 88 delete [] out_RENAME_OUT_EXCEPTION_USE; 89 90 DELETE2_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_event_state); 82 91 } 83 92 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp
r105 r108 65 65 log_printf(TRACE,Rename_select,FUNCTION," * rename_out_ack : %d",PORT_READ(in_RENAME_OUT_ACK[i])); 66 66 67 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]):0; 68 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_IN_CONTEXT_ID [x][y]):0; 69 70 Tcontrol_t no_execute = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); 71 72 Tcontrol_t read_ra = (PORT_READ(in_RENAME_IN_READ_RA [x][y])); 73 Tcontrol_t read_rb = (PORT_READ(in_RENAME_IN_READ_RB [x][y])); 74 Tcontrol_t read_rc = (PORT_READ(in_RENAME_IN_READ_RC [x][y])); 75 Tcontrol_t write_rd = (PORT_READ(in_RENAME_IN_WRITE_RD [x][y])); 76 Tcontrol_t write_re = (PORT_READ(in_RENAME_IN_WRITE_RE [x][y])); 77 78 // Attention, j'ai enlevé event_state de la liste de sensibilité 79 // Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); 80 81 // Tcontrol_t no_execute = (PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]) or 82 // // ROB Flush 83 // ((event_state == EVENT_STATE_EVENT ) or 84 // (event_state == EVENT_STATE_WAITEND))); 85 86 // Tcontrol_t read_ra = (PORT_READ(in_RENAME_IN_READ_RA [x][y]) and not no_execute); 87 // Tcontrol_t read_rb = (PORT_READ(in_RENAME_IN_READ_RB [x][y]) and not no_execute); 88 // Tcontrol_t read_rc = (PORT_READ(in_RENAME_IN_READ_RC [x][y]) and not no_execute); 89 // Tcontrol_t write_rd = (PORT_READ(in_RENAME_IN_WRITE_RD [x][y]) and not no_execute); 90 // Tcontrol_t write_re = (PORT_READ(in_RENAME_IN_WRITE_RE [x][y]) and not no_execute); 91 67 92 if (_param->_have_port_front_end_id) 68 PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i], PORT_READ(in_RENAME_IN_FRONT_END_ID [x][y]));93 PORT_WRITE(out_RENAME_OUT_FRONT_END_ID [i],front_end_id); 69 94 if (_param->_have_port_context_id) 70 PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i],PORT_READ(in_RENAME_IN_CONTEXT_ID [x][y]));95 PORT_WRITE(out_RENAME_OUT_CONTEXT_ID [i],context_id); 71 96 if (_param->_have_port_depth) 72 97 PORT_WRITE(out_RENAME_OUT_DEPTH [i],PORT_READ(in_RENAME_IN_DEPTH [x][y])); 73 98 PORT_WRITE(out_RENAME_OUT_TYPE [i],PORT_READ(in_RENAME_IN_TYPE [x][y])); 74 99 PORT_WRITE(out_RENAME_OUT_OPERATION [i],PORT_READ(in_RENAME_IN_OPERATION [x][y])); 75 PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i], PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y]));100 PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i],no_execute); 76 101 PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y])); 102 #ifdef DEBUG 103 PORT_WRITE(out_RENAME_OUT_ADDRESS [i],PORT_READ(in_RENAME_IN_ADDRESS [x][y])); 104 #endif 77 105 PORT_WRITE(out_RENAME_OUT_ADDRESS_NEXT [i],PORT_READ(in_RENAME_IN_ADDRESS_NEXT [x][y])); 78 106 PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT [x][y])); 79 107 PORT_WRITE(out_RENAME_OUT_IMMEDIAT [i],PORT_READ(in_RENAME_IN_IMMEDIAT [x][y])); 80 PORT_WRITE(out_RENAME_OUT_READ_RA [i], PORT_READ(in_RENAME_IN_READ_RA [x][y]));108 PORT_WRITE(out_RENAME_OUT_READ_RA [i],read_ra); 81 109 PORT_WRITE(out_RENAME_OUT_NUM_REG_RA [i],PORT_READ(in_RENAME_IN_NUM_REG_RA [x][y])); 82 PORT_WRITE(out_RENAME_OUT_READ_RB [i], PORT_READ(in_RENAME_IN_READ_RB [x][y]));110 PORT_WRITE(out_RENAME_OUT_READ_RB [i],read_rb); 83 111 PORT_WRITE(out_RENAME_OUT_NUM_REG_RB [i],PORT_READ(in_RENAME_IN_NUM_REG_RB [x][y])); 84 PORT_WRITE(out_RENAME_OUT_READ_RC [i], PORT_READ(in_RENAME_IN_READ_RC [x][y]));112 PORT_WRITE(out_RENAME_OUT_READ_RC [i],read_rc); 85 113 PORT_WRITE(out_RENAME_OUT_NUM_REG_RC [i],PORT_READ(in_RENAME_IN_NUM_REG_RC [x][y])); 86 PORT_WRITE(out_RENAME_OUT_WRITE_RD [i], PORT_READ(in_RENAME_IN_WRITE_RD [x][y]));114 PORT_WRITE(out_RENAME_OUT_WRITE_RD [i],write_rd); 87 115 PORT_WRITE(out_RENAME_OUT_NUM_REG_RD [i],PORT_READ(in_RENAME_IN_NUM_REG_RD [x][y])); 88 PORT_WRITE(out_RENAME_OUT_WRITE_RE [i], PORT_READ(in_RENAME_IN_WRITE_RE [x][y]));116 PORT_WRITE(out_RENAME_OUT_WRITE_RE [i],write_re); 89 117 PORT_WRITE(out_RENAME_OUT_NUM_REG_RE [i],PORT_READ(in_RENAME_IN_NUM_REG_RE [x][y])); 90 118 PORT_WRITE(out_RENAME_OUT_EXCEPTION_USE[i],PORT_READ(in_RENAME_IN_EXCEPTION_USE [x][y])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp
r105 r108 57 57 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 #ifdef DEBUG 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 #endif 59 62 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 63 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 81 84 ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,"out_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_insert); 82 85 ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,"out_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_insert); 86 #ifdef DEBUG 87 ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS ,"out_INSERT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_insert); 88 #endif 83 89 ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,"out_INSERT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_insert); 84 90 ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,"out_INSERT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_insert); … … 155 161 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 156 162 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 163 #ifdef DEBUG 164 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 165 #endif 157 166 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 158 167 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 183 192 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); 184 193 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); 194 #ifdef DEBUG 195 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS ,_param->_nb_inst_insert); 196 #endif 185 197 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); 186 198 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); … … 297 309 DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 298 310 DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 311 #ifdef DEBUG 312 DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 313 #endif 299 314 DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 300 315 DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 322 337 DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); 323 338 DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); 339 #ifdef DEBUG 340 DELETE1_SC_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert); 341 #endif 324 342 DELETE1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); 325 343 DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
r105 r108 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 80 #ifdef DEBUG 81 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] 82 #endif 80 83 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 81 84 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 104 107 public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] 105 108 public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] 109 #ifdef DEBUG 110 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] 111 #endif 106 112 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS_NEXT ;//[nb_inst_insert] 107 113 public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r105 r108 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 #ifdef DEBUG 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 #endif 71 74 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 75 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 102 ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 103 ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 104 #ifdef DEBUG 105 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); 106 #endif 101 107 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 102 108 ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); … … 301 307 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT", 302 308 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT"); 309 #ifdef DEBUG 310 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS" , 311 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); 312 #endif 303 313 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" , 304 314 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); … … 349 359 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_DEPTH" , 350 360 dest,"out_INSERT_" +toString(i)+"_DEPTH" ); 361 #ifdef DEBUG 362 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS" , 363 dest,"out_INSERT_" +toString(i)+"_ADDRESS" ); 364 #endif 351 365 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS_NEXT", 352 366 dest,"out_INSERT_" +toString(i)+"_ADDRESS_NEXT"); … … 412 426 dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_EXCEPTION" ); 413 427 } 428 429 for (uint32_t i=0; i<_param->_nb_front_end; i++) 430 for (uint32_t j=0; j<_param->_nb_context[i]; j++) 431 { 432 dest = _name; 433 434 #ifdef POSITION 435 _component->interface_map (src ,"retire_event_"+toString(i)+"_"+toString(j), 436 dest,"retire_event_"+toString(i)+"_"+toString(j)); 437 #endif 438 PORT_MAP(_component,src , "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE", 439 dest, "in_RETIRE_EVENT_"+toString(i)+"_"+toString(j)+"_STATE"); 440 } 414 441 } 415 442 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
r105 r108 37 37 DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 38 38 DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 39 #ifdef DEBUG 40 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); 41 #endif 39 42 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); 40 43 DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); … … 62 65 DELETE1_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert,1 ); 63 66 DELETE1_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); 67 #ifdef DEBUG 68 DELETE1_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_instruction_address ); 69 #endif 64 70 DELETE1_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert,_param->_size_instruction_address ); 65 71 DELETE1_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg
r88 r108 13 13 1 1 +1 # nb_inst_branch_complete 14 14 1 1 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] 15 1 1 +1 # size_nb_inst_decod 15 16 1 1 +1 # nb_rename_unit_select 16 17 1 1 +1 # nb_execute_loop_select -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp
r88 r108 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 2 210 #define NB_PARAMS 23 11 11 12 12 void usage (int argc, char * argv[]) … … 27 27 err (_(" * nb_inst_branch_complete (uint32_t )\n")); 28 28 err (_(" * nb_branch_speculated [nb_front_end][nb_context] (uint32_t )\n")); 29 err (_(" * size_nb_inst_decod (uint32_t )\n")); 29 30 err (_(" * nb_rename_unit_select (uint32_t )\n")); 30 31 err (_(" * nb_execute_loop_select (uint32_t )\n")); … … 130 131 _nb_branch_speculated [i][j] = fromString<uint32_t>(argv[x++]); 131 132 } 133 uint32_t _size_nb_inst_decod = fromString<uint32_t >(argv[x++]); 132 134 uint32_t _nb_rename_unit_select = fromString<uint32_t >(argv[x++]); 133 135 uint32_t _nb_execute_loop_select = fromString<uint32_t >(argv[x++]); … … 275 277 _nb_inst_branch_complete , 276 278 _nb_branch_speculated , 279 _size_nb_inst_decod , 277 280 _nb_rename_unit_select , 278 281 _nb_execute_loop_select , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r105 r108 57 57 ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 #ifdef DEBUG 60 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 #endif 59 62 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ," in_RENAME_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 63 ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 165 168 ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,"out_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); 166 169 ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,"out_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); 170 ALLOC2_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); 167 171 168 172 ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); … … 194 198 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 195 199 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 200 #ifdef DEBUG 201 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 202 #endif 196 203 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 197 204 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 315 322 INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 316 323 INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); 324 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 317 325 318 326 if (_param->_have_port_depth) … … 378 386 DELETE2_SC_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 379 387 DELETE2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 388 #ifdef DEBUG 389 DELETE2_SC_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 390 #endif 380 391 DELETE2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 381 392 DELETE2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 484 495 DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 485 496 DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); 497 DELETE2_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); 486 498 DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); 487 499 DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
r105 r108 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 79 #ifdef DEBUG 80 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod] 81 #endif 79 82 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 80 83 public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 194 197 public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] 195 198 public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] 199 public : SC_IN (Tcounter_t ) *** in_NB_INST_DECOD_ALL ;//[nb_front_end][nb_context] 196 200 197 201 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h
r104 r108 134 134 uint32_t nb_inst_branch_complete , 135 135 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 136 uint32_t size_nb_inst_decod , 136 137 uint32_t nb_rename_unit_select , 137 138 uint32_t nb_execute_loop_select , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r105 r108 66 66 _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 67 67 _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 68 #ifdef DEBUG 69 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 70 #endif 68 71 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 69 72 _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 158 161 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 159 162 { 160 ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_ issue);163 ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_branch_complete); 161 164 162 165 ALLOC1_VALACK_OUT (out_BRANCH_COMPLETE_VAL , VAL); … … 219 222 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); 220 223 _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); 224 _ALLOC2_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"DECOD_ALL" ,Tcounter_t ,_param->_size_nb_inst_decod ,_param->_nb_front_end,_param->_nb_context[it1]); 221 225 } 222 226 … … 413 417 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IS_DELAY_SLOT", 414 418 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT"); 419 #ifdef DEBUG 420 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS" , 421 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS" ); 422 #endif 415 423 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS_NEXT" , 416 424 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" ); … … 477 485 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_IS_DELAY_SLOT" , 478 486 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" ); 487 #ifdef DEBUG 488 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS" , 489 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); 490 #endif 479 491 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS_NEXT" , 480 492 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); … … 755 767 756 768 // in_INSERT_DEPTH - component_rename_unit 769 // in_INSERT_ADDRESS - component_rename_unit 757 770 // in_INSERT_ADDRESS_NEXT - component_rename_unit 758 771 // in_INSERT_EXCEPTION_USE - component_rename_unit … … 991 1004 PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_MEM", 992 1005 dest,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_MEM"); 1006 PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_"+toString(j)+"_DECOD_ALL" , 1007 dest, "in_NB_INST_"+toString(i)+"_"+toString(j)+"_DECOD_ALL" ); 993 1008 } 994 1009 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
r105 r108 36 36 DELETE2_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 37 37 DELETE2_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 38 #ifdef DEBUG 39 DELETE2_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 40 #endif 38 41 DELETE2_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 39 42 DELETE2_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); … … 142 145 DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); 143 146 DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); 147 DELETE2_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_decod ); 144 148 DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); 145 149 DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp
r88 r108 31 31 uint32_t nb_inst_branch_complete , 32 32 uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] 33 uint32_t size_nb_inst_decod , 33 34 uint32_t nb_rename_unit_select , 34 35 uint32_t nb_execute_loop_select , … … 242 243 _nb_inst_branch_complete , 243 244 _nb_branch_speculated , 245 size_nb_inst_decod , 244 246 size_general_data , 245 247 size_store_queue_ptr , … … 336 338 _size_rob_ptr = size_packet_id; 337 339 _size_nb_inst_commit = log2(size_re_order_buffer)+1; 340 _size_nb_inst_decod = size_nb_inst_decod; 338 341 339 342 _have_port_front_end_id = _size_front_end_id > 0;
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