Ignore:
Timestamp:
Mar 18, 2009, 11:36:26 PM (15 years ago)
Author:
rosiere
Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp

    r88 r112  
    4848                                                         ,IN
    4949                                                         ,SOUTH,
    50                                                          "Generalist interface"
     50                                                         _("Generalist interface")
    5151#endif
    5252                                                         );
    … …  
    5858    // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    5959    {
    60       ALLOC_INTERFACE("address", IN, NORTH, "Transaction with PC management.");
     60      ALLOC0_INTERFACE_BEGIN("address", IN, NORTH, "Transaction with PC management.");
    6161
    62       ALLOC_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
    63       ALLOC_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
    64       ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
    65       ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
    66       ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
    67       ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
    68       ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
     62      ALLOC0_VALACK_IN ( in_ADDRESS_VAL                        ,VAL);
     63      ALLOC0_VALACK_OUT(out_ADDRESS_ACK                        ,ACK);
     64      ALLOC0_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t ,_param->_size_instruction_address        );
     65      ALLOC0_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr);
     66      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state   );
     67      ALLOC0_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth          );
     68      ALLOC0_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID            ,"ifetch_queue_id"            ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr);
    6969
     70      ALLOC0_INTERFACE_END();
    7071    }
    7172    {
    72       ALLOC1_INTERFACE("address", IN, NORTH, "Transaction with PC management.",_param->_nb_instruction);
     73      ALLOC1_INTERFACE_BEGIN("address", IN, NORTH, _("Transaction with PC management."),_param->_nb_instruction);
    7374
    7475      ALLOC1_SIGNAL_IN( in_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t         ,1);
     76
     77      ALLOC1_INTERFACE_END(_param->_nb_instruction);
    7578    }
    7679
    7780    // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    7881    {
    79       ALLOC1_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.",_param->_nb_instruction);
     82      ALLOC1_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."),_param->_nb_instruction);
    8083     
    8184      ALLOC1_VALACK_OUT(out_DECOD_VAL        ,VAL);
    8285      ALLOC1_VALACK_IN ( in_DECOD_ACK        ,ACK);
    8386      ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION,"instruction",Tinstruction_t,_param->_size_instruction);
     87
     88      ALLOC1_INTERFACE_END(_param->_nb_instruction);
    8489    }
    8590    {
    86       ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage.");
     91      ALLOC0_INTERFACE_BEGIN("decod",OUT, EAST, _("Send instruction bundle to the decod's stage."));
    8792     
    88       ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
    89       ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
    90       ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
    91       ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
    92       ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
     93      ALLOC0_SIGNAL_OUT(out_DECOD_ADDRESS                    ,"address"                    ,Tgeneral_address_t,_param->_size_instruction_address         );
     94      ALLOC0_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr );
     95      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state    );
     96      ALLOC0_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth           );
     97      ALLOC0_SIGNAL_OUT(out_DECOD_EXCEPTION                  ,"exception"                  ,Texception_t      ,_param->_size_exception_ifetch);
     98
     99      ALLOC0_INTERFACE_END();
    93100    }
    94101
    95102    // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    96103    {
    97       ALLOC_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.");
     104      ALLOC0_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."));
    98105     
    99       ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
    100       ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
    101       ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
    102       ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
     106      ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL      ,VAL);
     107      ALLOC0_VALACK_OUT(out_ICACHE_RSP_ACK      ,ACK);
     108      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t      ,_param->_size_ifetch_queue_ptr);
     109      ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR    ,"error"    ,Ticache_error_t,_param->_size_icache_error);
     110
     111      ALLOC0_INTERFACE_END();
    103112    }
    104113    {
    105       ALLOC1_INTERFACE("icache_rsp", IN, WEST, "Respons from Instruction Cache.",_param->_nb_instruction);
     114      ALLOC1_INTERFACE_BEGIN("icache_rsp", IN, WEST, _("Respons from Instruction Cache."),_param->_nb_instruction);
    106115     
    107116      ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction);
     117
     118      ALLOC1_INTERFACE_END(_param->_nb_instruction);
    108119    }
    109120
    110121    // ~~~~~[ Interface "event_reset" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    111122    {
    112       ALLOC_INTERFACE("event_reset", IN, NORTH, "An event occure and reset queue.");
     123      ALLOC0_INTERFACE_BEGIN("event_reset", IN, NORTH, _("An event occure and reset queue."));
    113124
    114       ALLOC_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
    115       ALLOC_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
     125      ALLOC0_VALACK_IN ( in_EVENT_RESET_VAL,VAL);
     126      ALLOC0_VALACK_OUT(out_EVENT_RESET_ACK,ACK);
     127
     128      ALLOC0_INTERFACE_END();
    116129    }
    117130
    … …  
    119132    if (usage_is_set(_usage,USE_SYSTEMC))
    120133      {
    121         internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction];
     134        ALLOC1(internal_DECOD_VAL,Tcontrol_t,_param->_nb_instruction);
    122135       
    123136        _queue = new ifetch_queue_entry_t * [_param->_size_queue];

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp

    r88 r112  
    77
    88#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h"
     9#include "Behavioural/include/Allocation.h"
    910
    1011namespace morpheo                    {
    … …  
    2829        delete    in_NRESET;
    2930
    30         delete     in_ADDRESS_VAL                        ;
    31         delete    out_ADDRESS_ACK                        ;
    32         if (_param->_have_port_ifetch_queue_ptr)
    33         delete    out_ADDRESS_IFETCH_QUEUE_ID            ;
    34         delete []  in_ADDRESS_INSTRUCTION_ENABLE         ;
    35         delete     in_ADDRESS_INSTRUCTION_ADDRESS        ;
    36         if (_param->_have_port_inst_ifetch_ptr)
    37         delete     in_ADDRESS_INST_IFETCH_PTR            ;
    38         delete     in_ADDRESS_BRANCH_STATE               ;
    39         if (_param->_have_port_depth)
    40         delete     in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
    41         delete [] out_DECOD_VAL                          ;
    42         delete []  in_DECOD_ACK                          ;
    43         delete [] out_DECOD_INSTRUCTION                  ;
    44         delete    out_DECOD_ADDRESS                      ;
    45         if (_param->_have_port_inst_ifetch_ptr)
    46         delete    out_DECOD_INST_IFETCH_PTR              ;
    47         delete    out_DECOD_BRANCH_STATE                 ;
    48         if (_param->_have_port_depth)
    49         delete    out_DECOD_BRANCH_UPDATE_PREDICTION_ID  ;
    50         delete    out_DECOD_EXCEPTION                    ;
    51         delete     in_ICACHE_RSP_VAL                     ;
    52         delete    out_ICACHE_RSP_ACK                     ;
    53         if (_param->_have_port_ifetch_queue_ptr)
    54         delete     in_ICACHE_RSP_PACKET_ID               ;
    55         delete []  in_ICACHE_RSP_INSTRUCTION             ;
    56         delete     in_ICACHE_RSP_ERROR                   ;
    57         delete     in_EVENT_RESET_VAL                    ;
    58         delete    out_EVENT_RESET_ACK                    ;
     31        DELETE0_SIGNAL( in_ADDRESS_VAL                        ,1);
     32        DELETE0_SIGNAL(out_ADDRESS_ACK                        ,1);
     33        DELETE0_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS        ,_param->_size_instruction_address);
     34        DELETE0_SIGNAL( in_ADDRESS_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr);
     35        DELETE0_SIGNAL( in_ADDRESS_BRANCH_STATE               ,_param->_size_branch_state   );
     36        DELETE0_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth          );
     37        DELETE0_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID            ,_param->_size_ifetch_queue_ptr);
     38        DELETE1_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE         ,1,_param->_nb_instruction);
     39     
     40        DELETE1_SIGNAL(out_DECOD_VAL                        ,1,_param->_nb_instruction);
     41        DELETE1_SIGNAL( in_DECOD_ACK                        ,1,_param->_nb_instruction);
     42        DELETE1_SIGNAL(out_DECOD_INSTRUCTION                ,_param->_size_instruction,_param->_nb_instruction);
     43        DELETE0_SIGNAL(out_DECOD_ADDRESS                    ,_param->_size_instruction_address);
     44        DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR            ,_param->_size_inst_ifetch_ptr );
     45        DELETE0_SIGNAL(out_DECOD_BRANCH_STATE               ,_param->_size_branch_state    );
     46        DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth           );
     47        DELETE0_SIGNAL(out_DECOD_EXCEPTION                  ,_param->_size_exception_ifetch);
     48
     49        DELETE0_SIGNAL( in_ICACHE_RSP_VAL        ,1);
     50        DELETE0_SIGNAL(out_ICACHE_RSP_ACK        ,1);
     51        DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID  ,_param->_size_ifetch_queue_ptr);
     52        DELETE0_SIGNAL( in_ICACHE_RSP_ERROR      ,_param->_size_icache_error);
     53        DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction);
     54
     55        DELETE0_SIGNAL( in_EVENT_RESET_VAL,1);
     56        DELETE0_SIGNAL(out_EVENT_RESET_ACK,1);
    5957      }
    6058
    … …  
    6260    if (usage_is_set(_usage,USE_SYSTEMC))
    6361      {
    64         delete    internal_DECOD_VAL;
     62        DELETE1(internal_DECOD_VAL,_param->_nb_instruction);
     63       
     64        for (uint32_t i=0;i<_param->_size_queue; i++)
     65          delete _queue[i];
    6566        delete [] _queue;
    6667      }
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