Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit
- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit
- Files:
-
- 1 deleted
- 45 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp
r88 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 60 60 { 61 61 { 62 ALLOC1_INTERFACE ("predict", IN, WEST, "predict",_param->_nb_inst_predict);62 ALLOC1_INTERFACE_BEGIN("predict", IN, WEST, _("predict"),_param->_nb_inst_predict); 63 63 64 64 ALLOC1_SIGNAL_IN ( in_PREDICT_VAL , "val" ,Tcontrol_t , 1); … … 84 84 ALLOC1_SIGNAL_IN ( in_PREDICT_VICTIM_VICTIM , "victim_victim" ,Tptr_t , _param->_size_victim); 85 85 } 86 87 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 86 88 } 87 89 { 88 ALLOC2_INTERFACE ("predict", IN, WEST, "predict",_param->_nb_inst_predict, _param->_associativity);90 ALLOC2_INTERFACE_BEGIN("predict", IN, WEST, _("predict"),_param->_nb_inst_predict, _param->_associativity); 89 91 90 92 ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_HIT ,"register_hit" ,Tcontrol_t ,1); … … 94 96 ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_LAST_TAKE ,"register_last_take" ,Tcontrol_t ,1); 95 97 ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_IS_ACCURATE ,"register_is_accurate" ,Tcontrol_t ,1); 98 99 ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity); 96 100 } 97 101 } … … 99 103 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 100 104 { 101 ALLOC1_INTERFACE ("decod", IN, WEST, "decod",_param->_nb_inst_decod);105 ALLOC1_INTERFACE_BEGIN("decod", IN, WEST, _("decod"),_param->_nb_inst_decod); 102 106 103 107 ALLOC1_SIGNAL_IN ( in_DECOD_VAL ,"val" ,Tcontrol_t ,1); … … 115 119 ALLOC1_SIGNAL_OUT(out_DECOD_VICTIM_ADDRESS,"victim_address",Tgeneral_data_t,_param->_size_victim_address); 116 120 } 121 122 ALLOC1_INTERFACE_END(_param->_nb_inst_decod); 117 123 } 118 124 119 125 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 120 126 { 121 ALLOC1_INTERFACE ("update", IN, WEST, "update",_param->_nb_inst_update);127 ALLOC1_INTERFACE_BEGIN("update", IN, WEST, _("update"),_param->_nb_inst_update); 122 128 123 129 ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t ,1); … … 135 141 ALLOC1_SIGNAL_OUT(out_UPDATE_VICTIM_ADDRESS,"victim_address",Tgeneral_data_t,_param->_size_victim_address); 136 142 } 143 144 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 137 145 } 138 146 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 delete [] in_PREDICT_VAL ; 32 delete [] out_PREDICT_ACK ; 33 delete [] out_PREDICT_HIT ; 34 delete [] out_PREDICT_ADDRESS_SRC ; 35 delete [] out_PREDICT_ADDRESS_DEST ; 36 delete [] out_PREDICT_CONDITION ; 37 delete [] out_PREDICT_LAST_TAKE ; 38 delete [] out_PREDICT_IS_ACCURATE ; 39 delete [] out_PREDICT_REGISTER_VAL ; 40 delete [] in_PREDICT_REGISTER_ACK ; 41 delete [] in_PREDICT_REGISTER_HIT ; 42 delete [] in_PREDICT_REGISTER_ADDRESS_SRC ; 43 delete [] in_PREDICT_REGISTER_ADDRESS_DEST ; 44 delete [] in_PREDICT_REGISTER_CONDITION ; 45 delete [] in_PREDICT_REGISTER_LAST_TAKE ; 46 delete [] in_PREDICT_REGISTER_IS_ACCURATE ; 32 DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict, 1); 33 DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict, 1); 34 DELETE1_SIGNAL(out_PREDICT_HIT ,_param->_nb_inst_predict, 1); 35 DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict, _param->_size_instruction_address); 36 DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_predict, _param->_size_instruction_address); 37 DELETE1_SIGNAL(out_PREDICT_CONDITION ,_param->_nb_inst_predict, _param->_size_branch_condition); 38 DELETE1_SIGNAL(out_PREDICT_LAST_TAKE ,_param->_nb_inst_predict, 1); 39 DELETE1_SIGNAL(out_PREDICT_IS_ACCURATE ,_param->_nb_inst_predict, 1); 40 DELETE1_SIGNAL(out_PREDICT_REGISTER_VAL ,_param->_nb_inst_predict, 1); 41 DELETE1_SIGNAL( in_PREDICT_REGISTER_ACK ,_param->_nb_inst_predict, 1); 47 42 if (_param->_have_port_victim) 48 43 { 49 delete [] in_PREDICT_SORT_VAL;50 delete [] in_PREDICT_SORT_INDEX;51 delete [] out_PREDICT_VICTIM_VAL ; 52 delete [] in_PREDICT_VICTIM_ACK;53 delete [] out_PREDICT_VICTIM_HIT;54 if (not _param->_is_full_associative)55 delete [] out_PREDICT_VICTIM_ADDRESS;56 delete [] out_PREDICT_VICTIM_INDEX;57 delete [] in_PREDICT_VICTIM_VICTIM;44 DELETE1_SIGNAL( in_PREDICT_SORT_VAL ,_param->_nb_inst_predict,1); 45 DELETE1_SIGNAL( in_PREDICT_SORT_INDEX ,_param->_nb_inst_predict,_param->_size_victim); 46 47 DELETE1_SIGNAL(out_PREDICT_VICTIM_VAL ,_param->_nb_inst_predict, 1); 48 DELETE1_SIGNAL( in_PREDICT_VICTIM_ACK ,_param->_nb_inst_predict, 1); 49 DELETE1_SIGNAL(out_PREDICT_VICTIM_HIT ,_param->_nb_inst_predict, 1); 50 DELETE1_SIGNAL(out_PREDICT_VICTIM_ADDRESS,_param->_nb_inst_predict, _param->_size_victim_address); 51 DELETE1_SIGNAL(out_PREDICT_VICTIM_INDEX ,_param->_nb_inst_predict, _param->_size_victim); 52 DELETE1_SIGNAL( in_PREDICT_VICTIM_VICTIM ,_param->_nb_inst_predict, _param->_size_victim); 58 53 } 59 delete [] in_DECOD_VAL ; 60 delete [] out_DECOD_ACK ; 61 if (not _param->_is_full_associative) 62 delete [] in_DECOD_ADDRESS_SRC ; 63 delete [] out_DECOD_REGISTER_VAL ; 64 delete [] in_DECOD_REGISTER_ACK ; 65 if (_param->_have_port_victim) 66 { 67 delete [] out_DECOD_VICTIM_VAL ; 68 delete [] in_DECOD_VICTIM_ACK ; 69 if (not _param->_is_full_associative) 70 delete [] out_DECOD_VICTIM_ADDRESS ; 71 } 72 delete [] in_UPDATE_VAL ; 73 delete [] out_UPDATE_ACK ; 74 if (not _param->_is_full_associative) 75 delete [] in_UPDATE_ADDRESS_SRC ; 76 delete [] out_UPDATE_REGISTER_VAL ; 77 delete [] in_UPDATE_REGISTER_ACK ; 78 if (_param->_have_port_victim) 79 { 80 delete [] out_UPDATE_VICTIM_VAL ; 81 delete [] in_UPDATE_VICTIM_ACK ; 82 if (not _param->_is_full_associative) 83 delete [] out_UPDATE_VICTIM_ADDRESS ; 84 } 54 55 DELETE2_SIGNAL( in_PREDICT_REGISTER_HIT ,_param->_nb_inst_predict, _param->_associativity,1); 56 DELETE2_SIGNAL( in_PREDICT_REGISTER_ADDRESS_SRC ,_param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); 57 DELETE2_SIGNAL( in_PREDICT_REGISTER_ADDRESS_DEST,_param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); 58 DELETE2_SIGNAL( in_PREDICT_REGISTER_CONDITION ,_param->_nb_inst_predict, _param->_associativity,_param->_size_branch_condition); 59 DELETE2_SIGNAL( in_PREDICT_REGISTER_LAST_TAKE ,_param->_nb_inst_predict, _param->_associativity,1); 60 DELETE2_SIGNAL( in_PREDICT_REGISTER_IS_ACCURATE ,_param->_nb_inst_predict, _param->_associativity,1); 61 62 DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); 63 DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); 64 if (not _param->_is_full_associative) 65 DELETE1_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); 66 67 DELETE1_SIGNAL(out_DECOD_REGISTER_VAL ,_param->_nb_inst_decod,1); 68 DELETE1_SIGNAL( in_DECOD_REGISTER_ACK ,_param->_nb_inst_decod,1); 69 if (_param->_have_port_victim) 70 { 71 DELETE1_SIGNAL(out_DECOD_VICTIM_VAL ,_param->_nb_inst_decod,1); 72 DELETE1_SIGNAL( in_DECOD_VICTIM_ACK ,_param->_nb_inst_decod,1); 73 DELETE1_SIGNAL(out_DECOD_VICTIM_ADDRESS,_param->_nb_inst_decod,_param->_size_victim_address); 74 } 75 76 DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); 77 DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); 78 if (not _param->_is_full_associative) 79 DELETE1_SIGNAL( in_UPDATE_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); 80 DELETE1_SIGNAL(out_UPDATE_REGISTER_VAL ,_param->_nb_inst_update,1); 81 DELETE1_SIGNAL( in_UPDATE_REGISTER_ACK ,_param->_nb_inst_update,1); 82 if (_param->_have_port_victim) 83 { 84 DELETE1_SIGNAL(out_UPDATE_VICTIM_VAL ,_param->_nb_inst_update,1); 85 DELETE1_SIGNAL( in_UPDATE_VICTIM_ACK ,_param->_nb_inst_update,1); 86 DELETE1_SIGNAL(out_UPDATE_VICTIM_ADDRESS,_param->_nb_inst_update,_param->_size_victim_address); 87 } 88 85 89 } 86 90 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp
r88 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 59 59 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("predict", IN, SOUTH, "Compute next pc.", _param->_nb_inst_predict);61 ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Compute next pc."), _param->_nb_inst_predict); 62 62 63 63 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 66 66 ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); 67 67 68 { 69 ALLOC2_INTERFACE("predict", OUT, SOUTH, "Compute next pc.", _param->_nb_inst_predict, _param->_associativity); 70 71 ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); 72 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); 73 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); 74 ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); 75 ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 76 ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 77 } 68 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 69 } 70 { 71 ALLOC2_INTERFACE_BEGIN("predict", OUT, SOUTH, _("Compute next pc."), _param->_nb_inst_predict, _param->_associativity); 72 73 ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); 74 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); 75 ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); 76 ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); 77 ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 78 ALLOC2_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 79 80 ALLOC2_INTERFACE_END(_param->_nb_inst_predict, _param->_associativity); 78 81 } 79 82 80 83 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 81 84 { 82 ALLOC1_INTERFACE ("decod", IN, SOUTH, "decod instruction", _param->_nb_inst_decod);85 ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod instruction"), _param->_nb_inst_decod); 83 86 84 87 ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); … … 97 100 ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 98 101 ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 102 103 ALLOC1_INTERFACE_END(_param->_nb_inst_decod); 99 104 } 100 105 101 106 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 102 107 { 103 ALLOC1_INTERFACE ("update", IN, SOUTH, "update instruction", _param->_nb_inst_update);108 ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update instruction"), _param->_nb_inst_update); 104 109 105 110 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); … … 117 122 ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 118 123 ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 124 125 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 119 126 } 120 127 … … 122 129 { 123 130 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 124 reg_BTB = new btb_entry_t * [_param->_size_bank]; 125 for (uint32_t i=0; i<_param->_size_bank; i++) 126 reg_BTB [i] = new btb_entry_t [_param->_associativity]; 131 ALLOC2(reg_BTB,btb_entry_t,_param->_size_bank,_param->_associativity); 127 132 128 internal_DECOD_ACK = new Tcontrol_t [_param->_nb_inst_decod];129 internal_DECOD_HIT = new Tcontrol_t [_param->_nb_inst_decod];130 internal_DECOD_NUM_BANK = new uint32_t [_param->_nb_inst_decod];131 internal_DECOD_NUM_ENTRY = new uint32_t [_param->_nb_inst_decod];133 ALLOC1(internal_DECOD_ACK ,Tcontrol_t,_param->_nb_inst_decod ); 134 ALLOC1(internal_DECOD_HIT ,Tcontrol_t,_param->_nb_inst_decod ); 135 ALLOC1(internal_DECOD_NUM_BANK ,uint32_t ,_param->_nb_inst_decod ); 136 ALLOC1(internal_DECOD_NUM_ENTRY ,uint32_t ,_param->_nb_inst_decod ); 132 137 133 internal_UPDATE_ACK = new Tcontrol_t [_param->_nb_inst_update];134 internal_UPDATE_HIT = new Tcontrol_t [_param->_nb_inst_update];135 internal_UPDATE_NUM_BANK = new uint32_t [_param->_nb_inst_update];136 internal_UPDATE_NUM_ENTRY = new uint32_t [_param->_nb_inst_update];138 ALLOC1(internal_UPDATE_ACK ,Tcontrol_t,_param->_nb_inst_update); 139 ALLOC1(internal_UPDATE_HIT ,Tcontrol_t,_param->_nb_inst_update); 140 ALLOC1(internal_UPDATE_NUM_BANK ,uint32_t ,_param->_nb_inst_update); 141 ALLOC1(internal_UPDATE_NUM_ENTRY,uint32_t ,_param->_nb_inst_update); 137 142 } 138 143 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 delete [] in_PREDICT_VAL ; 32 delete [] out_PREDICT_ACK ; 33 if (_param->_have_port_context_id) 34 delete [] in_PREDICT_CONTEXT_ID ; 35 delete [] in_PREDICT_ADDRESS ; 36 delete [] out_PREDICT_HIT ; 37 delete [] out_PREDICT_ADDRESS_SRC ; 38 delete [] out_PREDICT_ADDRESS_DEST ; 39 delete [] out_PREDICT_CONDITION ; 40 delete [] out_PREDICT_LAST_TAKE ; 41 delete [] out_PREDICT_IS_ACCURATE ; 42 delete [] in_DECOD_VAL ; 43 delete [] out_DECOD_ACK ; 44 if (_param->_have_port_victim) 45 { 46 delete [] out_DECOD_HIT ; 47 delete [] out_DECOD_HIT_INDEX ; 48 delete [] in_DECOD_VICTIM ; 49 } 50 if (_param->_have_port_context_id) 51 delete [] in_DECOD_CONTEXT_ID ; 52 delete [] in_DECOD_ADDRESS_SRC ; 53 delete [] in_DECOD_ADDRESS_DEST ; 54 delete [] in_DECOD_CONDITION ; 55 delete [] in_DECOD_LAST_TAKE ; 56 delete [] in_DECOD_MISS_PREDICTION ; 57 delete [] in_DECOD_IS_ACCURATE ; 58 delete [] in_UPDATE_VAL ; 59 delete [] out_UPDATE_ACK ; 60 if (_param->_have_port_victim) 61 { 62 delete [] out_UPDATE_HIT ; 63 delete [] out_UPDATE_HIT_INDEX ; 64 delete [] in_UPDATE_VICTIM ; 65 } 66 if (_param->_have_port_context_id) 67 delete [] in_UPDATE_CONTEXT_ID ; 68 delete [] in_UPDATE_ADDRESS_SRC ; 69 delete [] in_UPDATE_ADDRESS_DEST ; 70 delete [] in_UPDATE_CONDITION ; 71 delete [] in_UPDATE_LAST_TAKE ; 72 delete [] in_UPDATE_MISS_PREDICTION; 32 DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); 33 DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); 34 DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); 35 DELETE1_SIGNAL( in_PREDICT_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); 36 DELETE2_SIGNAL(out_PREDICT_HIT , _param->_nb_inst_predict, _param->_associativity,1); 37 DELETE2_SIGNAL(out_PREDICT_ADDRESS_SRC , _param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); 38 DELETE2_SIGNAL(out_PREDICT_ADDRESS_DEST, _param->_nb_inst_predict, _param->_associativity,_param->_size_instruction_address); 39 DELETE2_SIGNAL(out_PREDICT_CONDITION , _param->_nb_inst_predict, _param->_associativity,_param->_size_branch_state); 40 DELETE2_SIGNAL(out_PREDICT_LAST_TAKE , _param->_nb_inst_predict, _param->_associativity,1); 41 DELETE2_SIGNAL(out_PREDICT_IS_ACCURATE , _param->_nb_inst_predict, _param->_associativity,1); 42 43 DELETE1_SIGNAL( in_DECOD_VAL , _param->_nb_inst_decod,1); 44 DELETE1_SIGNAL(out_DECOD_ACK , _param->_nb_inst_decod,1); 45 if (_param->_have_port_victim) 46 { 47 DELETE1_SIGNAL(out_DECOD_HIT , _param->_nb_inst_decod,1); 48 DELETE1_SIGNAL(out_DECOD_HIT_INDEX , _param->_nb_inst_decod,_param->_size_victim); 49 DELETE1_SIGNAL( in_DECOD_VICTIM , _param->_nb_inst_decod,_param->_size_victim); 50 } 51 DELETE1_SIGNAL( in_DECOD_CONTEXT_ID , _param->_nb_inst_decod,_param->_size_context_id); 52 DELETE1_SIGNAL( in_DECOD_ADDRESS_SRC , _param->_nb_inst_decod,_param->_size_instruction_address); 53 DELETE1_SIGNAL( in_DECOD_ADDRESS_DEST , _param->_nb_inst_decod,_param->_size_instruction_address); 54 DELETE1_SIGNAL( in_DECOD_CONDITION , _param->_nb_inst_decod,_param->_size_branch_state); 55 DELETE1_SIGNAL( in_DECOD_LAST_TAKE , _param->_nb_inst_decod,1); 56 DELETE1_SIGNAL( in_DECOD_MISS_PREDICTION, _param->_nb_inst_decod,1); 57 DELETE1_SIGNAL( in_DECOD_IS_ACCURATE , _param->_nb_inst_decod,1); 58 59 DELETE1_SIGNAL( in_UPDATE_VAL , _param->_nb_inst_update,1); 60 DELETE1_SIGNAL(out_UPDATE_ACK , _param->_nb_inst_update,1); 61 if (_param->_have_port_victim) 62 { 63 DELETE1_SIGNAL(out_UPDATE_HIT , _param->_nb_inst_update,1); 64 DELETE1_SIGNAL(out_UPDATE_HIT_INDEX , _param->_nb_inst_update,_param->_size_victim); 65 DELETE1_SIGNAL( in_UPDATE_VICTIM , _param->_nb_inst_update,_param->_size_victim); 66 } 67 DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID , _param->_nb_inst_update,_param->_size_context_id); 68 DELETE1_SIGNAL( in_UPDATE_ADDRESS_SRC , _param->_nb_inst_update,_param->_size_instruction_address); 69 DELETE1_SIGNAL( in_UPDATE_ADDRESS_DEST , _param->_nb_inst_update,_param->_size_instruction_address); 70 DELETE1_SIGNAL( in_UPDATE_CONDITION , _param->_nb_inst_update,_param->_size_branch_state); 71 DELETE1_SIGNAL( in_UPDATE_LAST_TAKE , _param->_nb_inst_update,1); 72 DELETE1_SIGNAL( in_UPDATE_MISS_PREDICTION, _param->_nb_inst_update,1); 73 74 DELETE2(reg_BTB ,_param->_size_bank,_param->_associativity); 73 75 74 delete [] reg_BTB; 75 76 delete [] internal_DECOD_ACK ; 77 delete [] internal_DECOD_HIT ; 78 delete [] internal_DECOD_NUM_BANK ; 79 delete [] internal_DECOD_NUM_ENTRY ; 80 81 delete [] internal_UPDATE_ACK ; 82 delete [] internal_UPDATE_HIT ; 83 delete [] internal_UPDATE_NUM_BANK ; 84 delete [] internal_UPDATE_NUM_ENTRY; 76 DELETE1(internal_DECOD_ACK ,_param->_nb_inst_decod ); 77 DELETE1(internal_DECOD_HIT ,_param->_nb_inst_decod ); 78 DELETE1(internal_DECOD_NUM_BANK ,_param->_nb_inst_decod ); 79 DELETE1(internal_DECOD_NUM_ENTRY ,_param->_nb_inst_decod ); 80 DELETE1(internal_UPDATE_ACK ,_param->_nb_inst_update); 81 DELETE1(internal_UPDATE_HIT ,_param->_nb_inst_update); 82 DELETE1(internal_UPDATE_NUM_BANK ,_param->_nb_inst_update); 83 DELETE1(internal_UPDATE_NUM_ENTRY,_param->_nb_inst_update); 85 84 } 86 85 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp
r108 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 59 59 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("predict", IN, SOUTH, "Predict (next pc) interface", _param->_nb_inst_predict);61 ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Predict (next pc) interface"), _param->_nb_inst_predict); 62 62 63 63 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 71 71 ALLOC1_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 72 72 ALLOC1_SIGNAL_OUT(out_PREDICT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 73 74 ALLOC1_INTERFACE_END(param->_nb_inst_predict); 73 75 } 74 76 75 77 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 76 78 { 77 ALLOC1_INTERFACE ("decod", IN, SOUTH, "Decod Interface", _param->_nb_inst_decod);79 ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("Decod Interface"), _param->_nb_inst_decod); 78 80 79 81 ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); … … 86 88 ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 87 89 ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 90 91 ALLOC1_INTERFACE_END(_param->_nb_inst_decod); 88 92 } 89 93 90 94 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 95 { 92 ALLOC1_INTERFACE ("update", IN, SOUTH, "Update interface", _param->_nb_inst_update);96 ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("Update interface"), _param->_nb_inst_update); 93 97 94 98 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); … … 100 104 ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 101 105 ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 106 107 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 102 108 } 103 109 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/include/Branch_Target_Buffer.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 28 29 delete in_NRESET; 29 30 30 delete [] in_PREDICT_VAL ; 31 delete [] out_PREDICT_ACK ; 32 if (_param->_have_port_context_id) 33 delete [] in_PREDICT_CONTEXT_ID ; 34 delete [] in_PREDICT_ADDRESS ; 35 delete [] out_PREDICT_HIT ; 36 delete [] out_PREDICT_ADDRESS_SRC ; 37 delete [] out_PREDICT_ADDRESS_DEST ; 38 delete [] out_PREDICT_CONDITION ; 39 delete [] out_PREDICT_LAST_TAKE ; 40 delete [] out_PREDICT_IS_ACCURATE ; 31 DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); 32 DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); 33 DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); 34 DELETE1_SIGNAL( in_PREDICT_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); 35 DELETE1_SIGNAL(out_PREDICT_HIT ,_param->_nb_inst_predict,1); 36 DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_size_instruction_address); 37 DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_size_instruction_address); 38 DELETE1_SIGNAL(out_PREDICT_CONDITION ,_param->_nb_inst_predict,_param->_size_branch_condition); 39 DELETE1_SIGNAL(out_PREDICT_LAST_TAKE ,_param->_nb_inst_predict,1); 40 DELETE1_SIGNAL(out_PREDICT_IS_ACCURATE ,_param->_nb_inst_predict,1); 41 41 42 delete [] in_DECOD_VAL ; 43 delete [] out_DECOD_ACK ; 44 if (_param->_have_port_context_id) 45 delete [] in_DECOD_CONTEXT_ID ; 46 delete [] in_DECOD_ADDRESS_SRC ; 47 delete [] in_DECOD_ADDRESS_DEST ; 48 delete [] in_DECOD_CONDITION ; 49 delete [] in_DECOD_LAST_TAKE ; 50 delete [] in_DECOD_MISS_PREDICTION ; 51 delete [] in_DECOD_IS_ACCURATE ; 42 DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); 43 DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); 44 DELETE1_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id); 45 DELETE1_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); 46 DELETE1_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); 47 DELETE1_SIGNAL( in_DECOD_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); 48 DELETE1_SIGNAL( in_DECOD_LAST_TAKE ,_param->_nb_inst_decod,1); 49 DELETE1_SIGNAL( in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod,1); 50 DELETE1_SIGNAL( in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod,1); 52 51 53 delete [] in_UPDATE_VAL ; 54 delete [] out_UPDATE_ACK ; 55 if (_param->_have_port_context_id) 56 delete [] in_UPDATE_CONTEXT_ID ; 57 delete [] in_UPDATE_ADDRESS_SRC ; 58 delete [] in_UPDATE_ADDRESS_DEST ; 59 delete [] in_UPDATE_CONDITION ; 60 delete [] in_UPDATE_LAST_TAKE ; 61 delete [] in_UPDATE_MISS_PREDICTION; 52 DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); 53 DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); 54 DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); 55 DELETE1_SIGNAL( in_UPDATE_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); 56 DELETE1_SIGNAL( in_UPDATE_ADDRESS_DEST ,_param->_nb_inst_update,_param->_size_instruction_address); 57 DELETE1_SIGNAL( in_UPDATE_CONDITION ,_param->_nb_inst_update,_param->_size_branch_condition); 58 DELETE1_SIGNAL( in_UPDATE_LAST_TAKE ,_param->_nb_inst_update,1); 59 DELETE1_SIGNAL( in_UPDATE_MISS_PREDICTION,_param->_nb_inst_update,1); 62 60 } 63 61 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp
r88 r112 51 51 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 52 52 53 ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t,_param->_nb_inst_predict); 54 ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t,_param->_nb_inst_predict); 55 ALLOC1_SC_SIGNAL( in_PREDICT_ADDRESS_SRC ," in_PREDICT_ADDRESS_SRC ",Taddress_t,_param->_nb_inst_predict); 56 ALLOC1_SC_SIGNAL( in_PREDICT_STATIC ," in_PREDICT_STATIC ",Tcontrol_t,_param->_nb_inst_predict); 57 ALLOC1_SC_SIGNAL( in_PREDICT_LAST_TAKE ," in_PREDICT_LAST_TAKE ",Tcontrol_t,_param->_nb_inst_predict); 58 ALLOC1_SC_SIGNAL(out_PREDICT_HISTORY ,"out_PREDICT_HISTORY ",Thistory_t,_param->_nb_inst_predict); 59 ALLOC1_SC_SIGNAL(out_PREDICT_DIRECTION ,"out_PREDICT_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); 60 ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_VAL ,"out_PREDICT_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_predict); 61 ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_ACK ," in_PREDICT_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_predict); 62 ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_ADDRESS_SRC,"out_PREDICT_PREDICTOR_ADDRESS_SRC",Taddress_t,_param->_nb_inst_predict); 63 ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_HISTORY ," in_PREDICT_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_predict); 64 ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_DIRECTION ," in_PREDICT_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); 65 ALLOC1_SC_SIGNAL( in_UPDATE_VAL ," in_UPDATE_VAL ",Tcontrol_t,_param->_nb_inst_update); 66 ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t,_param->_nb_inst_update); 67 ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); 68 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); 69 ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 70 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_VAL ,"out_UPDATE_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_update); 71 ALLOC1_SC_SIGNAL( in_UPDATE_PREDICTOR_ACK ," in_UPDATE_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_update); 72 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_ADDRESS ,"out_UPDATE_PREDICTOR_ADDRESS ",Taddress_t,_param->_nb_inst_update); 73 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,"out_UPDATE_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_update); 74 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,"out_UPDATE_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 53 ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t,_param->_nb_inst_predict); 54 ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t,_param->_nb_inst_predict); 55 ALLOC1_SC_SIGNAL( in_PREDICT_ADDRESS_SRC ," in_PREDICT_ADDRESS_SRC ",Taddress_t,_param->_nb_inst_predict); 56 ALLOC1_SC_SIGNAL( in_PREDICT_STATIC ," in_PREDICT_STATIC ",Tcontrol_t,_param->_nb_inst_predict); 57 ALLOC1_SC_SIGNAL( in_PREDICT_LAST_TAKE ," in_PREDICT_LAST_TAKE ",Tcontrol_t,_param->_nb_inst_predict); 58 ALLOC1_SC_SIGNAL(out_PREDICT_HISTORY ,"out_PREDICT_HISTORY ",Thistory_t,_param->_nb_inst_predict); 59 ALLOC1_SC_SIGNAL(out_PREDICT_DIRECTION ,"out_PREDICT_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); 60 ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_VAL ,"out_PREDICT_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_predict); 61 ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_ACK ," in_PREDICT_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_predict); 62 ALLOC1_SC_SIGNAL(out_PREDICT_PREDICTOR_ADDRESS_SRC ,"out_PREDICT_PREDICTOR_ADDRESS_SRC ",Taddress_t,_param->_nb_inst_predict); 63 ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_HISTORY ," in_PREDICT_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_predict); 64 ALLOC1_SC_SIGNAL( in_PREDICT_PREDICTOR_DIRECTION ," in_PREDICT_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_predict); 65 ALLOC1_SC_SIGNAL( in_UPDATE_VAL ," in_UPDATE_VAL ",Tcontrol_t,_param->_nb_inst_update); 66 ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t,_param->_nb_inst_update); 67 ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); 68 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); 69 ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 70 ALLOC1_SC_SIGNAL( in_UPDATE_PREDICTION_IFETCH ," in_UPDATE_PREDICTION_IFETCH ",Tcontrol_t,_param->_nb_inst_update); 71 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_VAL ,"out_UPDATE_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_inst_update); 72 ALLOC1_SC_SIGNAL( in_UPDATE_PREDICTOR_ACK ," in_UPDATE_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_inst_update); 73 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_ADDRESS ,"out_UPDATE_PREDICTOR_ADDRESS ",Taddress_t,_param->_nb_inst_update); 74 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,"out_UPDATE_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_inst_update); 75 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,"out_UPDATE_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 76 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTOR_PREDICTION_IFETCH ,"out_UPDATE_PREDICTOR_PREDICTION_IFETCH ",Tcontrol_t,_param->_nb_inst_update); 75 77 76 78 /******************************************************** … … 83 85 (*(_Direction_Glue->in_NRESET)) (*(in_NRESET)); 84 86 85 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_VAL ,_param->_nb_inst_predict); 86 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_ACK ,_param->_nb_inst_predict); 87 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict); 88 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_STATIC ,_param->_nb_inst_predict); 89 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_LAST_TAKE ,_param->_nb_inst_predict); 90 if (_param->_have_port_history) 91 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_HISTORY ,_param->_nb_inst_predict); 92 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_DIRECTION ,_param->_nb_inst_predict); 93 if (_param->_have_component_meta_predictor) 94 { 95 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_VAL ,_param->_nb_inst_predict); 96 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_ACK ,_param->_nb_inst_predict); 97 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_ADDRESS_SRC,_param->_nb_inst_predict); 98 if (_param->_have_port_history) 99 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_HISTORY ,_param->_nb_inst_predict); 100 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_DIRECTION ,_param->_nb_inst_predict); 101 } 102 103 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_VAL ,_param->_nb_inst_update ); 104 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_ACK ,_param->_nb_inst_update ); 105 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_ADDRESS ,_param->_nb_inst_update ); 106 if (_param->_have_port_history) 107 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_HISTORY ,_param->_nb_inst_update ); 108 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_DIRECTION ,_param->_nb_inst_update ); 109 if (_param->_have_component_meta_predictor) 110 { 111 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_VAL ,_param->_nb_inst_update ); 112 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_PREDICTOR_ACK ,_param->_nb_inst_update ); 113 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_ADDRESS ,_param->_nb_inst_update ); 114 if (_param->_have_port_history) 115 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_inst_update ); 116 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_inst_update ); 87 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_VAL ,_param->_nb_inst_predict); 88 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_ACK ,_param->_nb_inst_predict); 89 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_ADDRESS_SRC ,_param->_nb_inst_predict); 90 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_STATIC ,_param->_nb_inst_predict); 91 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_LAST_TAKE ,_param->_nb_inst_predict); 92 if (_param->_have_port_history) 93 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_HISTORY ,_param->_nb_inst_predict); 94 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_DIRECTION ,_param->_nb_inst_predict); 95 if (_param->_have_component_meta_predictor) 96 { 97 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_VAL ,_param->_nb_inst_predict); 98 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_ACK ,_param->_nb_inst_predict); 99 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_PREDICT_PREDICTOR_ADDRESS_SRC ,_param->_nb_inst_predict); 100 if (_param->_have_port_history) 101 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_HISTORY ,_param->_nb_inst_predict); 102 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_PREDICT_PREDICTOR_DIRECTION ,_param->_nb_inst_predict); 103 } 104 105 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_VAL ,_param->_nb_inst_update ); 106 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_ACK ,_param->_nb_inst_update ); 107 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_ADDRESS ,_param->_nb_inst_update ); 108 if (_param->_have_port_history) 109 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_HISTORY ,_param->_nb_inst_update ); 110 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_DIRECTION ,_param->_nb_inst_update ); 111 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update ); 112 if (_param->_have_component_meta_predictor) 113 { 114 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_VAL ,_param->_nb_inst_update ); 115 INSTANCE1_SC_SIGNAL(_Direction_Glue, in_UPDATE_PREDICTOR_ACK ,_param->_nb_inst_update ); 116 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_ADDRESS ,_param->_nb_inst_update ); 117 if (_param->_have_port_history) 118 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_inst_update ); 119 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_inst_update ); 120 INSTANCE1_SC_SIGNAL(_Direction_Glue,out_UPDATE_PREDICTOR_PREDICTION_IFETCH ,_param->_nb_inst_update ); 117 121 } 118 122 … … 163 167 in_UPDATE_HISTORY [i]->write(range<Thistory_t>(rand(),_param->_size_history)); 164 168 in_UPDATE_DIRECTION [i]->write(rand()%2); 169 in_UPDATE_PREDICTION_IFETCH [i]->write(rand()%2); 165 170 in_UPDATE_PREDICTOR_ACK [i]->write(rand()%2); 166 171 } … … 228 233 case PREDICTOR_CUSTOM : 229 234 { 230 TEST(Tcontrol_t,out_UPDATE_ACK [i]->read(), in_UPDATE_PREDICTOR_ACK [i]->read()); 231 TEST(Tcontrol_t,out_UPDATE_PREDICTOR_VAL [i]->read(), in_UPDATE_VAL [i]->read()); 232 TEST(Taddress_t,out_UPDATE_PREDICTOR_ADDRESS [i]->read(), in_UPDATE_ADDRESS [i]->read()); 233 TEST(Thistory_t,out_UPDATE_PREDICTOR_HISTORY [i]->read(), in_UPDATE_HISTORY [i]->read()); 234 TEST(Tcontrol_t,out_UPDATE_PREDICTOR_DIRECTION [i]->read(), in_UPDATE_DIRECTION [i]->read()); 235 TEST(Tcontrol_t,out_UPDATE_ACK [i]->read(), in_UPDATE_PREDICTOR_ACK [i]->read()); 236 TEST(Tcontrol_t,out_UPDATE_PREDICTOR_VAL [i]->read(), in_UPDATE_VAL [i]->read()); 237 TEST(Taddress_t,out_UPDATE_PREDICTOR_ADDRESS [i]->read(), in_UPDATE_ADDRESS [i]->read()); 238 TEST(Thistory_t,out_UPDATE_PREDICTOR_HISTORY [i]->read(), in_UPDATE_HISTORY [i]->read()); 239 TEST(Tcontrol_t,out_UPDATE_PREDICTOR_DIRECTION [i]->read(), in_UPDATE_DIRECTION [i]->read()); 240 TEST(Tcontrol_t,out_UPDATE_PREDICTOR_PREDICTION_IFETCH[i]->read(), in_UPDATE_PREDICTION_IFETCH [i]->read()); 235 241 236 242 break; … … 281 287 delete [] in_UPDATE_HISTORY ; 282 288 delete [] in_UPDATE_DIRECTION ; 289 delete [] in_UPDATE_PREDICTION_IFETCH ; 283 290 delete [] out_UPDATE_PREDICTOR_VAL ; 284 291 delete [] in_UPDATE_PREDICTOR_ACK ; … … 286 293 delete [] out_UPDATE_PREDICTOR_HISTORY ; 287 294 delete [] out_UPDATE_PREDICTOR_DIRECTION ; 295 delete [] out_UPDATE_PREDICTOR_PREDICTION_IFETCH; 288 296 #endif 289 297 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Direction_Glue.h
r82 r112 79 79 80 80 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 81 public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; 82 public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; 83 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; 84 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; 85 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; 81 public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; 82 public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; 83 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; 84 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; 85 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; 86 public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTION_IFETCH ; 86 87 87 public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_VAL ; 88 public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTOR_ACK ; 89 public : SC_OUT(Taddress_t) ** out_UPDATE_PREDICTOR_ADDRESS ; 90 public : SC_OUT(Thistory_t) ** out_UPDATE_PREDICTOR_HISTORY ; 91 public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_DIRECTION; 88 public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_VAL ; 89 public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTOR_ACK ; 90 public : SC_OUT(Taddress_t) ** out_UPDATE_PREDICTOR_ADDRESS ; 91 public : SC_OUT(Thistory_t) ** out_UPDATE_PREDICTOR_HISTORY ; 92 public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_DIRECTION ; 93 public : SC_OUT(Tcontrol_t) ** out_UPDATE_PREDICTOR_PREDICTION_IFETCH; 92 94 93 95 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp
r107 r112 215 215 // sensitive << (*(in_CLOCK)).neg(); // don't use internal register 216 216 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 217 sensitive << (*(in_UPDATE_VAL [i])) 218 << (*(in_UPDATE_PREDICTOR_ACK [i])) 219 << (*(in_UPDATE_ADDRESS [i])) 220 << (*(in_UPDATE_HISTORY [i])) 221 << (*(in_UPDATE_DIRECTION [i])); 217 sensitive << (*(in_UPDATE_VAL [i])) 218 << (*(in_UPDATE_PREDICTOR_ACK [i])) 219 << (*(in_UPDATE_ADDRESS [i])) 220 << (*(in_UPDATE_HISTORY [i])) 221 << (*(in_UPDATE_DIRECTION [i])) 222 << (*(in_UPDATE_PREDICTION_IFETCH [i])) 223 ; 222 224 223 225 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp
r88 r112 59 59 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("predict", IN, SOUTH, "predict's interface", _param->_nb_inst_predict);61 ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("predict's interface"), _param->_nb_inst_predict); 62 62 63 63 ALLOC1_SIGNAL_IN ( in_PREDICT_VAL ,"val" ,Tcontrol_t,1); … … 68 68 ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"history" ,Thistory_t,_param->_size_history); 69 69 ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"direction" ,Tcontrol_t,1); 70 if (_param->_have_component_meta_predictor) 71 { 70 71 if (_param->_have_component_meta_predictor) 72 { 72 73 ALLOC1_SIGNAL_OUT(out_PREDICT_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); 73 74 ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); … … 76 77 ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_DIRECTION ,"predictor_direction" ,Tcontrol_t,1); 77 78 } 79 80 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 78 81 } 79 82 80 83 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 81 84 { 82 ALLOC1_INTERFACE ("update", IN, SOUTH, "update's interface", _param->_nb_inst_update);85 ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update's interface"), _param->_nb_inst_update); 83 86 84 ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t,1); 85 ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t,1); 86 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 87 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); 88 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); 87 ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t,1); 88 ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t,1); 89 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 90 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); 91 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); 92 ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t,1); 93 89 94 if (_param->_have_component_meta_predictor) 90 95 { 91 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); 92 ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); 93 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_ADDRESS ,"predictor_address" ,Taddress_t,_param->_size_instruction_address); 94 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"predictor_history" ,Thistory_t,_param->_size_history); 95 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION,"predictor_direction",Tcontrol_t,1); 96 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); 97 ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); 98 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_ADDRESS ,"predictor_address" ,Taddress_t,_param->_size_instruction_address); 99 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"predictor_history" ,Thistory_t,_param->_size_history); 100 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION ,"predictor_direction" ,Tcontrol_t,1); 101 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_PREDICTION_IFETCH,"predictor_prediction_ifetch",Tcontrol_t,1); 96 102 } 103 104 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 97 105 } 98 106 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Direction_Glue.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 delete [] in_PREDICT_VAL ; 32 delete [] out_PREDICT_ACK ; 33 delete [] in_PREDICT_ADDRESS_SRC ; 34 delete [] in_PREDICT_STATIC ; 35 delete [] in_PREDICT_LAST_TAKE ; 36 if (_param->_have_port_history) 37 delete [] out_PREDICT_HISTORY ; 38 delete [] out_PREDICT_DIRECTION ; 39 if (_param->_have_component_meta_predictor) 40 { 41 delete [] out_PREDICT_PREDICTOR_VAL ; 42 delete [] in_PREDICT_PREDICTOR_ACK ; 43 delete [] out_PREDICT_PREDICTOR_ADDRESS_SRC; 44 if (_param->_have_port_history) 45 delete [] in_PREDICT_PREDICTOR_HISTORY ; 46 delete [] in_PREDICT_PREDICTOR_DIRECTION ; 47 } 48 delete [] in_UPDATE_VAL ; 49 delete [] out_UPDATE_ACK ; 50 delete [] in_UPDATE_ADDRESS ; 51 if (_param->_have_port_history) 52 delete [] in_UPDATE_HISTORY ; 53 delete [] in_UPDATE_DIRECTION ; 54 if (_param->_have_component_meta_predictor) 55 { 56 delete [] out_UPDATE_PREDICTOR_VAL ; 57 delete [] in_UPDATE_PREDICTOR_ACK ; 58 delete [] out_UPDATE_PREDICTOR_ADDRESS ; 59 if (_param->_have_port_history) 60 delete [] out_UPDATE_PREDICTOR_HISTORY ; 61 delete [] out_UPDATE_PREDICTOR_DIRECTION; 62 } 32 DELETE1_SIGNAL( in_PREDICT_VAL , _param->_nb_inst_predict,1); 33 DELETE1_SIGNAL(out_PREDICT_ACK , _param->_nb_inst_predict,1); 34 DELETE1_SIGNAL( in_PREDICT_ADDRESS_SRC , _param->_nb_inst_predict,_param->_size_instruction_address); 35 DELETE1_SIGNAL( in_PREDICT_STATIC , _param->_nb_inst_predict,1); 36 DELETE1_SIGNAL( in_PREDICT_LAST_TAKE , _param->_nb_inst_predict,1); 37 DELETE1_SIGNAL(out_PREDICT_HISTORY , _param->_nb_inst_predict,_param->_size_history); 38 DELETE1_SIGNAL(out_PREDICT_DIRECTION , _param->_nb_inst_predict,1); 39 if (_param->_have_component_meta_predictor) 40 { 41 DELETE1_SIGNAL(out_PREDICT_PREDICTOR_VAL , _param->_nb_inst_predict,1); 42 DELETE1_SIGNAL( in_PREDICT_PREDICTOR_ACK , _param->_nb_inst_predict,1); 43 DELETE1_SIGNAL(out_PREDICT_PREDICTOR_ADDRESS_SRC, _param->_nb_inst_predict,_param->_size_instruction_address); 44 DELETE1_SIGNAL( in_PREDICT_PREDICTOR_HISTORY , _param->_nb_inst_predict,_param->_size_history); 45 DELETE1_SIGNAL( in_PREDICT_PREDICTOR_DIRECTION , _param->_nb_inst_predict,1); 46 } 47 48 DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); 49 DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); 50 DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); 51 DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); 52 DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1); 53 DELETE1_SIGNAL( in_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update,1); 54 if (_param->_have_component_meta_predictor) 55 { 56 DELETE1_SIGNAL(out_UPDATE_PREDICTOR_VAL ,_param->_nb_inst_update,1); 57 DELETE1_SIGNAL( in_UPDATE_PREDICTOR_ACK ,_param->_nb_inst_update,1); 58 DELETE1_SIGNAL(out_UPDATE_PREDICTOR_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); 59 DELETE1_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_inst_update,_param->_size_history); 60 DELETE1_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_inst_update,1); 61 DELETE1_SIGNAL(out_UPDATE_PREDICTOR_PREDICTION_IFETCH,_param->_nb_inst_update,1); 62 } 63 63 } 64 64 65 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 65 66 66 delete _component; 67 67 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_genMealy_update.cpp
r107 r112 28 28 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 29 29 { 30 PORT_WRITE(out_UPDATE_PREDICTOR_VAL [i], PORT_READ(in_UPDATE_VAL [i])); 31 PORT_WRITE(out_UPDATE_ACK [i], PORT_READ(in_UPDATE_PREDICTOR_ACK [i])); 32 PORT_WRITE(out_UPDATE_PREDICTOR_ADDRESS [i], PORT_READ(in_UPDATE_ADDRESS [i])); 33 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [i], PORT_READ(in_UPDATE_HISTORY [i])); 34 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [i], PORT_READ(in_UPDATE_DIRECTION [i])); 30 PORT_WRITE(out_UPDATE_PREDICTOR_VAL [i], PORT_READ(in_UPDATE_VAL [i])); 31 PORT_WRITE(out_UPDATE_ACK [i], PORT_READ(in_UPDATE_PREDICTOR_ACK [i])); 32 PORT_WRITE(out_UPDATE_PREDICTOR_ADDRESS [i], PORT_READ(in_UPDATE_ADDRESS [i])); 33 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [i], PORT_READ(in_UPDATE_HISTORY [i])); 34 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [i], PORT_READ(in_UPDATE_DIRECTION [i])); 35 PORT_WRITE(out_UPDATE_PREDICTOR_PREDICTION_IFETCH [i], PORT_READ(in_UPDATE_PREDICTION_IFETCH [i])); 35 36 } 36 37 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/SelfTest/src/test.cpp
r111 r112 64 64 ALLOC1_SC_SIGNAL(out_UPDATE_ACK ,"out_UPDATE_ACK ",Tcontrol_t,_param->_nb_inst_update); 65 65 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); 66 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ," in_UPDATE_HISTORY_VAL ",Tcontrol_t,_param->_nb_inst_update); 66 67 ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 67 68 ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_VAL ,"out_UPDATE_PREDICTOR_VAL ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); 68 69 ALLOC2_SC_SIGNAL( in_UPDATE_PREDICTOR_ACK ," in_UPDATE_PREDICTOR_ACK ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); 69 70 ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,"out_UPDATE_PREDICTOR_HISTORY ",Thistory_t,_param->_nb_predictor,_param->_nb_inst_update); 71 ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_HISTORY_VAL ,"out_UPDATE_PREDICTOR_HISTORY_VAL ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); 70 72 ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,"out_UPDATE_PREDICTOR_DIRECTION ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); 71 73 ALLOC2_SC_SIGNAL(out_UPDATE_PREDICTOR_MISS ,"out_UPDATE_PREDICTOR_MISS ",Tcontrol_t,_param->_nb_predictor,_param->_nb_inst_update); … … 100 102 INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_ACK ,_param->_nb_inst_update); 101 103 INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_HISTORY ,_param->_nb_inst_update); 104 INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); 102 105 INSTANCE1_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_DIRECTION ,_param->_nb_inst_update); 103 106 … … 105 108 INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue, in_UPDATE_PREDICTOR_ACK ,_param->_nb_predictor,_param->_nb_inst_update); 106 109 INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_predictor,_param->_nb_inst_update); 110 INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_PREDICTOR_HISTORY_VAL ,_param->_nb_predictor,_param->_nb_inst_update); 107 111 INSTANCE2_SC_SIGNAL(_Meta_Predictor_Glue,out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_predictor,_param->_nb_inst_update); 108 112 for (uint32_t i=0; i<_param->_nb_predictor; ++i) … … 169 173 DELETE1_SC_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update); 170 174 DELETE1_SC_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update); 175 DELETE1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); 171 176 DELETE1_SC_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update); 172 177 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h
r111 r112 83 83 public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ;// [nb_inst_update] 84 84 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ;// [nb_inst_update] 85 public : SC_IN (Tcontrol_t) ** in_UPDATE_HISTORY_VAL ;// [nb_inst_update] 85 86 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ;// [nb_inst_update] 86 87 … … 88 89 public : SC_IN (Tcontrol_t) *** in_UPDATE_PREDICTOR_ACK ;//[nb_predictor][nb_inst_update] 89 90 public : SC_OUT(Thistory_t) *** out_UPDATE_PREDICTOR_HISTORY ;//[nb_predictor][nb_inst_update] 91 public : SC_OUT(Tcontrol_t) *** out_UPDATE_PREDICTOR_HISTORY_VAL ;//[nb_predictor][nb_inst_update] 90 92 public : SC_OUT(Tcontrol_t) *** out_UPDATE_PREDICTOR_DIRECTION ;//[nb_predictor][nb_inst_update] 91 93 public : SC_OUT(Tcontrol_t) *** out_UPDATE_PREDICTOR_MISS ;//[nb_predictor][nb_inst_update] // if update_on_prediction -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue.cpp
r111 r112 101 101 // sensitive << (*(in_CLOCK)).neg(); // don't need internal register 102 102 for (uint32_t i=0; i<_param->_nb_inst_update; ++i) 103 sensitive << (*(in_UPDATE_HISTORY [i])) 104 << (*(in_UPDATE_DIRECTION [i])); 103 sensitive << (*(in_UPDATE_HISTORY [i])) 104 << (*(in_UPDATE_HISTORY_VAL [i])) 105 << (*(in_UPDATE_DIRECTION [i])); 105 106 106 107 # ifdef SYSTEMCASS_SPECIFIC -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_allocation.cpp
r111 r112 61 61 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 62 62 { 63 ALLOC1_INTERFACE ("predict",IN,NORTH,_("Predict next address"),_param->_nb_inst_predict);63 ALLOC1_INTERFACE_BEGIN("predict",IN,NORTH,_("Predict next address"),_param->_nb_inst_predict); 64 64 65 65 ALLOC1_SIGNAL_IN ( in_PREDICT_VAL ,"VAL" ,Tcontrol_t,1); … … 67 67 ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); 68 68 ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"DIRECTION" ,Tcontrol_t,1); 69 70 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 69 71 } 70 72 71 73 { 72 ALLOC2_INTERFACE ("predict_predictor",IN,NORTH,_("Predict next address"),_param->_nb_predictor,_param->_nb_inst_predict);74 ALLOC2_INTERFACE_BEGIN("predict_predictor",IN,NORTH,_("Predict next address"),_param->_nb_predictor,_param->_nb_inst_predict); 73 75 74 76 ALLOC2_SIGNAL_OUT(out_PREDICT_PREDICTOR_VAL ,"VAL" ,Tcontrol_t,1); … … 78 80 ALLOC2_SIGNAL_OUT(out_PREDICT_PREDICTOR_DIRECTION_VAL,"DIRECTION_VAL",Tcontrol_t,(_param->_predictor_update_on_prediction [it1])?1:0); 79 81 ALLOC2_SIGNAL_OUT(out_PREDICT_PREDICTOR_DIRECTION ,"DIRECTION" ,Tcontrol_t,(_param->_predictor_update_on_prediction [it1])?1:0); 82 83 ALLOC2_INTERFACE_END(_param->_nb_predictor,_param->_nb_inst_predict); 80 84 } 81 85 82 86 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 83 87 { 84 ALLOC1_INTERFACE ("update",IN,NORTH,_("Update predictor"),_param->_nb_inst_update);88 ALLOC1_INTERFACE_BEGIN("update",IN,NORTH,_("Update predictor"),_param->_nb_inst_update); 85 89 86 90 ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"VAL" ,Tcontrol_t,1); 87 91 ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ACK" ,Tcontrol_t,1); 88 92 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); 93 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1); 89 94 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"DIRECTION" ,Tcontrol_t,1); 95 96 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 90 97 } 91 98 { 92 ALLOC2_INTERFACE ("update_predictor",IN,NORTH,_("Update predictor"),_param->_nb_predictor,_param->_nb_inst_update);99 ALLOC2_INTERFACE_BEGIN("update_predictor",IN,NORTH,_("Update predictor"),_param->_nb_predictor,_param->_nb_inst_update); 93 100 94 101 ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"VAL" ,Tcontrol_t,1); 95 102 ALLOC2_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"ACK" ,Tcontrol_t,1); 96 103 ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"HISTORY" ,Thistory_t,_param->_predictor_size_history[it1]); 104 ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1); 97 105 ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION ,"DIRECTION" ,Tcontrol_t,1); 98 106 ALLOC2_SIGNAL_OUT(out_UPDATE_PREDICTOR_MISS ,"MISS" ,Tcontrol_t,(_param->_predictor_update_on_prediction [it1])?1:0); 107 108 ALLOC2_INTERFACE_END(_param->_nb_predictor,_param->_nb_inst_update); 99 109 } 100 110 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_deallocation.cpp
r111 r112 46 46 DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); 47 47 DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); 48 DELETE1_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update,1); 48 49 DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1); 49 50 … … 51 52 DELETE2_SIGNAL( in_UPDATE_PREDICTOR_ACK ,_param->_nb_predictor,_param->_nb_inst_update,1); 52 53 DELETE2_SIGNAL(out_UPDATE_PREDICTOR_HISTORY ,_param->_nb_predictor,_param->_nb_inst_update,_param->_predictor_size_history[it1]); 54 DELETE2_SIGNAL(out_UPDATE_PREDICTOR_HISTORY_VAL ,_param->_nb_predictor,_param->_nb_inst_update,1); 53 55 DELETE2_SIGNAL(out_UPDATE_PREDICTOR_DIRECTION ,_param->_nb_predictor,_param->_nb_inst_update,1); 54 56 DELETE2_SIGNAL(out_UPDATE_PREDICTOR_MISS ,_param->_nb_predictor,_param->_nb_inst_update,(_param->_predictor_update_on_prediction [it1])?1:0); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Meta_Predictor_Glue_genMealy_update.cpp
r111 r112 29 29 for (uint32_t i=0; i<_param->_nb_inst_update; ++i) 30 30 { 31 Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); 32 Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i]); 31 Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); 32 Tcontrol_t history_val = PORT_READ(in_UPDATE_HISTORY_VAL [i]); 33 Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i]); 33 34 34 35 switch (_param->_nb_predictor) … … 38 39 Thistory_t history_0 = history; 39 40 Tcontrol_t direction_old_0 = (history_0>>_param->_predictor_history_shift_msb[0])&1; 40 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); 41 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); 41 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); 42 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [0][i],history_val); 43 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); 42 44 if (_param->_predictor_update_on_prediction [0]) 43 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0);45 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0); 44 46 45 47 break; … … 83 85 (not direction and direction_old_0)); 84 86 85 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction);86 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [1][i],direction);87 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [2][i],direction_new_2);87 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [0][i],direction); 88 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [1][i],direction); 89 PORT_WRITE(out_UPDATE_PREDICTOR_DIRECTION [2][i],direction_new_2); 88 90 89 91 if (_param->_predictor_update_on_prediction [0]) 90 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0);92 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [0][i],direction xor direction_old_0); 91 93 if (_param->_predictor_update_on_prediction [1]) 92 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [1][i],direction xor direction_old_1);94 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [1][i],direction xor direction_old_1); 93 95 if (_param->_predictor_update_on_prediction [2]) 94 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [2][i],direction_new_2 xor direction_old_2);96 PORT_WRITE(out_UPDATE_PREDICTOR_MISS [2][i],direction_new_2 xor direction_old_2); 95 97 96 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); 97 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [1][i],history_1); 98 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [2][i],history_2); 98 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [0][i],history_0); 99 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [1][i],history_1); 100 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY [2][i],history_2); 101 102 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [0][i],history_val); 103 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [1][i],history_val); 104 PORT_WRITE(out_UPDATE_PREDICTOR_HISTORY_VAL [2][i],history_val); 99 105 100 106 break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/SelfTest/src/test.cpp
r111 r112 60 60 ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); 61 61 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); 62 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ," in_UPDATE_HISTORY_VAL ",Tcontrol_t,_param->_nb_inst_update); 62 63 ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 63 64 … … 81 82 INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_ADDRESS ,_param->_nb_inst_update); 82 83 INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_HISTORY ,_param->_nb_inst_update); 84 INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); 83 85 INSTANCE1_SC_SIGNAL(_Meta_Predictor, in_UPDATE_DIRECTION ,_param->_nb_inst_update); 84 86 … … 137 139 DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); 138 140 DELETE1_SC_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update); 141 DELETE1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); 139 142 DELETE1_SC_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update); 140 143 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp
r111 r112 63 63 ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update); 64 64 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY ," in_UPDATE_HISTORY ",Thistory_t,_param->_nb_inst_update); 65 ALLOC1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ," in_UPDATE_HISTORY_VAL ",Tcontrol_t,_param->_nb_inst_update); 65 66 ALLOC1_SC_SIGNAL( in_UPDATE_DIRECTION ," in_UPDATE_DIRECTION ",Tcontrol_t,_param->_nb_inst_update); 66 67 ALLOC1_SC_SIGNAL( in_UPDATE_MISS ," in_UPDATE_MISS ",Tcontrol_t,_param->_nb_inst_update); … … 90 91 INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_ADDRESS ,_param->_nb_inst_update); 91 92 INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_HISTORY ,_param->_nb_inst_update); 93 INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); 92 94 INSTANCE1_SC_SIGNAL(_Two_Level_Branch_Predictor, in_UPDATE_DIRECTION ,_param->_nb_inst_update); 93 95 if (_param->_update_on_prediction) … … 155 157 { 156 158 bool val = ((rand()%2)<percent_transaction_update); 157 in_UPDATE_VAL [port]->write(val);158 in_UPDATE_DIRECTION [port]->write(0);159 in_UPDATE_VAL [port]->write(val); 160 in_UPDATE_DIRECTION [port]->write(0); 159 161 160 162 if (_param->_update_on_prediction) 161 in_UPDATE_MISS [port]->write(1); // miss 162 in_UPDATE_HISTORY [port]->write(0); 163 in_UPDATE_ADDRESS [port]->write(bht_num_reg); 163 in_UPDATE_MISS [port]->write(1); // miss 164 in_UPDATE_HISTORY [port]->write(0); 165 in_UPDATE_HISTORY_VAL [port]->write(0); 166 in_UPDATE_ADDRESS [port]->write(bht_num_reg); 164 167 165 168 SC_START(0); … … 185 188 { 186 189 bool val = ((rand()%2)<percent_transaction_update); 187 in_UPDATE_VAL [port]->write(val);188 in_UPDATE_DIRECTION [port]->write(0);190 in_UPDATE_VAL [port]->write(val); 191 in_UPDATE_DIRECTION [port]->write(0); 189 192 190 193 if (_param->_update_on_prediction) 191 in_UPDATE_MISS [port]->write(1); // miss 192 in_UPDATE_HISTORY [port]->write(i<<_param->_bht_history_rshift); 193 in_UPDATE_ADDRESS [port]->write(pht_num_bank<<_param->_pht_address_bank_rshift); 194 in_UPDATE_MISS [port]->write(1); // miss 195 in_UPDATE_HISTORY [port]->write(i<<_param->_bht_history_rshift); 196 in_UPDATE_HISTORY_VAL [port]->write(1); 197 in_UPDATE_ADDRESS [port]->write(pht_num_bank<<_param->_pht_address_bank_rshift); 194 198 195 199 SC_START(0); … … 241 245 DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); 242 246 DELETE1_SC_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update); 247 DELETE1_SC_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update); 243 248 DELETE1_SC_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update); 244 249 DELETE1_SC_SIGNAL( in_UPDATE_MISS ,_param->_nb_inst_update); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Parameters.h
r111 r112 59 59 public : Taddress_t _pht_address_bank_rshift ; 60 60 61 public : Thistory_t _bht_init_take ; 62 public : Thistory_t _bht_init_ntake ; 63 64 public : Thistory_t _pht_init_take ; 65 public : Thistory_t _pht_init_ntake ; 66 61 67 //-----[ methods ]----------------------------------------------------------- 62 68 public : Parameters (uint32_t nb_inst_predict , -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/include/Two_Level_Branch_Predictor.h
r111 r112 80 80 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ;//[nb_inst_update] 81 81 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ;//[nb_inst_update] 82 public : SC_IN (Tcontrol_t) ** in_UPDATE_HISTORY_VAL ;//[nb_inst_update] 82 83 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ;//[nb_inst_update] 83 84 public : SC_IN (Tcontrol_t) ** in_UPDATE_MISS ;//[nb_inst_update] // if update_on_prediction -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Parameters.cpp
r111 r112 44 44 _bht_nb_shifter = (have_bht)?(bht_nb_shifter ):0; 45 45 _have_pht = have_pht ; 46 _pht_size_counter = (have_pht)?(pht_size_counter 47 _pht_nb_counter = (have_pht)?(pht_nb_counter 46 _pht_size_counter = (have_pht)?(pht_size_counter):0; 47 _pht_nb_counter = (have_pht)?(pht_nb_counter ):0; 48 48 _pht_size_address_share = (have_bht and have_pht)?(pht_size_address_share):0; 49 49 _update_on_prediction = update_on_prediction ; … … 54 54 test(); 55 55 56 // history to update_prediction_table : 57 // MSB : pht_history 58 // LSB : bht_history 59 56 60 _size_history = _bht_size_shifter + _pht_size_counter; 57 58 61 _bht_history_mask = gen_mask<Thistory_t>(_bht_size_shifter); 59 62 _bht_history_rshift = 0; … … 67 70 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _pht_history_rshift : %d",_pht_history_rshift); 68 71 72 _bht_init_take = (Thistory_t)(-1)&_bht_history_mask; 73 _bht_init_ntake = 0; 74 _pht_init_take = (1<<(_pht_size_counter-1)); // size = 4 : 1000/2 75 _pht_init_ntake = _pht_init_take-1; // size = 4 : 0111/2 76 77 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _bht_init_take : 0x%x",_bht_init_take ); 78 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _bht_init_ntake : 0x%x",_bht_init_ntake); 79 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _pht_init_take : 0x%x",_pht_init_take ); 80 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * _pht_init_ntake : 0x%x",_pht_init_ntake); 81 69 82 if (_have_bht) 70 83 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_allocation.cpp
r111 r112 59 59 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict);61 ALLOC1_INTERFACE_BEGIN("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict); 62 62 63 63 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 71 71 ALLOC1_SIGNAL_IN ( in_PREDICT_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); 72 72 } 73 74 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 73 75 } 74 76 75 77 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 76 78 { 77 ALLOC1_INTERFACE ("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update);79 ALLOC1_INTERFACE_BEGIN("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update); 78 80 79 81 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); … … 81 83 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"ADDRESS" ,Taddress_t,_param->_size_address); 82 84 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); 85 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1 ); 83 86 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); 84 87 if (_param->_update_on_prediction) 85 88 ALLOC1_SIGNAL_IN ( in_UPDATE_MISS ,"MISS" ,Tcontrol_t,1 ); 89 90 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 86 91 } 92 93 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 94 88 95 if (usage_is_set(_usage,USE_SYSTEMC)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_deallocation.cpp
r111 r112 46 46 DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_address); 47 47 DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); 48 DELETE1_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update,1 ); 48 49 DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1 ); 49 50 if (_param->_update_on_prediction) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/src/Two_Level_Branch_Predictor_transition.cpp
r111 r112 90 90 { 91 91 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * UPDATE [%d]",i); 92 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * miss : %d",PORT_READ(in_UPDATE_MISS [i])); 93 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * update_on_predict: %d",_param->_update_on_prediction); 92 94 93 95 // Update if 94 96 // * update_on_prediction and miss 95 97 // * not update_on_prediction 96 if (not _param->_update_on_prediction or (_param->_update_on_prediction and PORT_READ(in_UPDATE_MISS [i]))) 97 { 98 Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 99 Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); 100 Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i])&1; 98 Tcontrol_t history_val = PORT_READ(in_UPDATE_HISTORY_VAL [i]); 99 100 if (not _param->_update_on_prediction or 101 (_param->_update_on_prediction and PORT_READ(in_UPDATE_MISS [i])) or 102 not history_val // static_prediction 103 ) 104 { 105 Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 106 Thistory_t history = PORT_READ(in_UPDATE_HISTORY [i]); 107 Tcontrol_t direction = PORT_READ(in_UPDATE_DIRECTION [i])&1; 101 108 102 109 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * address : %.8x",address); 103 110 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * direction : %d",direction); 111 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * history_val : %d",direction); 104 112 105 113 Thistory_t pht_bht_history = 0; … … 107 115 if (_param->_have_bht) 108 116 { 117 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht"); 118 109 119 Thistory_t bht_history = (history>>_param->_bht_history_rshift)&_param->_bht_history_mask; 110 120 Thistory_t bht_num_reg = address & _param->_bht_address_mask; 111 121 122 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",bht_history); 123 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_num_reg : %x",bht_num_reg); 124 125 // BHT : shift register 126 if (not history_val) 127 bht_history = (direction)?_param->_bht_init_take:_param->_bht_init_ntake; 128 else 129 bht_history = ((bht_history<<1) | direction)&_param->_bht_history_mask ; 130 112 131 pht_bht_history = bht_history; 113 114 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",bht_history); 115 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_num_reg : %x",bht_num_reg); 116 117 // BHT : shift register 118 119 bht_history = ((bht_history<<1) | direction)&_param->_bht_history_mask ; 120 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (new): %x",bht_history); 132 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (new): %x",bht_history); 121 133 reg_BHT [bht_num_reg] = bht_history; 122 134 } … … 124 136 if (_param->_have_pht) 125 137 { 138 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht"); 139 126 140 Thistory_t pht_history = (history>>_param->_pht_history_rshift)&_param->_pht_history_mask; 127 141 Thistory_t pht_num_reg = pht_bht_history xor ((address&_param->_pht_address_share_mask)<<_param->_pht_address_share_lshift); 128 142 Thistory_t pht_num_bank= (address>>_param->_pht_address_bank_rshift)&_param->_pht_address_bank_mask; 129 143 130 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",pht_bht_history);131 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (old): %x",pht_history);132 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_reg : %x",pht_num_reg);133 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_bank : %x",pht_num_bank);144 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * bht_history (old): %x",pht_bht_history); 145 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (old): %x",pht_history); 146 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_reg : %x",pht_num_reg); 147 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_num_bank : %x",pht_num_bank); 134 148 135 149 // PHT : saturation counter 136 pht_history = (direction==1)?((pht_history<_param->_pht_counter_max)?(pht_history+1):(pht_history)):((pht_history>0)?(pht_history-1):(pht_history)); 137 138 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (new): %x",pht_history); 150 if (not history_val) 151 pht_history = (direction)?_param->_pht_init_take:_param->_pht_init_ntake; 152 else 153 pht_history = (direction==1)?((pht_history<_param->_pht_counter_max)?(pht_history+1):(pht_history)):((pht_history>0)?(pht_history-1):(pht_history)); 154 155 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * pht_history (new): %x",pht_history); 139 156 140 157 reg_PHT [pht_num_bank][pht_num_reg] = pht_history; … … 145 162 146 163 #if defined(DEBUG) and DEBUG_Two_Level_Branch_Predictor and (DEBUG >= DEBUG_TRACE) 147 if ( 0)164 if (1) 148 165 { 149 166 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," * Dump Two_Level_Branch_Predictor"); … … 180 197 for (uint32_t num_bank=0; num_bank <_param->_pht_nb_bank; ++num_bank) 181 198 { 182 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," [%.4d]",num_bank); 183 184 for (uint32_t i=0; i<_param->_pht_size_bank; i+=limit) 185 { 186 std::string str = ""; 199 if (_param->_pht_size_bank == 1) 200 { 201 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," [%.4d][0000] %4x",num_bank,reg_PHT[num_bank][0]); 202 } 203 else 204 { 205 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," [%.4d]",num_bank); 187 206 188 for (uint32_t j=0; j<limit; j++)207 for (uint32_t i=0; i<_param->_pht_size_bank; i+=limit) 189 208 { 190 uint32_t index = i+j; 191 if (index >= _param->_pht_nb_counter) 192 break; 193 else 194 str+=toString("[%.4d] %.4x ",index,reg_PHT[num_bank][index]); 209 std::string str = ""; 210 211 for (uint32_t j=0; j<limit; j++) 212 { 213 uint32_t index = i+j; 214 if (index >= _param->_pht_size_bank) 215 break; 216 else 217 str+=toString("[%.4d] %.4x ",index,reg_PHT[num_bank][index]); 218 } 219 220 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," %s",str.c_str()); 195 221 } 196 197 log_printf(TRACE,Two_Level_Branch_Predictor,FUNCTION," %s",str.c_str());198 222 } 199 223 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/include/Meta_Predictor.h
r111 r112 80 80 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ;//[nb_inst_update] 81 81 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ;//[nb_inst_update] 82 public : SC_IN (Tcontrol_t) ** in_UPDATE_HISTORY_VAL ;//[nb_inst_update] 82 83 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ;//[nb_inst_update] 83 84 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_allocation.cpp
r111 r112 58 58 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict);60 ALLOC1_INTERFACE_BEGIN("predict",IN,WEST,_("Predict direction interface"),_param->_nb_inst_predict); 61 61 62 62 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 65 65 ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); 66 66 ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); 67 68 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 67 69 } 68 70 69 71 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 72 { 71 ALLOC1_INTERFACE ("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update);73 ALLOC1_INTERFACE_BEGIN("update",IN,WEST,_("Update direction interface"),_param->_nb_inst_update); 72 74 73 75 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); … … 75 77 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"ADDRESS" ,Taddress_t,_param->_size_address); 76 78 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"HISTORY" ,Thistory_t,_param->_size_history); 79 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY_VAL ,"HISTORY_VAL" ,Tcontrol_t,1 ); 77 80 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"DIRECTION" ,Tcontrol_t,1 ); 81 82 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 78 83 } 79 84 … … 218 223 COMPONENT_MAP(_component,src , "in_UPDATE_" +toString(j)+"_HISTORY" , 219 224 dest,"out_UPDATE_PREDICTOR_"+toString(i)+"_"+toString(j)+"_HISTORY" ); 225 COMPONENT_MAP(_component,src , "in_UPDATE_" +toString(j)+"_HISTORY_VAL" , 226 dest,"out_UPDATE_PREDICTOR_"+toString(i)+"_"+toString(j)+"_HISTORY_VAL" ); 220 227 if (_param->_predictor_update_on_prediction [i]) 221 228 COMPONENT_MAP(_component,src , "in_UPDATE_" +toString(j)+"_MISS" , … … 286 293 #endif 287 294 288 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , 289 dest, "in_UPDATE_"+toString(i)+"_VAL" ); 290 PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , 291 dest,"out_UPDATE_"+toString(i)+"_ACK" ); 292 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , 293 dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); 294 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION", 295 dest, "in_UPDATE_"+toString(i)+"_DIRECTION"); 296 } 297 298 // out_UPDATE_PREDICTOR_VAL -> two_level_branch_predictor. in_UPDATE_PREDICTOR_VAL 299 // in_UPDATE_PREDICTOR_ACK -> two_level_branch_predictor.out_UPDATE_PREDICTOR_ACK 300 // out_UPDATE_PREDICTOR_HISTORY -> two_level_branch_predictor. in_UPDATE_PREDICTOR_HISTORY 301 // out_UPDATE_PREDICTOR_DIRECTION -> two_level_branch_predictor. in_UPDATE_PREDICTOR_DIRECTION 302 // out_UPDATE_PREDICTOR_MISS -> two_level_branch_predictor. in_UPDATE_PREDICTOR_MISS 295 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , 296 dest, "in_UPDATE_"+toString(i)+"_VAL" ); 297 PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , 298 dest,"out_UPDATE_"+toString(i)+"_ACK" ); 299 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , 300 dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); 301 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY_VAL", 302 dest, "in_UPDATE_"+toString(i)+"_HISTORY_VAL"); 303 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION" , 304 dest, "in_UPDATE_"+toString(i)+"_DIRECTION" ); 305 } 306 307 // out_UPDATE_PREDICTOR_VAL -> two_level_branch_predictor. in_UPDATE_PREDICTOR_VAL 308 // in_UPDATE_PREDICTOR_ACK -> two_level_branch_predictor.out_UPDATE_PREDICTOR_ACK 309 // out_UPDATE_PREDICTOR_HISTORY -> two_level_branch_predictor. in_UPDATE_PREDICTOR_HISTORY 310 // out_UPDATE_PREDICTOR_HISTORY_VAL-> two_level_branch_predictor. in_UPDATE_PREDICTOR_HISTORY 311 // out_UPDATE_PREDICTOR_DIRECTION -> two_level_branch_predictor. in_UPDATE_PREDICTOR_DIRECTION 312 // out_UPDATE_PREDICTOR_MISS -> two_level_branch_predictor. in_UPDATE_PREDICTOR_MISS 303 313 304 314 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp
r111 r112 40 40 DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_address); 41 41 DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); 42 DELETE1_SIGNAL( in_UPDATE_HISTORY_VAL ,_param->_nb_inst_update,1 ); 42 43 DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1 ); 43 44 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp
r111 r112 64 64 if (_have_meta_predictor) 65 65 _predictor_update_on_prediction [_nb_predictor-1] = false; 66 67 // // All predictor can't update on prediction .... 68 // for (uint32_t i=0; i<_nb_predictor; ++i) 69 // _predictor_update_on_prediction [i] = false; 66 70 67 71 _param_two_level_branch_predictor = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::direction::meta_predictor::two_level_branch_predictor::Parameters * [_nb_predictor]; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Direction.h
r111 r112 63 63 64 64 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 65 public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ;66 public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ;67 public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS_SRC ;68 public : SC_IN (Tcontrol_t) ** in_PREDICT_STATIC ;69 public : SC_IN (Tcontrol_t) ** in_PREDICT_LAST_TAKE ;70 public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ;71 public : SC_OUT(Tcontrol_t) ** out_PREDICT_DIRECTION ;65 public : SC_IN (Tcontrol_t) ** in_PREDICT_VAL ; 66 public : SC_OUT(Tcontrol_t) ** out_PREDICT_ACK ; 67 public : SC_IN (Taddress_t) ** in_PREDICT_ADDRESS_SRC ; 68 public : SC_IN (Tcontrol_t) ** in_PREDICT_STATIC ; 69 public : SC_IN (Tcontrol_t) ** in_PREDICT_LAST_TAKE ; 70 public : SC_OUT(Thistory_t) ** out_PREDICT_HISTORY ; 71 public : SC_OUT(Tcontrol_t) ** out_PREDICT_DIRECTION ; 72 72 73 73 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 74 public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; 75 public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; 76 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; 77 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; 78 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; 74 public : SC_IN (Tcontrol_t) ** in_UPDATE_VAL ; 75 public : SC_OUT(Tcontrol_t) ** out_UPDATE_ACK ; 76 public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; 77 public : SC_IN (Thistory_t) ** in_UPDATE_HISTORY ; 78 public : SC_IN (Tcontrol_t) ** in_UPDATE_DIRECTION ; 79 public : SC_IN (Tcontrol_t) ** in_UPDATE_PREDICTION_IFETCH; 79 80 80 81 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp
r111 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 59 59 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 60 { 61 ALLOC1_INTERFACE ("predict", IN, SOUTH, "Interface predict",_param->_nb_inst_predict);61 ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("Interface predict"),_param->_nb_inst_predict); 62 62 63 63 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 68 68 ALLOC1_SIGNAL_OUT(out_PREDICT_HISTORY ,"history" ,Thistory_t,_param->_size_history); 69 69 ALLOC1_SIGNAL_OUT(out_PREDICT_DIRECTION ,"direction" ,Tcontrol_t,1); 70 71 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 70 72 } 71 73 72 74 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 73 75 { 74 ALLOC1_INTERFACE("update", IN, SOUTH, "Interface update",_param->_nb_inst_update); 75 76 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); 77 ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); 78 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 79 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); 80 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION,"direction",Tcontrol_t,1); 76 ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("Interface update"),_param->_nb_inst_update); 77 78 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); 79 ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); 80 ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 81 ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); 82 ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); 83 ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH,"prediction_ifetch",Tcontrol_t,1); 84 85 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 81 86 } 82 87 … … 183 188 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_HISTORY" , 184 189 dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ); 190 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_HISTORY_VAL" , 191 dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_PREDICTION_IFETCH"); 185 192 } 186 193 } … … 212 219 #endif 213 220 214 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_VAL" ,215 dest, "in_PREDICT_"+toString(i)+"_VAL" );216 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_ACK" ,217 dest,"out_PREDICT_"+toString(i)+"_ACK" );218 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_ADDRESS_SRC" ,219 dest, "in_PREDICT_"+toString(i)+"_ADDRESS_SRC" );220 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_STATIC" ,221 dest, "in_PREDICT_"+toString(i)+"_STATIC" );222 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_LAST_TAKE" ,223 dest, "in_PREDICT_"+toString(i)+"_LAST_TAKE" );224 if (_param->_have_port_history) 225 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_HISTORY" ,226 dest,"out_PREDICT_"+toString(i)+"_HISTORY" );227 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_DIRECTION" ,228 dest,"out_PREDICT_"+toString(i)+"_DIRECTION" );229 230 // PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL");231 // PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK");232 // PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC");233 // PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY");234 // PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION");221 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_VAL" , 222 dest, "in_PREDICT_"+toString(i)+"_VAL" ); 223 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_ACK" , 224 dest,"out_PREDICT_"+toString(i)+"_ACK" ); 225 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_ADDRESS_SRC" , 226 dest, "in_PREDICT_"+toString(i)+"_ADDRESS_SRC" ); 227 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_STATIC" , 228 dest, "in_PREDICT_"+toString(i)+"_STATIC" ); 229 PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_LAST_TAKE" , 230 dest, "in_PREDICT_"+toString(i)+"_LAST_TAKE" ); 231 if (_param->_have_port_history) 232 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_HISTORY" , 233 dest,"out_PREDICT_"+toString(i)+"_HISTORY" ); 234 PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_DIRECTION" , 235 dest,"out_PREDICT_"+toString(i)+"_DIRECTION" ); 236 237 // PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_VAL" ); 238 // PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_ACK" ); 239 // PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC" ,dest,"out_PREDICT_"+toString(i)+"_PREDICTOR_ADDRESS_SRC" ); 240 // PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_HISTORY" ); 241 // PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ,dest, "in_PREDICT_"+toString(i)+"_PREDICTOR_DIRECTION" ); 235 242 } 236 243 … … 243 250 #endif 244 251 245 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" ,246 dest, "in_UPDATE_"+toString(i)+"_VAL" );247 PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" ,248 dest,"out_UPDATE_"+toString(i)+"_ACK" );249 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_ADDRESS" ,250 dest, "in_UPDATE_"+toString(i)+"_ADDRESS" );252 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_VAL" , 253 dest, "in_UPDATE_"+toString(i)+"_VAL" ); 254 PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_ACK" , 255 dest,"out_UPDATE_"+toString(i)+"_ACK" ); 256 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_ADDRESS" , 257 dest, "in_UPDATE_"+toString(i)+"_ADDRESS" ); 251 258 if (_param->_have_port_history) 252 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , 253 dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); 254 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION", 255 dest, "in_UPDATE_"+toString(i)+"_DIRECTION"); 256 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ); 257 // PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ); 258 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ); 259 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ); 260 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION",dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION"); 259 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_HISTORY" , 260 dest, "in_UPDATE_"+toString(i)+"_HISTORY" ); 261 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_DIRECTION" , 262 dest, "in_UPDATE_"+toString(i)+"_DIRECTION" ); 263 PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_PREDICTION_IFETCH", 264 dest, "in_UPDATE_"+toString(i)+"_PREDICTION_IFETCH"); 265 266 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_VAL" ); 267 // PORT_MAP(_component,src , "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ,dest, "in_UPDATE_"+toString(i)+"_PREDICTOR_ACK" ); 268 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_ADDRESS" ); 269 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_HISTORY" ); 270 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION" ,dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_DIRECTION" ); 271 // PORT_MAP(_component,src ,"out_UPDATE_"+toString(i)+"_PREDICTOR_PREDICTION_IFETCH",dest,"out_UPDATE_"+toString(i)+"_PREDICTOR_PREDICTION_IFETCH"); 272 261 273 } 262 274 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp
r111 r112 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Direction.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 28 29 delete in_NRESET; 29 30 30 delete [] in_PREDICT_VAL;31 delete [] out_PREDICT_ACK;32 delete [] in_PREDICT_ADDRESS_SRC;33 delete [] in_PREDICT_STATIC;34 delete [] in_PREDICT_LAST_TAKE;35 if (_param->_have_port_history) 36 delete [] out_PREDICT_HISTORY;37 delete [] out_PREDICT_DIRECTION ; 38 delete [] in_UPDATE_VAL;39 delete [] out_UPDATE_ACK;40 delete [] in_UPDATE_ADDRESS;41 if (_param->_have_port_history) 42 delete [] in_UPDATE_HISTORY;43 delete [] in_UPDATE_DIRECTION;31 DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); 32 DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); 33 DELETE1_SIGNAL( in_PREDICT_ADDRESS_SRC,_param->_nb_inst_predict,_param->_size_instruction_address); 34 DELETE1_SIGNAL( in_PREDICT_STATIC ,_param->_nb_inst_predict,1); 35 DELETE1_SIGNAL( in_PREDICT_LAST_TAKE ,_param->_nb_inst_predict,1); 36 DELETE1_SIGNAL(out_PREDICT_HISTORY ,_param->_nb_inst_predict,_param->_size_history); 37 DELETE1_SIGNAL(out_PREDICT_DIRECTION ,_param->_nb_inst_predict,1); 38 39 DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); 40 DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); 41 DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); 42 DELETE1_SIGNAL( in_UPDATE_HISTORY ,_param->_nb_inst_update,_param->_size_history); 43 DELETE1_SIGNAL( in_UPDATE_DIRECTION ,_param->_nb_inst_update,1); 44 DELETE1_SIGNAL( in_UPDATE_PREDICTION_IFETCH,_param->_nb_inst_update,1); 44 45 } 45 46 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp
r110 r112 208 208 { 209 209 if (_param->_have_port_inst_ifetch_ptr) 210 INSTANCE _SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INST_IFETCH_PTR [i]);210 INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INST_IFETCH_PTR [i]); 211 211 if (_param->_have_port_depth) 212 INSTANCE _SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]);212 INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]); 213 213 } 214 214 … … 350 350 // if (_param->_have_port_depth) 351 351 // { 352 // INSTANCE _SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_TAIL [i]);353 // INSTANCE _SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_TAIL [i]);352 // INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_TAIL [i]); 353 // INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_TAIL [i]); 354 354 // } 355 // INSTANCE _SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_NB_BRANCH [i]);356 // INSTANCE _SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_NB_BRANCH [i]);355 // INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_NB_BRANCH [i]); 356 // INSTANCE0_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_NB_BRANCH [i]); 357 357 // } 358 358 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp
r110 r112 47 47 ,IN 48 48 ,SOUTH, 49 "Generalist interface"49 _("Generalist interface") 50 50 #endif 51 51 ); … … 58 58 { 59 59 { 60 ALLOC1_INTERFACE ("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context);60 ALLOC1_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context); 61 61 62 62 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 70 70 ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 71 71 ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 72 } 73 { 74 ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[it1]); 72 73 ALLOC1_INTERFACE_END(_param->_nb_context); 74 } 75 { 76 ALLOC2_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context,_param->_nb_instruction[it1]); 77 75 78 _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[it1]); 76 } 77 78 { 79 ALLOC1_INTERFACE("predict_btb",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); 79 80 ALLOC2_INTERFACE_END(_param->_nb_context,_param->_nb_instruction[it1]); 81 } 82 83 { 84 ALLOC1_INTERFACE_BEGIN("predict_btb",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); 80 85 81 86 ALLOC1_VALACK_OUT(out_PREDICT_BTB_VAL ,VAL); … … 89 94 // ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 90 95 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 91 } 92 93 { 94 ALLOC1_INTERFACE("predict_dir",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); 96 97 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); 98 } 99 100 { 101 ALLOC1_INTERFACE_BEGIN("predict_dir",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); 95 102 96 103 ALLOC1_VALACK_OUT(out_PREDICT_DIR_VAL ,VAL); … … 101 108 // ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_HISTORY ,"history" ,Thistory_t ,_param->_size_history); 102 109 ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); 103 } 104 105 { 106 ALLOC1_INTERFACE("predict_ras",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); 110 111 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); 112 } 113 114 { 115 ALLOC1_INTERFACE_BEGIN("predict_ras",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); 107 116 108 117 ALLOC1_VALACK_OUT(out_PREDICT_RAS_VAL ,VAL); … … 114 123 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS_POP ,"address_pop" ,Taddress_t ,_param->_size_instruction_address); 115 124 // ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); 116 } 117 118 { 119 ALLOC1_INTERFACE("predict_upt",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); 125 126 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); 127 } 128 129 { 130 ALLOC1_INTERFACE_BEGIN("predict_upt",OUT,NORTH,_("Interface with ifetch unit"),_param->_nb_inst_branch_predict); 120 131 121 132 ALLOC1_VALACK_OUT(out_PREDICT_UPT_VAL ,VAL); … … 131 142 ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 132 143 // ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); 144 145 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_predict); 133 146 } 134 147 } … … 137 150 { 138 151 { 139 ALLOC2_INTERFACE ("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);152 ALLOC2_INTERFACE_BEGIN("decod",IN,SOUTH,_("Interface with decod unit"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 140 153 141 154 _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); … … 150 163 _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 151 164 _ALLOC2_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 152 } 153 154 { 155 ALLOC1_INTERFACE("decod_btb",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); 165 166 ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 167 } 168 169 { 170 ALLOC1_INTERFACE_BEGIN("decod_btb",OUT,NORTH,_("Interface with decod unit"),_param->_nb_inst_branch_decod); 156 171 157 172 ALLOC1_VALACK_OUT(out_DECOD_BTB_VAL ,VAL); … … 164 179 ALLOC1_SIGNAL_OUT(out_DECOD_BTB_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); 165 180 ALLOC1_SIGNAL_OUT(out_DECOD_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 166 } 167 168 { 169 ALLOC1_INTERFACE("decod_ras",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); 181 182 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_decod); 183 } 184 185 { 186 ALLOC1_INTERFACE_BEGIN("decod_ras",OUT,NORTH,_("Interface with decod unit"),_param->_nb_inst_branch_decod); 170 187 171 188 ALLOC1_VALACK_OUT(out_DECOD_RAS_VAL ,VAL); … … 178 195 // ALLOC1_SIGNAL_IN ( in_DECOD_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); 179 196 ALLOC1_SIGNAL_OUT(out_DECOD_RAS_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 180 } 181 182 { 183 ALLOC1_INTERFACE("decod_upt",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); 197 198 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_decod); 199 } 200 201 { 202 ALLOC1_INTERFACE_BEGIN("decod_upt",OUT,NORTH,_("Interface with decod unit"),_param->_nb_inst_branch_decod); 184 203 185 204 ALLOC1_VALACK_OUT(out_DECOD_UPT_VAL ,VAL); … … 197 216 ALLOC1_SIGNAL_OUT(out_DECOD_UPT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 198 217 ALLOC1_SIGNAL_IN ( in_DECOD_UPT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); 218 219 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_decod); 199 220 } 200 221 } … … 203 224 { 204 225 { 205 ALLOC1_INTERFACE ("update_btb",OUT,SOUTH,"Interface with update unit",_param->_nb_inst_branch_update);226 ALLOC1_INTERFACE_BEGIN("update_btb",OUT,SOUTH,_("Interface with update unit"),_param->_nb_inst_branch_update); 206 227 207 228 ALLOC1_VALACK_OUT(out_UPDATE_BTB_VAL ,VAL); … … 213 234 // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); 214 235 // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 215 } 216 217 { 218 ALLOC1_INTERFACE("update_dir",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); 236 237 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); 238 } 239 240 { 241 ALLOC1_INTERFACE_BEGIN("update_dir",OUT,NORTH,_("Interface with update unit"),_param->_nb_inst_branch_update); 219 242 220 243 ALLOC1_VALACK_OUT(out_UPDATE_DIR_VAL ,VAL); … … 223 246 // ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_HISTORY ,"history" ,Thistory_t ,_param->_size_history); 224 247 // ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); 225 } 226 227 { 228 ALLOC1_INTERFACE("update_ras",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); 248 249 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); 250 } 251 252 { 253 ALLOC1_INTERFACE_BEGIN("update_ras",OUT,NORTH,_("Interface with update unit"),_param->_nb_inst_branch_update); 229 254 230 255 ALLOC1_VALACK_OUT(out_UPDATE_RAS_VAL ,VAL); … … 236 261 // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 237 262 // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t ,1); 238 } 239 240 { 241 ALLOC1_INTERFACE("update_upt",IN ,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); 263 264 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); 265 } 266 267 { 268 ALLOC1_INTERFACE_BEGIN("update_upt",IN ,NORTH,_("Interface with update unit"),_param->_nb_inst_branch_update); 242 269 243 270 ALLOC1_VALACK_IN ( in_UPDATE_UPT_VAL ,VAL); … … 257 284 // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); 258 285 // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); 286 287 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_update); 259 288 } 260 289 } … … 262 291 // // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 263 292 // { 264 // ALLOC1_INTERFACE ("depth",IN,NORTH,"Interface with depth",_param->_nb_context);293 // ALLOC1_INTERFACE_BEGIN("depth",IN,NORTH,_("Interface with depth"),_param->_nb_context); 265 294 // 266 295 // ALLOC1_SIGNAL_IN ( in_DEPTH_UPT_NB_BRANCH,"upt_nb_branch",Tdepth_t,_param->_size_depth+1); … … 268 297 // ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH ,"nb_branch" ,Tdepth_t,_param->_size_depth+1); 269 298 // ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"tail" ,Tdepth_t,_param->_size_depth); 299 // 300 // ALLOC1_INTERFACE_END(_param->_nb_context); 270 301 // } 271 302 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp
r100 r112 46 46 ,IN 47 47 ,SOUTH, 48 "Generalist interface"48 _("Generalist interface") 49 49 #endif 50 50 ); … … 56 56 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 57 57 { 58 ALLOC1_INTERFACE ("predict", IN, SOUTH, "predict's interface", _param->_nb_inst_predict);58 ALLOC1_INTERFACE_BEGIN("predict", IN, SOUTH, _("predict's interface"), _param->_nb_inst_predict); 59 59 60 60 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 66 66 ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_instruction_address); 67 67 ALLOC1_SIGNAL_OUT(out_PREDICT_INDEX ,"index" ,Tptr_t ,_param->_size_index); 68 69 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 68 70 } 69 71 70 72 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 71 73 { 72 ALLOC1_INTERFACE ("decod", IN, SOUTH, "decod's interface", _param->_nb_inst_decod);74 ALLOC1_INTERFACE_BEGIN("decod", IN, SOUTH, _("decod's interface"), _param->_nb_inst_decod); 73 75 74 76 ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); … … 81 83 ALLOC1_SIGNAL_OUT(out_DECOD_INDEX ,"index" ,Tptr_t ,_param->_size_index); 82 84 ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 85 86 ALLOC1_INTERFACE_END(_param->_nb_inst_decod); 83 87 } 84 88 85 89 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 90 { 87 ALLOC1_INTERFACE ("update", IN, SOUTH, "update's interface", _param->_nb_inst_update);91 ALLOC1_INTERFACE_BEGIN("update", IN, SOUTH, _("update's interface"), _param->_nb_inst_update); 88 92 89 93 ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); … … 96 100 ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); 97 101 ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH,"prediction_ifetch",Tcontrol_t,1); 102 103 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 98 104 } 99 105 … … 101 107 { 102 108 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 109 ALLOC2(reg_stack ,ras_entry_t,_param->_nb_context,_param->_size_queue [it1]); 103 110 104 reg_stack = new ras_entry_t * [_param->_nb_context];105 for (uint32_t i=0; i<_param->_nb_context; i++) 106 reg_stack [i] = new ras_entry_t [_param->_size_queue [i]];111 ALLOC1(reg_TOP ,Tptr_t ,_param->_nb_context); 112 // ALLOC1(reg_BOTTOM ,Tptr_t ,_param->_nb_context); 113 ALLOC1(reg_NB_ELT ,Tptr_t ,_param->_nb_context); 107 114 108 reg_TOP = new Tptr_t [_param->_nb_context];109 // reg_BOTTOM = new Tptr_t [_param->_nb_context];110 reg_NB_ELT = new Tptr_t [_param->_nb_context];115 ALLOC1(reg_PREDICT_TOP ,Tptr_t ,_param->_nb_context); 116 // ALLOC1(reg_PREDICT_BOTTOM ,Tptr_t ,_param->_nb_context); 117 ALLOC1(reg_PREDICT_NB_ELT ,Tptr_t ,_param->_nb_context); 111 118 112 reg_PREDICT_TOP = new Tptr_t [_param->_nb_context]; 113 // reg_PREDICT_BOTTOM = new Tptr_t [_param->_nb_context]; 114 reg_PREDICT_NB_ELT = new Tptr_t [_param->_nb_context]; 115 116 internal_PREDICT_ACK = new Tcontrol_t [_param->_nb_inst_predict]; 117 internal_PREDICT_HIT = new Tcontrol_t [_param->_nb_inst_predict]; 118 internal_DECOD_ACK = new Tcontrol_t [_param->_nb_inst_decod ]; 119 internal_DECOD_HIT = new Tcontrol_t [_param->_nb_inst_decod ]; 120 internal_UPDATE_ACK = new Tcontrol_t [_param->_nb_inst_update ]; 119 ALLOC1(internal_PREDICT_ACK ,Tcontrol_t ,_param->_nb_inst_predict); 120 ALLOC1(internal_PREDICT_HIT ,Tcontrol_t ,_param->_nb_inst_predict); 121 ALLOC1(internal_DECOD_ACK ,Tcontrol_t ,_param->_nb_inst_decod ); 122 ALLOC1(internal_DECOD_HIT ,Tcontrol_t ,_param->_nb_inst_decod ); 123 ALLOC1(internal_UPDATE_ACK ,Tcontrol_t ,_param->_nb_inst_update ); 121 124 } 122 125 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp
r100 r112 59 59 60 60 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 61 62 for (uint32_t i=0; i<_param->_nb_context; i++) 63 delete [] reg_stack [i]; 64 delete [] reg_stack; 65 delete [] reg_TOP; 66 // delete [] reg_BOTTOM; 67 delete [] reg_NB_ELT; 68 delete [] reg_PREDICT_TOP; 69 // delete [] reg_PREDICT_BOTTOM; 70 delete [] reg_PREDICT_NB_ELT; 71 72 delete [] internal_PREDICT_ACK; 73 delete [] internal_PREDICT_HIT; 74 delete [] internal_DECOD_ACK; 75 delete [] internal_DECOD_HIT; 76 delete [] internal_UPDATE_ACK; 61 DELETE2(reg_stack ,_param->_nb_context,_param->_size_queue [it1]); 62 63 DELETE1(reg_TOP ,_param->_nb_context); 64 // DELETE1(reg_BOTTOM ,_param->_nb_context); 65 DELETE1(reg_NB_ELT ,_param->_nb_context); 66 67 DELETE1(reg_PREDICT_TOP ,_param->_nb_context); 68 // DELETE1(reg_PREDICT_BOTTOM ,_param->_nb_context); 69 DELETE1(reg_PREDICT_NB_ELT ,_param->_nb_context); 70 71 DELETE1(internal_PREDICT_ACK ,_param->_nb_inst_predict); 72 DELETE1(internal_PREDICT_HIT ,_param->_nb_inst_predict); 73 DELETE1(internal_DECOD_ACK ,_param->_nb_inst_decod ); 74 DELETE1(internal_DECOD_HIT ,_param->_nb_inst_decod ); 75 DELETE1(internal_UPDATE_ACK ,_param->_nb_inst_update ); 77 76 } 78 77 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r111 r112 126 126 ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update); 127 127 ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update); 128 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,"out_UPDATE_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); 128 129 ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update); 129 130 ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update); … … 137 138 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update); 138 139 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update); 139 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);140 140 141 141 ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); … … 223 223 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update); 224 224 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update); 225 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update); 225 226 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update); 226 227 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update); … … 235 236 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update); 236 237 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); 237 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);238 238 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context); 239 239 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context); … … 575 575 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 576 576 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 577 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 577 578 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 578 579 if (update_btb(it_upt->condition)) … … 593 594 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 594 595 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 595 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);596 596 } 597 597 ++ it_upt; … … 906 906 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 907 907 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 908 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);908 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 909 909 } 910 910 ++ it_upt; … … 1281 1281 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 1282 1282 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 1283 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_ufpt->miss_ifetch);1283 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 1284 1284 } 1285 1285 } … … 1353 1353 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1354 1354 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1355 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);1355 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1356 1356 } 1357 1357 ++ it_upt; … … 1888 1888 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 1889 1889 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 1890 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_ufpt->miss_ifetch);1890 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 1891 1891 } 1892 1892 } … … 1976 1976 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1977 1977 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1978 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);1978 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1979 1979 } 1980 1980 … … 2103 2103 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2104 2104 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2105 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);2105 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2106 2106 } 2107 2107 … … 2544 2544 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 2545 2545 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 2546 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_ufpt->miss_ifetch);2546 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 2547 2547 } 2548 2548 } … … 2637 2637 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2638 2638 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2639 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);2639 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2640 2640 } 2641 2641 // -- it_upt; … … 2763 2763 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2764 2764 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2765 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);2765 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2766 2766 } 2767 2767 … … 2870 2870 delete [] out_UPDATE_MISS_PREDICTION ; 2871 2871 delete [] out_UPDATE_DIRECTION_GOOD ; 2872 delete [] out_UPDATE_PREDICTION_IFETCH ; 2872 2873 delete [] out_UPDATE_BTB_VAL ; 2873 2874 delete [] out_UPDATE_BTB_ADDRESS_SRC ; … … 2881 2882 delete [] out_UPDATE_RAS_ADDRESS ; 2882 2883 delete [] out_UPDATE_RAS_INDEX ; 2883 delete [] out_UPDATE_RAS_PREDICTION_IFETCH;2884 2884 2885 2885 DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r111 r112 88 88 public : Tcontrol_t _ifetch_prediction; // not in ufpt 89 89 90 // to branchement_log_file 90 91 public : bool _retire_ok ; 92 public : bool _miss_prediction ; 91 93 }; 92 94 … … 115 117 #define pop_ras(cond) ((cond == BRANCH_CONDITION_READ_STACK )) 116 118 117 #define need_update(cond) update_ras(cond)119 #define need_update(cond) (update_ras(cond) or update_dir(cond)) 118 120 119 121 }; // end namespace update_prediction_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r111 r112 130 130 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_MISS_PREDICTION ; //[nb_inst_update] 131 131 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIRECTION_GOOD ; //[nb_inst_update] 132 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_PREDICTION_IFETCH ; //[nb_inst_update] 132 133 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_BTB_VAL ; //[nb_inst_update] 133 134 public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_SRC ; //[nb_inst_update] … … 141 142 public : SC_OUT(Taddress_t ) ** out_UPDATE_RAS_ADDRESS ; //[nb_inst_update] 142 143 public : SC_OUT(Tptr_t ) ** out_UPDATE_RAS_INDEX ; //[nb_inst_update] 143 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PREDICTION_IFETCH ; //[nb_inst_update]144 144 145 145 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 183 183 private : bool * reg_EVENT_VAL ; //[nb_context] 184 184 private : uint32_t * reg_EVENT_UPT_PTR ; //[nb_context] 185 private : bool * reg_EVENT_UPT_FULL ; //[nb_context] 185 186 186 187 private : event_state_t * reg_EVENT_STATE ; //[nb_context] 187 private : event_source_t * reg_EVENT_SOURCE; //[nb_context]188 private : bool * reg_EVENT_IS_BRANCH ; //[nb_context] 188 189 private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] 189 190 private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r111 r112 48 48 ,IN 49 49 ,SOUTH, 50 "Generalist interface"50 _("Generalist interface") 51 51 #endif 52 52 ); … … 58 58 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("predict", IN,SOUTH, "predict", _param->_nb_inst_predict);60 ALLOC1_INTERFACE_BEGIN("predict", IN,SOUTH, _("predict"), _param->_nb_inst_predict); 61 61 62 62 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 72 72 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 73 73 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 74 75 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 74 76 } 75 77 76 78 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 79 { 78 ALLOC1_INTERFACE ("decod", IN,SOUTH, "decod", _param->_nb_inst_decod);80 ALLOC1_INTERFACE_BEGIN("decod", IN,SOUTH, _("decod"), _param->_nb_inst_decod); 79 81 80 82 ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); … … 93 95 ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 94 96 ALLOC1_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); 97 98 ALLOC1_INTERFACE_END(_param->_nb_inst_decod); 95 99 } 96 100 97 101 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 98 102 { 99 ALLOC1_INTERFACE ("branch_complete", IN,SOUTH, "branch_complete", _param->_nb_inst_branch_complete);103 ALLOC1_INTERFACE_BEGIN("branch_complete", IN,SOUTH, _("branch_complete"), _param->_nb_inst_branch_complete); 100 104 101 105 ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL ,VAL); … … 109 113 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); 110 114 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); 115 116 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); 111 117 } 112 118 113 119 // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 120 { 115 ALLOC1_INTERFACE ("branch_event", IN,SOUTH, "branch_event", _param->_nb_context);121 ALLOC1_INTERFACE_BEGIN("branch_event", IN,SOUTH, _("branch_event"), _param->_nb_context); 116 122 117 123 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); … … 123 129 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); 124 130 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); 131 132 ALLOC1_INTERFACE_END(_param->_nb_context); 125 133 } 126 134 127 135 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 128 136 { 129 ALLOC1_INTERFACE ("update",OUT,SOUTH, "update", _param->_nb_inst_update);137 ALLOC1_INTERFACE_BEGIN("update",OUT,SOUTH, "update", _param->_nb_inst_update); 130 138 131 139 ALLOC1_VALACK_OUT(out_UPDATE_VAL ,VAL); … … 134 142 ALLOC1_SIGNAL_OUT(out_UPDATE_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 135 143 ALLOC1_SIGNAL_OUT(out_UPDATE_DIRECTION_GOOD ,"direction_good" ,Tcontrol_t ,1); 144 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t ,1); 136 145 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); 137 146 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); … … 145 154 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 146 155 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 147 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); 156 157 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 148 158 } 149 159 150 160 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 151 161 { 152 ALLOC1_INTERFACE ("event", IN,SOUTH,"event", _param->_nb_context);162 ALLOC1_INTERFACE_BEGIN("event", IN,SOUTH,_("event"), _param->_nb_context); 153 163 154 164 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); … … 156 166 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 157 167 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); 168 169 ALLOC1_INTERFACE_END(_param->_nb_context); 158 170 } 159 171 160 172 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 161 173 { 162 ALLOC1_INTERFACE("depth",OUT,SOUTH, "depth", _param->_nb_context); 174 ALLOC1_INTERFACE_BEGIN("depth",OUT,SOUTH, _("depth"), _param->_nb_context); 175 163 176 ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"VAL" ,Tcontrol_t,1); 164 177 ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t ,_param->_size_depth); … … 166 179 ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth); 167 180 ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"FULL" ,Tcontrol_t,1); 181 182 ALLOC1_INTERFACE_END(_param->_nb_context); 168 183 } 169 184 … … 209 224 ALLOC1(reg_EVENT_VAL ,bool ,_param->_nb_context); 210 225 ALLOC1(reg_EVENT_UPT_PTR ,uint32_t ,_param->_nb_context); 226 ALLOC1(reg_EVENT_UPT_FULL ,bool ,_param->_nb_context); 211 227 212 228 ALLOC1(reg_EVENT_STATE ,event_state_t ,_param->_nb_context); 213 ALLOC1(reg_EVENT_ SOURCE ,event_source_t,_param->_nb_context);229 ALLOC1(reg_EVENT_IS_BRANCH ,bool ,_param->_nb_context); 214 230 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 215 231 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r111 r112 29 29 delete in_NRESET; 30 30 31 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 delete [] in_PREDICT_VAL ; 33 delete [] out_PREDICT_ACK ; 34 if (_param->_have_port_context_id) 35 delete [] in_PREDICT_CONTEXT_ID ; 36 delete [] in_PREDICT_BTB_ADDRESS_SRC ; 37 delete [] in_PREDICT_BTB_ADDRESS_DEST ; 38 delete [] in_PREDICT_BTB_CONDITION ; 39 delete [] in_PREDICT_BTB_LAST_TAKE ; 40 delete [] in_PREDICT_BTB_IS_ACCURATE ; 41 if (_param->_have_port_history) 42 delete [] in_PREDICT_DIR_HISTORY ; 43 delete [] in_PREDICT_RAS_ADDRESS ; 44 delete [] in_PREDICT_RAS_INDEX ; 45 if (_param->_have_port_depth) 46 delete [] out_PREDICT_UPDATE_PREDICTION_ID; 47 48 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 delete [] in_DECOD_VAL ; 50 delete [] out_DECOD_ACK ; 51 if (_param->_have_port_context_id) 52 delete [] in_DECOD_CONTEXT_ID ; 53 delete [] in_DECOD_BTB_ADDRESS_SRC ; 54 delete [] in_DECOD_BTB_ADDRESS_DEST ; 55 delete [] in_DECOD_BTB_CONDITION ; 56 delete [] in_DECOD_BTB_LAST_TAKE ; 57 delete [] in_DECOD_RAS_ADDRESS ; 58 delete [] in_DECOD_RAS_INDEX ; 59 delete [] in_DECOD_MISS_IFETCH ; 60 delete [] in_DECOD_MISS_DECOD ; 61 if (_param->_have_port_depth) 62 delete [] in_DECOD_UPDATE_PREDICTION_ID ; 63 // if (_param->_have_port_depth) 64 // delete [] out_DECOD_DEPTH ; 65 delete [] in_DECOD_IS_ACCURATE ; 66 delete [] out_DECOD_CAN_CONTINUE ; 67 68 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 69 delete [] in_BRANCH_COMPLETE_VAL ; 70 delete [] out_BRANCH_COMPLETE_ACK ; 71 if (_param->_have_port_context_id) 72 delete [] in_BRANCH_COMPLETE_CONTEXT_ID ; 73 if (_param->_have_port_depth) 74 delete [] in_BRANCH_COMPLETE_DEPTH ; 75 delete [] in_BRANCH_COMPLETE_ADDRESS ; 76 delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; 77 delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; 78 // delete [] out_BRANCH_COMPLETE_TAKE ; 79 // delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ; 80 // delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ; 31 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); 33 DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); 34 DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); 35 DELETE1_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID,_param->_nb_inst_predict,_param->_size_depth); 36 DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_size_instruction_address); 37 DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_size_instruction_address); 38 DELETE1_SIGNAL( in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict,_param->_size_branch_condition); 39 DELETE1_SIGNAL( in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict,1); 40 DELETE1_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict,1); 41 DELETE1_SIGNAL( in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict,_param->_size_history); 42 DELETE1_SIGNAL( in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); 43 DELETE1_SIGNAL( in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict,_param->_max_size_ras_index); 44 45 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 46 DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); 47 DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); 48 DELETE1_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id); 49 DELETE1_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); 50 DELETE1_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); 51 DELETE1_SIGNAL( in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); 52 DELETE1_SIGNAL( in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod,1); 53 DELETE1_SIGNAL( in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address); 54 DELETE1_SIGNAL( in_DECOD_RAS_INDEX ,_param->_nb_inst_decod,_param->_max_size_ras_index); 55 DELETE1_SIGNAL( in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod,1); 56 DELETE1_SIGNAL( in_DECOD_MISS_DECOD ,_param->_nb_inst_decod,1); 57 DELETE1_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_depth); 58 // DELETE1_SIGNAL(out_DECOD_DEPTH ,_param->_nb_inst_decod,_param->_size_depth); 59 DELETE1_SIGNAL( in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod,1); 60 DELETE1_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod,1); 61 62 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 63 DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); 64 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); 65 DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id); 66 DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); 67 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 68 DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); 69 DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); 70 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); 71 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 72 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 81 73 82 74 // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 90 82 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 91 83 92 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 93 delete [] out_UPDATE_VAL ; 94 delete [] in_UPDATE_ACK ; 95 if (_param->_have_port_context_id) 96 delete [] out_UPDATE_CONTEXT_ID ; 97 delete [] out_UPDATE_MISS_PREDICTION ; 98 delete [] out_UPDATE_DIRECTION_GOOD ; 99 delete [] out_UPDATE_BTB_VAL ; 100 delete [] out_UPDATE_BTB_ADDRESS_SRC ; 101 delete [] out_UPDATE_BTB_ADDRESS_DEST ; 102 delete [] out_UPDATE_BTB_CONDITION ; 103 delete [] out_UPDATE_DIR_VAL ; 104 if (_param->_have_port_history) 105 delete [] out_UPDATE_DIR_HISTORY ; 106 delete [] out_UPDATE_RAS_VAL ; 107 delete [] out_UPDATE_RAS_FLUSH ; 108 delete [] out_UPDATE_RAS_PUSH ; 109 delete [] out_UPDATE_RAS_ADDRESS ; 110 delete [] out_UPDATE_RAS_INDEX ; 111 delete [] out_UPDATE_RAS_PREDICTION_IFETCH; 84 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 85 DELETE1_SIGNAL(out_UPDATE_VAL ,_param->_nb_inst_update,1); 86 DELETE1_SIGNAL( in_UPDATE_ACK ,_param->_nb_inst_update,1); 87 DELETE1_SIGNAL(out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); 88 DELETE1_SIGNAL(out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update,1); 89 DELETE1_SIGNAL(out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update,1); 90 DELETE1_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update,1); 91 DELETE1_SIGNAL(out_UPDATE_BTB_VAL ,_param->_nb_inst_update,1); 92 DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); 93 DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update,_param->_size_instruction_address); 94 DELETE1_SIGNAL(out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update,_param->_size_branch_condition); 95 DELETE1_SIGNAL(out_UPDATE_DIR_VAL ,_param->_nb_inst_update,1); 96 DELETE1_SIGNAL(out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update,_param->_size_history); 97 DELETE1_SIGNAL(out_UPDATE_RAS_VAL ,_param->_nb_inst_update,1); 98 DELETE1_SIGNAL(out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update,1); 99 DELETE1_SIGNAL(out_UPDATE_RAS_PUSH ,_param->_nb_inst_update,1); 100 DELETE1_SIGNAL(out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); 101 DELETE1_SIGNAL(out_UPDATE_RAS_INDEX ,_param->_nb_inst_update,_param->_max_size_ras_index); 112 102 113 103 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 162 152 DELETE1(reg_EVENT_VAL ,_param->_nb_context); 163 153 DELETE1(reg_EVENT_UPT_PTR ,_param->_nb_context); 154 DELETE1(reg_EVENT_UPT_FULL ,_param->_nb_context); 164 155 165 156 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 166 DELETE1(reg_EVENT_ SOURCE,_param->_nb_context);157 DELETE1(reg_EVENT_IS_BRANCH ,_param->_nb_context); 167 158 DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); 168 159 DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r111 r112 98 98 Tcontrol_t miss_prediction ; 99 99 Tcontrol_t direction_good ; 100 Tcontrol_t prediction_ifetch ; 100 101 Tcontrol_t btb_val ; 101 102 Taddress_t btb_address_src ; … … 109 110 Taddress_t ras_address ; 110 111 Tptr_t ras_index ; 111 Tcontrol_t ras_prediction_ifetch;112 112 113 113 // Test if update fetch prediction table need update port … … 133 133 miss_prediction = 1; 134 134 // direction_good = ; 135 prediction_ifetch = 1; 135 136 btb_val = 0; // don't update btb (is update by the event branch) 136 // btb_address_src = ;137 // btb_address_dest = ;138 // btb_condition = ;139 dir_val = 0; // don't update btb (is update by the event branch (if conditionnal branch))140 // dir_history =;137 // btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; 138 // btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 139 // btb_condition = condition; 140 dir_val = update_ras(condition); 141 dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history; 141 142 // repop/ repush data -> don't corrupt ras 142 143 ras_val = update_ras(condition); … … 145 146 ras_address = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras; 146 147 ras_index = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._index_ras; 147 ras_prediction_ifetch = 1;148 148 149 149 internal_UPDATE_FROM_UFPT [i] = true; … … 200 200 miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); 201 201 direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; 202 prediction_ifetch = ifetch; 202 203 btb_val = state_is_ok_ko and update_btb(condition); 203 204 btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; 204 205 btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 205 206 btb_condition = condition; 206 dir_val = state_is_ok_ko and update_dir(condition) and ifetch; // if not ifetch, then static prediction 207 dir_val = // state_is_ok_ko and 208 update_dir(condition); // if not ifetch, then static prediction 207 209 dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; 208 210 ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras … … 213 215 ras_address = (ras_flush)?(reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src+2):reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; 214 216 ras_index = reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras; 215 ras_prediction_ifetch = ifetch;216 217 217 218 internal_UPDATE_FROM_UFPT [i] = false; … … 257 258 PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],miss_prediction ); 258 259 PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],direction_good ); 260 PORT_WRITE(out_UPDATE_PREDICTION_IFETCH [i],prediction_ifetch ); 259 261 PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val ); 260 262 PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],btb_address_src ); … … 269 271 PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],ras_address ); 270 272 PORT_WRITE(out_UPDATE_RAS_INDEX [i],ras_index ); 271 PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ras_prediction_ifetch);272 273 } 273 274 } … … 290 291 } 291 292 } 293 else 294 { 295 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 296 { 297 internal_UPDATE_VAL [i] = 0; 298 internal_UPDATE_VAL_WITHOUT_ACK [i] = 0; 299 } 300 for (uint32_t i=0; i<_param->_nb_context; i++) 301 { 302 internal_BRANCH_EVENT_VAL [i] = 0; 303 } 304 } 305 292 306 293 307 log_end(Update_Prediction_Table,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r111 r112 53 53 reg_EVENT_VAL [i] = false; 54 54 reg_EVENT_STATE [i] = EVENT_STATE_OK; 55 reg_EVENT_IS_BRANCH [i] = true; 55 56 } 56 57 } … … 100 101 // Test if state is end 101 102 // if (end_ok or end_ko) 103 104 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end); 105 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",reg_UPT_BOTTOM [i]); 106 102 107 if (end) 103 108 { … … 108 113 branchement_log_file [num_thread] 109 114 << std::hex 110 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "111 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "115 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " " 116 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " " 112 117 << std::dec 113 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " " 118 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - " 119 << "[" << sc_simulation_time() << "] " << " " 120 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " " 121 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " " 122 << "(" << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition << ")" 114 123 << std::endl; 115 124 } … … 128 137 // if (bottom = reg_UPT_UPDATE [i]) 129 138 // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; 130 131 if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) 139 }// @@@ 140 141 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]); 142 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]); 143 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]); 144 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL[i]); 145 146 if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) 147 { 148 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); 149 150 if ((reg_EVENT_IS_BRANCH [i] == false) and (reg_EVENT_UPT_FULL [i] == false)) 151 reg_EVENT_STATE[i] = EVENT_STATE_OK; 152 153 if ((reg_EVENT_IS_BRANCH [i] == true) or (reg_EVENT_UPT_FULL [i] == false)) 132 154 { 133 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); 134 135 reg_EVENT_VAL [i] = false; 136 reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; 137 reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; 138 139 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 140 reg_UPT_EMPTY [i] = false; 141 142 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 143 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 144 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 145 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 155 reg_EVENT_VAL [i] = false; 156 // reg_EVENT_IS_BRANCH [i] = true; 157 reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; 158 reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; 159 160 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 161 reg_UPT_EMPTY [i] = false; 146 162 } 147 163 164 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 165 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 166 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 167 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 168 148 169 } 170 171 if (end) 172 reg_EVENT_UPT_FULL [i] = false; 149 173 } 150 174 } … … 245 269 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context); 246 270 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 271 // reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT; 247 272 } 248 273 else … … 251 276 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; 252 277 } 253 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UFPT;254 278 255 279 // Flush UPFT 256 280 flush_UFPT [context] = true; 257 281 282 reg_EVENT_IS_BRANCH [context] = true; 258 283 reg_EVENT_DEPTH [context] = upt_ptr_write; 259 284 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State … … 357 382 (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context])) 358 383 { 359 Tdepth_t depth = internal_UPDATE_DEPTH 384 Tdepth_t depth = internal_UPDATE_DEPTH [i]; 360 385 361 386 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); … … 369 394 // if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 370 395 if ((--reg_UFPT_NB_UPDATE [context])==0) 371 switch (reg_EVENT_STATE [context]) 372 { 373 case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; 374 // impossible to have an update on ufpt and reg_upt_update>reg_upt_top 375 case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; 376 case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; 377 case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; 378 default : break; 379 } 396 { 397 switch (reg_EVENT_STATE [context]) 398 { 399 case EVENT_STATE_MISS_FLUSH_UFPT : 400 { 401 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 402 // reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT; 403 404 break; 405 } 406 // impossible to have an update on ufpt and reg_upt_update>reg_upt_top 407 case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; 408 case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; 409 case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; 410 default : break; 411 } 412 } 380 413 381 414 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); … … 405 438 { 406 439 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); 407 440 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]); 441 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 442 408 443 // Change state 409 444 #ifdef DEBUG_TEST … … 430 465 431 466 if (ok or ko) 432 reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; 467 { 468 reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; 469 reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko; 470 } 433 471 434 472 // Have an update, test the state to transiste to the good state … … 444 482 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 445 483 446 reg_EVENT_VAL [context] = true; 447 reg_EVENT_UPT_PTR [context] = depth; 484 reg_EVENT_VAL [context] = true; 485 reg_EVENT_UPT_PTR [context] = depth; 486 // reg_EVENT_UPT_FULL [context] = 0; 487 // reg_EVENT_UPT_FULL [i] = (not reg_UPT_EMPTY [i] and (bottom == reg_UPT_TOP [i])); 488 448 489 449 490 #ifdef STATISTICS … … 473 514 // Update pointer 474 515 // * if update RAS : update pointer is decreaste until it equal at top pointer 516 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]); 517 475 518 if (internal_UPDATE_RAS [i]) 476 519 { 477 520 // if end_event, restart too bottom, else decrease pointer 478 521 bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); 522 523 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event); 524 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]); 479 525 480 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);481 526 if (end_event) 482 527 { 483 // reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 528 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); 529 // reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 484 530 485 531 if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT) … … 488 534 } 489 535 else 490 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 536 { 537 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 538 // reg_EVENT_SOURCE[context] = EVENT_SOURCE_UPT; 539 } 491 540 } 492 541 else … … 497 546 else 498 547 { 548 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update"); 549 499 550 // increase pointer 500 551 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; … … 502 553 503 554 // Free the branch with no accurate ? 504 if ( 555 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko) 505 556 reg_IS_ACCURATE [context] = true; 557 558 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]); 559 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 506 560 } 507 561 } … … 513 567 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 514 568 } 515 516 569 517 570 // =================================================================== … … 533 586 534 587 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 535 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 537 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 588 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 589 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 590 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 591 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 538 592 539 593 if (miss) … … 546 600 event_state_t event_state = reg_EVENT_STATE [context]; 547 601 upt_state_t event_top = reg_UPDATE_PREDICTION_TABLE [context][top]._state; 602 603 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_top : %s",toString(event_top).c_str()); 604 548 605 bool previous_ufpt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 606 (event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or … … 551 608 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT )); 552 609 553 bool previous_upt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 554 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 555 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 556 (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or 557 (event_top == UPDATE_PREDICTION_STATE_END_KO ) or 558 (event_top == UPDATE_PREDICTION_STATE_KO ) 559 // (event_state == EVENT_STATE_WAIT_END_EVENT ) or 560 // ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and 561 // (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) 562 ); 610 bool previous_upt_event = (false 611 or (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) 612 or (event_state == EVENT_STATE_MISS_FLUSH_UPT ) 613 or (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) 614 or (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) 615 or (event_top == UPDATE_PREDICTION_STATE_END_KO ) 616 or (event_top == UPDATE_PREDICTION_STATE_KO ) 617 // or (event_state == EVENT_STATE_WAIT_END_EVENT ) 618 // or ((event_state == EVENT_STATE_UPDATE_CONTEXT ) 619 // and (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) 620 ); 563 621 // bool update_ras = (new_update != depth); 564 622 … … 568 626 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event); 569 627 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event); 570 628 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]); 629 571 630 // Have a miss !!! 572 631 // Flush UPFT 573 flush_UFPT [context] = not previous_ufpt_event;632 flush_UFPT [context] |= not previous_ufpt_event; 574 633 575 634 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) … … 587 646 reg_UPT_TOP [context] = depth; 588 647 // reg_UPT_TOP_EVENT [context] = top; 589 648 590 649 if (not previous_upt_event) 591 650 { … … 604 663 // Have already update predictor 605 664 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END; 665 reg_UPT_UPDATE [context] = new_update; 606 666 break; 607 667 } … … 649 709 } 650 710 } 651 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;711 // reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT; 652 712 653 713 // else no update 654 714 715 reg_EVENT_IS_BRANCH [context] = true; 655 716 reg_EVENT_DEPTH [context] = depth; 656 717 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State … … 675 736 } 676 737 738 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 739 677 740 // In all case : update good_take 678 741 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; … … 686 749 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; 687 750 } 751 688 752 689 753 // =================================================================== … … 779 843 780 844 // Flush UPT 781 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; 782 uint32_t top = reg_UPT_TOP [i]; 783 uint32_t bottom = reg_UPT_BOTTOM [i]; 784 uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 785 // bool empty = reg_UPT_EMPTY [i]; 786 845 uint32_t bottom = reg_UPT_BOTTOM [i]; 846 847 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom); 848 849 // event_state_t event_state = reg_EVENT_STATE [i]; 850 // bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 851 // (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 852 // (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 853 // (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 854 855 bool find = false; // have slot to update ??? 856 Tdepth_t top = bottom; 857 Tdepth_t update = bottom; 858 bool empty = reg_UPT_EMPTY [i]; 859 860 // flush all slot, because this event is in head of rob 861 for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) 862 { 863 Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i]; 864 865 if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and 866 (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)) 867 { 868 find = true; // find a not empty slot 869 reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT; 870 reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false; 871 update = x; 872 } 873 874 if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY) 875 top = x+1; 876 } 877 878 top = top%_param->_size_upt_queue[i]; 879 880 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 787 881 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 788 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);789 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);790 791 event_state_t event_state = reg_EVENT_STATE [i];792 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or793 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or794 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or795 (event_state == EVENT_STATE_EVENT_FLUSH_UPT));796 797 bool find = false; // have slot to update ???798 Tdepth_t depth_new = depth;799 800 // flush all slot after the event801 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];802 j!=top;803 j=(j+1)%_param->_size_upt_queue[i])804 if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and805 (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY))806 {807 find = true;808 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;809 reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false;810 }811 else812 if (not find) // while state == end or empty813 depth_new ++;814 815 if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and816 (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY))817 {818 find = true;819 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;820 reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false;821 822 }823 else824 // while state == end or empty825 depth = (depth_new+1)%_param->_size_upt_queue[i];826 827 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);828 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new);829 882 830 883 // Test if have update slot 831 884 if (find) 832 885 { 833 // // flush all slot after the event834 // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];835 // j!=top;836 // j=(j+1)%_param->_size_upt_queue[i])837 // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;838 839 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;840 841 // reg_UPT_BOTTOM [i];842 886 // TODO : special case : event is an exception on branch, also depth is not valid 843 reg_UPT_TOP [i] = depth; // depth is again valid887 reg_UPT_TOP [i] = top; // depth is again valid 844 888 reg_UPT_TOP_EVENT [i] = top; 845 889 … … 847 891 reg_UPT_EMPTY [i] = true; 848 892 } 849 850 bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 851 bool update_ras = find and ((top != depth) or full); 852 853 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 854 855 if (not previous_update_ras and update_ras) 856 reg_UPT_UPDATE [i] = new_update; 893 reg_UPT_UPDATE [i] = update; 857 894 858 895 // new state : … … 862 899 // * ok : nothing 863 900 // * ko : flush upt 864 reg_EVENT_VAL [i] = true; 865 reg_EVENT_UPT_PTR [i] = depth; 866 901 reg_EVENT_VAL [i] = find; 902 reg_EVENT_IS_BRANCH [i] = false; 903 reg_EVENT_UPT_PTR [i] = top; 904 reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i])); 905 reg_EVENT_DEPTH [i] = top; 906 // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 907 // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 908 // reg_EVENT_ADDRESS_DEST [i] = good_addr; 909 910 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); 911 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 912 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 913 914 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]); 915 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]); 916 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]); 867 917 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 868 // if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 918 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); 919 869 920 if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or 870 921 (reg_UFPT_NB_UPDATE [i] > 0)) 871 922 { 872 if ( update_ras)923 if (find) 873 924 { 874 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT ( branch_complete - miss)",i);925 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (event - find)",i); 875 926 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; 876 927 } 877 928 else 878 929 { 879 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); 930 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (event - not find)",i); 931 // reg_EVENT_VAL [i] = false; 932 880 933 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; 881 934 } … … 883 936 else 884 937 { 885 // if (not previous_update_ras) 886 if (update_ras) 938 if (find) 887 939 { 888 940 // have ras prediction ? 889 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT ( branch_complete - miss)",i);941 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - find)",i); 890 942 891 943 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; … … 894 946 { 895 947 // special case : nothing 896 reg_EVENT_VAL [i] = false; 948 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - not find)",i); 949 950 // reg_EVENT_VAL [i] = false; 897 951 898 952 reg_EVENT_STATE [i] = EVENT_STATE_OK; … … 902 956 // else no update 903 957 904 reg_EVENT_DEPTH [i] = depth; 905 // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 906 // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 907 // reg_EVENT_ADDRESS_DEST [i] = good_addr; 958 // Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; 959 // uint32_t top = reg_UPT_TOP [i]; 960 // uint32_t bottom = reg_UPT_BOTTOM [i]; 961 // uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 962 // // bool empty = reg_UPT_EMPTY [i]; 963 964 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 965 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 966 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 967 968 // event_state_t event_state = reg_EVENT_STATE [i]; 969 // bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 970 // (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 971 // (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 972 // (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 973 974 // bool find = false; // have slot to update ??? 975 // Tdepth_t depth_new = depth; 976 977 // // flush all slot, because this event is in head of rob 978 // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 979 // //uint32_t j=bottom; 980 // j!=top; 981 // j=(j+1)%_param->_size_upt_queue[i]) 982 // if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and 983 // (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) 984 // { 985 // find = true; 986 // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 987 // reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false; 988 // } 989 // else 990 // if (not find) // while state == end or empty 991 // depth_new ++; 992 993 // if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and 994 // (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) 995 // { 996 // find = true; 997 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 998 // reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false; 999 1000 // } 1001 // else 1002 // // while state == end or empty 1003 // depth = (depth_new+1)%_param->_size_upt_queue[i]; 1004 1005 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 1006 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new); 1007 1008 // // Test if have update slot 1009 // if (find) 1010 // { 1011 // // // flush all slot after the event 1012 // // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 1013 // // j!=top; 1014 // // j=(j+1)%_param->_size_upt_queue[i]) 1015 // // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 1016 1017 // // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 1018 1019 // // reg_UPT_BOTTOM [i]; 1020 // // TODO : special case : event is an exception on branch, also depth is not valid 1021 // reg_UPT_TOP [i] = depth; // depth is again valid 1022 // reg_UPT_TOP_EVENT [i] = top; 1023 1024 // if (bottom == reg_UPT_TOP [i]) 1025 // reg_UPT_EMPTY [i] = true; 1026 // } 1027 1028 // bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 1029 // bool update_ras = find and ((top != depth) or full); 1030 1031 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 1032 1033 // if (not previous_update_ras and update_ras) 1034 // reg_UPT_UPDATE [i] = new_update; 1035 1036 // // new state : 1037 // // * test if ufpt is empty 1038 // // * ok : flush upft and upt 1039 // // * ko : test if have previous flush upt 1040 // // * ok : nothing 1041 // // * ko : flush upt 1042 // reg_EVENT_VAL [i] = update_ras; 1043 // reg_EVENT_UPT_PTR [i] = depth; 1044 1045 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 1046 // // if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 1047 // if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or 1048 // (reg_UFPT_NB_UPDATE [i] > 0)) 1049 // { 1050 // if (update_ras) 1051 // { 1052 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i); 1053 // reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; 1054 // } 1055 // else 1056 // { 1057 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); 1058 // // reg_EVENT_VAL [i] = false; 1059 1060 // reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; 1061 // } 1062 // } 1063 // else 1064 // { 1065 // // if (not previous_update_ras) 1066 // if (update_ras) 1067 // { 1068 // // have ras prediction ? 1069 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i); 1070 1071 // reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; 1072 // } 1073 // else 1074 // { 1075 // // special case : nothing 1076 // // reg_EVENT_VAL [i] = false; 1077 1078 // reg_EVENT_STATE [i] = EVENT_STATE_OK; 1079 // } 1080 // } 1081 1082 // // else no update 1083 1084 // reg_EVENT_DEPTH [i] = depth; 1085 // // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 1086 // // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 1087 // // reg_EVENT_ADDRESS_DEST [i] = good_addr; 908 1088 909 1089 break; … … 994 1174 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]); 995 1175 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); 1176 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]); 996 1177 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 997 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ SOURCE : %s" ,toString(reg_EVENT_SOURCE[i]).c_str());1178 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]); 998 1179 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 999 1180 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
r111 r112 45 45 ,IN 46 46 ,SOUTH, 47 "Generalist interface"47 _("Generalist interface") 48 48 #endif 49 49 ); … … 56 56 { 57 57 { 58 ALLOC1_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context);58 ALLOC1_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context); 59 59 60 60 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 68 68 ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 69 69 ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 70 71 ALLOC1_INTERFACE_END(_param->_nb_context); 70 72 } 71 73 { 72 ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[it1]); 74 ALLOC2_INTERFACE_BEGIN("predict",IN,SOUTH,_("Interface with ifetch unit"),_param->_nb_context,_param->_nb_instruction[it1]); 75 73 76 _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[it1]); 77 78 ALLOC2_INTERFACE_END(_param->_nb_context,_param->_nb_instruction[it1]); 74 79 } 75 80 } … … 78 83 { 79 84 { 80 ALLOC2_INTERFACE ("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[it1]);85 ALLOC2_INTERFACE_BEGIN("decod",IN,SOUTH,_("Interface with decod unit"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 81 86 82 87 _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); … … 91 96 _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 92 97 _ALLOC2_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 98 99 100 ALLOC2_INTERFACE_END(_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); 93 101 } 94 102 } … … 96 104 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 97 105 { 98 ALLOC1_INTERFACE ("branch_complete", IN,SOUTH, "branch_complete", _param->_nb_inst_branch_complete);106 ALLOC1_INTERFACE_BEGIN("branch_complete", IN,SOUTH, _("branch_complete"), _param->_nb_inst_branch_complete); 99 107 100 108 ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL ,VAL); … … 108 116 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); 109 117 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); 118 119 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); 110 120 } 111 121 112 122 // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 123 { 114 ALLOC1_INTERFACE ("branch_event", IN,SOUTH, "branch_event", _param->_nb_context);124 ALLOC1_INTERFACE_BEGIN("branch_event", IN,SOUTH, _("branch_event"), _param->_nb_context); 115 125 116 126 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); … … 122 132 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); 123 133 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); 134 135 ALLOC1_INTERFACE_END(_param->_nb_context); 124 136 } 125 137 126 138 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 127 139 { 128 ALLOC1_INTERFACE ("depth",OUT,SOUTH,"Interface with depth",_param->_nb_context);140 ALLOC1_INTERFACE_BEGIN("depth",OUT,SOUTH,_("Interface with depth"),_param->_nb_context); 129 141 130 142 ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"val" ,Tcontrol_t,1); … … 133 145 ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth); 134 146 ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"full" ,Tcontrol_t,1); 147 148 ALLOC1_INTERFACE_END(_param->_nb_context); 135 149 } 136 150 137 151 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 152 { 139 ALLOC1_INTERFACE ("event", IN,SOUTH,"event", _param->_nb_context);153 ALLOC1_INTERFACE_BEGIN("event", IN,SOUTH,_("event"), _param->_nb_context); 140 154 141 155 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); … … 143 157 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 144 158 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); 159 160 ALLOC1_INTERFACE_END(_param->_nb_context); 145 161 } 146 162 … … 421 437 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_DIRECTION", 422 438 dest,"out_UPDATE_"+toString(i)+ "_DIRECTION_GOOD"); 423 439 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH", 440 dest,"out_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH"); 424 441 } 425 442 } … … 532 549 dest,"out_UPDATE_"+toString(i)+ "_MISS_PREDICTION" ); 533 550 COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH", 534 dest,"out_UPDATE_"+toString(i)+ "_RAS_PREDICTION_IFETCH");551 dest,"out_UPDATE_"+toString(i)+ "_PREDICTION_IFETCH"); 535 552 } 536 553 } … … 656 673 //in_UPDATE_UPT_RAS_FLUSH - component_map return_address_stack 657 674 //in_UPDATE_UPT_RAS_INDEX - component_map return_address_stack 658 //in_UPDATE_UPT_ RAS_PREDICTION_IFETCH - component_map return_address_stack675 //in_UPDATE_UPT_PREDICTION_IFETCH - component_map return_address_stack, direction 659 676 } 660 677
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