Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit
- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit
- Files:
-
- 15 edited
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SelfTest/config_mono_thread.cfg (modified) (1 diff)
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SelfTest/config_multi_thread.cfg (modified) (1 diff)
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SelfTest/src/main.cpp (modified) (4 diffs)
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SelfTest/src/test.cpp (modified) (14 diffs)
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include/Parameters.h (modified) (2 diffs)
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include/Stat_List_unit.h (modified) (3 diffs)
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include/Types.h (modified) (4 diffs)
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src/Parameters.cpp (modified) (2 diffs)
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src/Parameters_print.cpp (modified) (1 diff)
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src/Stat_List_unit.cpp (modified) (2 diffs)
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src/Stat_List_unit_allocation.cpp (modified) (5 diffs)
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src/Stat_List_unit_deallocation.cpp (modified) (2 diffs)
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src/Stat_List_unit_genMealy.cpp (modified) (1 diff)
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src/Stat_List_unit_genMoore.cpp (modified) (1 diff)
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src/Stat_List_unit_transition.cpp (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_mono_thread.cfg
r81 r112 8 8 1 4 *2 #_nb_reg_free 9 9 4 4 *2 #_nb_bank 10 2 2 +1 #_size_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/config_multi_thread.cfg
r81 r112 9 9 4 4 *2 #_nb_reg_free 10 10 4 8 *2 #_nb_bank 11 2 4 *2 #_size_counter -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp
r88 r112 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/include/test.h" 9 9 10 #define NB_PARAMS 810 #define NB_PARAMS 7 11 11 12 12 void usage (int argc, char * argv[]) … … 22 22 err (_(" * nb_reg_free (uint32_t)\n")); 23 23 err (_(" * nb_bank (uint32_t)\n")); 24 err (_(" * size_counter (uint32_t)\n"));25 24 26 25 exit (1); … … 55 54 uint32_t _nb_reg_free = atoi(argv[x++]); 56 55 uint32_t _nb_bank = atoi(argv[x++]); 57 uint32_t _size_counter = atoi(argv[x++]);58 56 59 57 try … … 68 66 _nb_reg_free , 69 67 _nb_bank , 70 _size_counter ,71 68 true //is_toplevel 72 69 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp
r88 r112 75 75 ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); 76 76 ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); 77 ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE ," in_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire); 77 78 ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); 78 79 ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); … … 121 122 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_VAL ,_param->_nb_inst_retire); 122 123 INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_RETIRE_ACK ,_param->_nb_inst_retire); 124 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE ,_param->_nb_inst_retire); 123 125 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); 124 126 INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); … … 234 236 TEST(bool, true,((gpr_status[reg]._is_free == 0) and 235 237 (gpr_status[reg]._is_link == 0) and 236 (gpr_status[reg]._is_valid == 1) and 237 (gpr_status[reg]._counter == 0))); 238 (gpr_status[reg]._is_valid == 1)// and 239 // (gpr_status[reg]._counter == 0) 240 )); 238 241 239 242 gpr_status[reg]._is_free = 1; … … 254 257 TEST(bool, true,((spr_status[reg]._is_free == 0) and 255 258 (spr_status[reg]._is_link == 0) and 256 (spr_status[reg]._is_valid == 1) and 257 (spr_status[reg]._counter == 0))); 259 (spr_status[reg]._is_valid == 1)// and 260 // (spr_status[reg]._counter == 0) 261 )); 258 262 259 263 spr_status[reg]._is_free = 1; … … 301 305 Tspecial_address_t re = (it_spr != free_list_spr.end())?*it_spr:0; 302 306 303 Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link) and (gpr_status_insert[ra]._counter < _param->_max_reader);304 Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link) and (gpr_status_insert[rb]._counter < _param->_max_reader);305 Tcontrol_t read_rc = (spr_status_insert[rc]._is_link) and (spr_status_insert[rc]._counter < _param->_max_reader);307 Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link); // and (gpr_status_insert[ra]._counter < _param->_max_reader); 308 Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link); // and (gpr_status_insert[rb]._counter < _param->_max_reader); 309 Tcontrol_t read_rc = (spr_status_insert[rc]._is_link); // and (spr_status_insert[rc]._counter < _param->_max_reader); 306 310 Tcontrol_t write_rd = (it_gpr != free_list_gpr.end()); 307 311 Tcontrol_t write_re = (it_spr != free_list_spr.end()); … … 341 345 Tspecial_address_t re_new = (rand()%(_param->_nb_special_register )) ; 342 346 343 Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link) and (gpr_status_retire[ra]._counter > 0);344 Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link) and (gpr_status_retire[rb]._counter > 0);345 Tcontrol_t read_rc = (spr_status_retire[rc]._is_link) and (spr_status_retire[rc]._counter > 0);347 Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link); // and (gpr_status_retire[ra]._counter > 0); 348 Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link); // and (gpr_status_retire[rb]._counter > 0); 349 Tcontrol_t read_rc = (spr_status_retire[rc]._is_link); // and (spr_status_retire[rc]._counter > 0); 346 350 Tcontrol_t write_rd = ( (gpr_status_retire[rd_old]._is_link ) and 347 351 (gpr_status_retire[rd_old]._is_valid) and … … 355 359 in_RETIRE_VAL [i]->write((rand()%100) < percent_transaction_retire); 356 360 in_RETIRE_READ_RA [i]->write(read_ra ); 357 in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); 361 in_RETIRE_RESTORE [i]->write(0); 362 in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); 358 363 in_RETIRE_READ_RB [i]->write(read_rb ); 359 364 in_RETIRE_NUM_REG_RB_PHY [i]->write(rb); … … 502 507 if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read()) 503 508 { 509 Tcontrol_t restore = in_RETIRE_RESTORE [i]->read(); 504 510 Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); 505 511 Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); … … 518 524 519 525 LABEL("RETIRE [%d] - Accepted",i); 526 LABEL(" * restore : %d",restore); 520 527 LABEL(" * read_ra : %d",read_ra ); 521 528 LABEL(" * reg_ra : %d",ra ); … … 575 582 if (write_rd) 576 583 { 577 if (restore _rd_old)584 if (restore) 578 585 { 579 gpr_status[rd_old]._is_link = 1; 580 gpr_status[rd_new]._is_link = 0; 581 gpr_status[rd_new]._is_valid = 1; 586 if (restore_rd_old) 587 { 588 gpr_status[rd_old]._is_link = 1; 589 gpr_status[rd_new]._is_link = 0; 590 gpr_status[rd_new]._is_valid = 1; 591 } 592 else 593 { 594 gpr_status[rd_old]._is_link = 0; 595 gpr_status[rd_new]._is_link = 0; 596 gpr_status[rd_new]._is_valid = 1; 597 } 582 598 } 583 599 else … … 586 602 gpr_status[rd_new]._is_valid = 1; 587 603 } 604 588 605 } 589 606 if (write_re) … … 619 636 TEST(bool, true,((gpr_status[reg]._is_free == 0) and 620 637 (gpr_status[reg]._is_link == 0) and 621 (gpr_status[reg]._is_valid == 1) and 622 (gpr_status[reg]._counter == 0))); 638 (gpr_status[reg]._is_valid == 1)// and 639 // (gpr_status[reg]._counter == 0) 640 )); 623 641 624 642 gpr_status[reg]._is_free = 1; … … 639 657 TEST(bool, true,((spr_status[reg]._is_free == 0) and 640 658 (spr_status[reg]._is_link == 0) and 641 (spr_status[reg]._is_valid == 1) and 642 (spr_status[reg]._counter == 0))); 659 (spr_status[reg]._is_valid == 1)// and 660 // (spr_status[reg]._counter == 0) 661 )); 643 662 644 663 spr_status[reg]._is_free = 1; … … 678 697 delete [] in_RETIRE_VAL ; 679 698 delete [] out_RETIRE_ACK ; 699 delete [] in_RETIRE_RESTORE ; 680 700 delete [] in_RETIRE_READ_RA ; 681 701 delete [] in_RETIRE_NUM_REG_RA_PHY ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h
r88 r112 34 34 public : uint32_t _nb_reg_free ; 35 35 public : uint32_t _nb_bank ; 36 36 //public : uint32_t _size_counter ; 37 37 38 38 //public : uint32_t _size_general_register ; 39 39 //public : uint32_t _size_special_register ; 40 40 41 41 //public : uint32_t _max_reader ; 42 42 public : uint32_t _nb_gpr_use_init ; 43 43 public : uint32_t _nb_spr_use_init ; … … 63 63 uint32_t nb_reg_free , 64 64 uint32_t nb_bank , 65 uint32_t size_counter ,65 // uint32_t size_counter , 66 66 bool is_toplevel=false 67 67 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h
r88 r112 79 79 public : SC_IN (Tcontrol_t ) ** in_RETIRE_VAL ;//[nb_inst_retire] 80 80 public : SC_OUT(Tcontrol_t ) ** out_RETIRE_ACK ;//[nb_inst_retire] 81 public : SC_IN (Tcontrol_t ) ** in_RETIRE_RESTORE ;//[nb_inst_retire] 81 82 public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RA ;//[nb_inst_retire] 82 83 public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] … … 110 111 private : stat_list_entry_t ** spr_stat_list; //[nb_bank][nb_general_register_by_bank] 111 112 113 private : uint32_t reg_GPR_PTR_FREE; 114 private : uint32_t reg_SPR_PTR_FREE; 115 112 116 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 private : uint32_t internal_GPR_PTR_FREE;114 private : uint32_t internal_SPR_PTR_FREE;115 116 117 private : Tcontrol_t * internal_INSERT_ACK ;//[nb_inst_insert] 117 118 private : Tcontrol_t * internal_RETIRE_ACK ;//[nb_inst_retire] … … 154 155 public : void transition (void); 155 156 public : void genMoore (void); 156 157 //public : void genMealy (void); 157 158 #endif 158 159 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h
r88 r112 25 25 public : bool _is_free ; // set = is present in free list 26 26 public : bool _is_link ; // set = is present in rat 27 28 27 //public : bool _is_valid; // set = an instruction have write in this register 28 //public : uint32_t _counter ; // number of register that must read this register 29 29 30 30 public : stat_list_entry_t (void) {}; … … 35 35 _is_free = 0; 36 36 _is_link = is_link; 37 38 37 // _is_valid = 1; 38 // _counter = 0; 39 39 } 40 40 41 public : void insert_read (void) 42 { 43 _counter ++; 44 } 41 // public : void insert_read (void) 42 // { 43 // _counter ++; 44 // } 45 45 46 public : void insert_write (void) 46 47 { 47 48 _is_free = 0; 48 49 _is_link = 1; 49 50 // _is_valid = 0; 50 51 } 51 52 52 public : void retire_read (void) 53 // public : void retire_read (void) 54 // { 55 // _counter --; 56 // } 57 58 public : void retire_write_old (bool restore, bool restore_old) 53 59 { 54 _counter --; 60 // restore restore_old is_link 61 // 0 x 0 - normal case : unallocate 62 // 1 0 0 - event and previous update 63 // 1 1 1 - event and first update 64 65 _is_link = restore and restore_old; 55 66 } 56 67 57 public : void retire_write_ old (bool restore_old)68 public : void retire_write_new (bool restore, bool restore_old) 58 69 { 59 if (not restore_old) 60 { 61 _is_link = 0; 62 } 63 // else nothing 64 } 70 // restore restore_old is_link 71 // 0 x 1 - normal case : allocate 72 // 1 x 0 - event, need restore oldest register 65 73 66 public : void retire_write_new (bool restore_old) 67 { 68 if (restore_old) 69 { 70 _is_link = 0; 71 } 74 if (restore) 75 _is_link = 0; 72 76 73 77 // in all case 74 78 // _is_valid = 1; 75 79 } 76 80 … … 80 84 } 81 85 82 public : bool can_insert_read (uint32_t max_reader)83 {84 85 }86 // public : bool can_insert_read (uint32_t max_reader) 87 // { 88 // return ((_counter+1) < max_reader); 89 // } 86 90 87 91 public : bool can_free (void) 88 92 { 89 93 return ((_is_free == 0) and 90 (_is_link == 0) and 91 // (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset 92 (_counter == 0)); 94 (_is_link == 0) // and 95 // (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset 96 // (_counter == 0) 97 ); 93 98 } 94 99 … … 97 102 { 98 103 output << x._is_free << " " 99 << x._is_link << " " 100 << x._is_valid << " " 101 << x._counter; 104 << x._is_link // << " " 105 // << x._is_valid << " " 106 // << x._counter 107 ; 102 108 103 109 return output; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp
r88 r112 29 29 uint32_t nb_reg_free , 30 30 uint32_t nb_bank , 31 uint32_t size_counter ,31 // uint32_t size_counter , 32 32 bool is_toplevel) 33 33 { … … 42 42 _nb_reg_free = nb_reg_free ; 43 43 _nb_bank = nb_bank ; 44 44 // _size_counter = size_counter ; 45 45 46 46 // _max_reader = 1<<size_counter; 47 47 48 48 uint32_t nb_thread = 0; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters_print.cpp
r81 r112 35 35 xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); 36 36 xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); 37 xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end();37 // xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end(); 38 38 39 39 for (uint32_t i=0;i<_nb_front_end; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit.cpp
r88 r112 75 75 { 76 76 // Constant 77 for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 78 { 79 internal_INSERT_ACK[i] = 1; 80 PORT_WRITE(out_INSERT_ACK[i], internal_INSERT_ACK[i]); 81 } 77 82 for (uint32_t i=0; i<_param->_nb_inst_retire; i++) 78 83 { … … 101 106 # endif 102 107 103 log_printf(INFO,Stat_List_unit,FUNCTION,"Method - genMealy");108 // log_printf(INFO,Stat_List_unit,FUNCTION,"Method - genMealy"); 104 109 105 SC_METHOD (genMealy);106 dont_initialize ();107 sensitive << (*(in_CLOCK)).neg(); // need internal register108 for (uint32_t i=0; i<_param->_nb_inst_insert; i++)109 sensitive << (*(in_INSERT_READ_RA [i]))110 << (*(in_INSERT_NUM_REG_RA_PHY [i]))111 << (*(in_INSERT_READ_RB [i]))112 << (*(in_INSERT_NUM_REG_RB_PHY [i]))113 << (*(in_INSERT_READ_RC [i]))114 << (*(in_INSERT_NUM_REG_RC_PHY [i]));110 // SC_METHOD (genMealy); 111 // dont_initialize (); 112 // sensitive << (*(in_CLOCK)).neg(); // need internal register 113 // for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 114 // sensitive << (*(in_INSERT_READ_RA [i])) 115 // << (*(in_INSERT_NUM_REG_RA_PHY [i])) 116 // << (*(in_INSERT_READ_RB [i])) 117 // << (*(in_INSERT_NUM_REG_RB_PHY [i])) 118 // << (*(in_INSERT_READ_RC [i])) 119 // << (*(in_INSERT_NUM_REG_RC_PHY [i])); 115 120 116 # ifdef SYSTEMCASS_SPECIFIC117 // List dependency information121 // # ifdef SYSTEMCASS_SPECIFIC 122 // // List dependency information 118 123 119 for (uint32_t i=0; i<_param->_nb_inst_insert; i++)120 {121 (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RA [i]));122 (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RA_PHY [i]));123 (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RB [i]));124 (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RB_PHY [i]));125 (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RC [i]));126 (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RC_PHY [i]));127 }128 # endif124 // for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 125 // { 126 // (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RA [i])); 127 // (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RA_PHY [i])); 128 // (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RB [i])); 129 // (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RB_PHY [i])); 130 // (*(out_INSERT_ACK [i])) (*(in_INSERT_READ_RC [i])); 131 // (*(out_INSERT_ACK [i])) (*(in_INSERT_NUM_REG_RC_PHY [i])); 132 // } 133 // # endif 129 134 130 135 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp
r88 r112 49 49 ,IN 50 50 ,SOUTH, 51 "Generalist interface"51 _("Generalist interface") 52 52 #endif 53 53 ); … … 58 58 // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("insert",IN,SOUTH,"Insert a renaming result",_param->_nb_inst_insert);60 ALLOC1_INTERFACE_BEGIN("insert",IN,SOUTH,_("Insert a renaming result"),_param->_nb_inst_insert); 61 61 62 62 ALLOC1_VALACK_IN ( in_INSERT_VAL ,VAL); … … 72 72 ALLOC1_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 73 73 ALLOC1_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); 74 75 ALLOC1_INTERFACE_END(_param->_nb_inst_insert); 74 76 } 75 77 76 78 // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 79 { 78 ALLOC1_INTERFACE ("retire",IN,NORTH,"Retire a renaming result",_param->_nb_inst_retire);80 ALLOC1_INTERFACE_BEGIN("retire",IN,NORTH,_("Retire a renaming result"),_param->_nb_inst_retire); 79 81 80 82 ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); 81 83 ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); 84 ALLOC1_SIGNAL_IN ( in_RETIRE_RESTORE ,"restore" ,Tcontrol_t ,1 ); 82 85 ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); 83 86 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register); … … 94 97 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); 95 98 ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); 99 100 ALLOC1_INTERFACE_END(_param->_nb_inst_retire); 96 101 } 97 102 98 103 // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 99 104 { 100 ALLOC1_INTERFACE ("push_gpr",OUT,SOUTH,"Free a general register",_param->_nb_reg_free);105 ALLOC1_INTERFACE_BEGIN("push_gpr",OUT,SOUTH,_("Free a general register"),_param->_nb_reg_free); 101 106 102 107 ALLOC1_VALACK_OUT(out_PUSH_GPR_VAL ,VAL); 103 108 ALLOC1_VALACK_IN ( in_PUSH_GPR_ACK ,ACK); 104 109 ALLOC1_SIGNAL_OUT(out_PUSH_GPR_NUM_REG,"num_reg",Tgeneral_address_t,_param->_size_general_register); 110 111 ALLOC1_INTERFACE_END(_param->_nb_reg_free); 105 112 } 106 113 107 114 // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 108 115 { 109 ALLOC1_INTERFACE ("push_spr",OUT,SOUTH,"Free a special register",_param->_nb_reg_free);116 ALLOC1_INTERFACE_BEGIN("push_spr",OUT,SOUTH,_("Free a special register"),_param->_nb_reg_free); 110 117 111 118 ALLOC1_VALACK_OUT(out_PUSH_SPR_VAL ,VAL); 112 119 ALLOC1_VALACK_IN ( in_PUSH_SPR_ACK ,ACK); 113 120 ALLOC1_SIGNAL_OUT(out_PUSH_SPR_NUM_REG,"num_reg",Tspecial_address_t,_param->_size_special_register); 121 122 ALLOC1_INTERFACE_END(_param->_nb_reg_free); 114 123 } 115 124 … … 117 126 if (usage_is_set(_usage,USE_SYSTEMC)) 118 127 { 119 gpr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; 120 spr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; 121 122 for (uint32_t i=0; i<_param->_nb_bank; i++) 123 { 124 gpr_stat_list [i] = new stat_list_entry_t [_param->_nb_general_register_by_bank]; 125 spr_stat_list [i] = new stat_list_entry_t [_param->_nb_special_register_by_bank]; 126 } 127 128 internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert]; 129 internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire]; 130 internal_PUSH_GPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; 131 internal_PUSH_GPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; 132 internal_PUSH_SPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; 133 internal_PUSH_SPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; 128 ALLOC2(gpr_stat_list,stat_list_entry_t,_param->_nb_bank,_param->_nb_general_register_by_bank); 129 ALLOC2(spr_stat_list,stat_list_entry_t,_param->_nb_bank,_param->_nb_special_register_by_bank); 130 ALLOC1(internal_INSERT_ACK ,Tcontrol_t,_param->_nb_inst_insert); 131 ALLOC1(internal_RETIRE_ACK ,Tcontrol_t,_param->_nb_inst_retire); 132 ALLOC1(internal_PUSH_GPR_VAL ,Tcontrol_t,_param->_nb_reg_free); 133 ALLOC1(internal_PUSH_GPR_NUM_BANK,uint32_t ,_param->_nb_reg_free); 134 ALLOC1(internal_PUSH_SPR_VAL ,Tcontrol_t,_param->_nb_reg_free); 135 ALLOC1(internal_PUSH_SPR_NUM_BANK,uint32_t ,_param->_nb_reg_free); 134 136 } 135 137 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 29 30 delete in_NRESET; 30 31 31 delete [] in_INSERT_VAL;32 delete [] out_INSERT_ACK;33 delete [] in_INSERT_READ_RA;34 delete [] in_INSERT_NUM_REG_RA_PHY;35 delete [] in_INSERT_READ_RB;36 delete [] in_INSERT_NUM_REG_RB_PHY;37 delete [] in_INSERT_READ_RC;38 delete [] in_INSERT_NUM_REG_RC_PHY;39 delete [] in_INSERT_WRITE_RD;40 delete [] in_INSERT_NUM_REG_RD_PHY_NEW;41 delete [] in_INSERT_WRITE_RE;42 delete [] in_INSERT_NUM_REG_RE_PHY_NEW;32 DELETE1_SIGNAL( in_INSERT_VAL ,_param->_nb_inst_insert,1); 33 DELETE1_SIGNAL(out_INSERT_ACK ,_param->_nb_inst_insert,1); 34 DELETE1_SIGNAL( in_INSERT_READ_RA ,_param->_nb_inst_insert,1 ); 35 DELETE1_SIGNAL( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register); 36 DELETE1_SIGNAL( in_INSERT_READ_RB ,_param->_nb_inst_insert,1 ); 37 DELETE1_SIGNAL( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register); 38 DELETE1_SIGNAL( in_INSERT_READ_RC ,_param->_nb_inst_insert,1 ); 39 DELETE1_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register); 40 DELETE1_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); 41 DELETE1_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register); 42 DELETE1_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); 43 DELETE1_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register); 43 44 44 delete [] in_RETIRE_VAL ; 45 delete [] out_RETIRE_ACK ; 46 delete [] in_RETIRE_READ_RA ; 47 delete [] in_RETIRE_NUM_REG_RA_PHY ; 48 delete [] in_RETIRE_READ_RB ; 49 delete [] in_RETIRE_NUM_REG_RB_PHY ; 50 delete [] in_RETIRE_READ_RC ; 51 delete [] in_RETIRE_NUM_REG_RC_PHY ; 52 delete [] in_RETIRE_WRITE_RD ; 53 delete [] in_RETIRE_RESTORE_RD_PHY_OLD; 54 delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; 55 delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; 56 delete [] in_RETIRE_WRITE_RE ; 57 delete [] in_RETIRE_RESTORE_RE_PHY_OLD; 58 delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; 59 delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; 45 DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); 46 DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); 47 DELETE1_SIGNAL( in_RETIRE_RESTORE ,_param->_nb_inst_retire,1 ); 48 DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); 49 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register); 50 DELETE1_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire,1 ); 51 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire,_param->_size_general_register); 52 DELETE1_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire,1 ); 53 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire,_param->_size_special_register); 54 DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1 ); 55 DELETE1_SIGNAL( in_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire,1 ); 56 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire,_param->_size_general_register); 57 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire,_param->_size_general_register); 58 DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1 ); 59 DELETE1_SIGNAL( in_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire,1 ); 60 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire,_param->_size_special_register); 61 DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire,_param->_size_special_register); 60 62 61 delete [] out_PUSH_GPR_VAL ; 62 delete [] in_PUSH_GPR_ACK ; 63 DELETE1_SIGNAL(out_PUSH_GPR_VAL ,_param->_nb_reg_free,1); 64 DELETE1_SIGNAL( in_PUSH_GPR_ACK ,_param->_nb_reg_free,1); 65 DELETE1_SIGNAL(out_PUSH_GPR_NUM_REG,_param->_nb_reg_free,_param->_size_general_register); 63 66 64 delete [] out_PUSH_GPR_NUM_REG ; 65 delete [] out_PUSH_SPR_VAL ; 66 delete [] in_PUSH_SPR_ACK ; 67 delete [] out_PUSH_SPR_NUM_REG ; 68 69 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 71 delete [] gpr_stat_list; 72 delete [] spr_stat_list; 73 74 delete [] internal_INSERT_ACK ; 75 delete [] internal_RETIRE_ACK ; 76 delete [] internal_PUSH_GPR_VAL ; 77 delete [] internal_PUSH_GPR_NUM_BANK; 78 delete [] internal_PUSH_SPR_VAL ; 79 delete [] internal_PUSH_SPR_NUM_BANK; 67 DELETE1_SIGNAL(out_PUSH_SPR_VAL ,_param->_nb_reg_free,1); 68 DELETE1_SIGNAL( in_PUSH_SPR_ACK ,_param->_nb_reg_free,1); 69 DELETE1_SIGNAL(out_PUSH_SPR_NUM_REG,_param->_nb_reg_free,_param->_size_special_register); 70 71 DELETE2(gpr_stat_list ,_param->_nb_bank,_param->_nb_general_register_by_bank); 72 DELETE2(spr_stat_list ,_param->_nb_bank,_param->_nb_special_register_by_bank); 73 DELETE1(internal_INSERT_ACK ,_param->_nb_inst_insert); 74 DELETE1(internal_RETIRE_ACK ,_param->_nb_inst_retire); 75 DELETE1(internal_PUSH_GPR_VAL ,_param->_nb_reg_free); 76 DELETE1(internal_PUSH_GPR_NUM_BANK,_param->_nb_reg_free); 77 DELETE1(internal_PUSH_SPR_VAL ,_param->_nb_reg_free); 78 DELETE1(internal_PUSH_SPR_NUM_BANK,_param->_nb_reg_free); 80 79 } 81 82 80 83 81 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp
r88 r112 19 19 20 20 21 #undef FUNCTION22 #define FUNCTION "Stat_List_unit::genMealy"23 void Stat_List_unit::genMealy (void)24 {25 log_begin(Stat_List_unit,FUNCTION);26 log_function(Stat_List_unit,FUNCTION,_name.c_str());21 // #undef FUNCTION 22 // #define FUNCTION "Stat_List_unit::genMealy" 23 // void Stat_List_unit::genMealy (void) 24 // { 25 // log_begin(Stat_List_unit,FUNCTION); 26 // log_function(Stat_List_unit,FUNCTION,_name.c_str()); 27 27 28 for (uint32_t i=0; i<_param->_nb_inst_insert; i++)29 {30 bool ack = true;28 // for (uint32_t i=0; i<_param->_nb_inst_insert; i++) 29 // { 30 // bool ack = true; 31 31 32 if (PORT_READ(in_INSERT_READ_RA [i]))33 {34 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]);35 uint32_t bank = num_reg >> _param->_shift_gpr;36 uint32_t reg = num_reg & _param->_mask_gpr ;37 ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader);38 }32 // if (PORT_READ(in_INSERT_READ_RA [i])) 33 // { 34 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); 35 // uint32_t bank = num_reg >> _param->_shift_gpr; 36 // uint32_t reg = num_reg & _param->_mask_gpr ; 37 // ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); 38 // } 39 39 40 if (PORT_READ(in_INSERT_READ_RB [i]))41 {42 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]);43 uint32_t bank = num_reg >> _param->_shift_gpr;44 uint32_t reg = num_reg & _param->_mask_gpr ;45 ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader);46 }40 // if (PORT_READ(in_INSERT_READ_RB [i])) 41 // { 42 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); 43 // uint32_t bank = num_reg >> _param->_shift_gpr; 44 // uint32_t reg = num_reg & _param->_mask_gpr ; 45 // ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader); 46 // } 47 47 48 if (PORT_READ(in_INSERT_READ_RC [i]))49 {50 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]);51 uint32_t bank = num_reg >> _param->_shift_spr;52 uint32_t reg = num_reg & _param->_mask_spr ;53 ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader);54 }48 // if (PORT_READ(in_INSERT_READ_RC [i])) 49 // { 50 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); 51 // uint32_t bank = num_reg >> _param->_shift_spr; 52 // uint32_t reg = num_reg & _param->_mask_spr ; 53 // ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader); 54 // } 55 55 56 internal_INSERT_ACK [i] = ack;57 PORT_WRITE(out_INSERT_ACK [i], ack);58 }56 // internal_INSERT_ACK [i] = ack; 57 // PORT_WRITE(out_INSERT_ACK [i], ack); 58 // } 59 59 60 log_end(Stat_List_unit,FUNCTION);61 };60 // log_end(Stat_List_unit,FUNCTION); 61 // }; 62 62 63 63 }; // end namespace stat_list_unit -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp
r88 r112 26 26 log_function(Stat_List_unit,FUNCTION,_name.c_str()); 27 27 28 uint32_t gpr_ptr = internal_GPR_PTR_FREE;29 uint32_t spr_ptr = internal_SPR_PTR_FREE;28 uint32_t gpr_ptr = reg_GPR_PTR_FREE; 29 uint32_t spr_ptr = reg_SPR_PTR_FREE; 30 30 31 31 for (uint32_t i=0; i<_param->_nb_reg_free; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp
r106 r112 38 38 spr_stat_list [i][j].reset((spr++)<_param->_nb_spr_use_init); 39 39 } 40 internal_GPR_PTR_FREE = 0;41 internal_SPR_PTR_FREE = 0;40 reg_GPR_PTR_FREE = 0; 41 reg_SPR_PTR_FREE = 0; 42 42 } 43 43 else … … 51 51 log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); 52 52 53 if (PORT_READ(in_INSERT_READ_RA [i]))54 {55 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]);56 57 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg);58 59 uint32_t bank = num_reg >> _param->_shift_gpr;60 uint32_t reg = num_reg & _param->_mask_gpr ;61 gpr_stat_list [bank][reg].insert_read();62 }63 64 if (PORT_READ(in_INSERT_READ_RB [i]))65 {66 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]);67 68 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg);69 70 uint32_t bank = num_reg >> _param->_shift_gpr;71 uint32_t reg = num_reg & _param->_mask_gpr ;72 gpr_stat_list [bank][reg].insert_read();73 }74 75 if (PORT_READ(in_INSERT_READ_RC [i]))76 {77 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]);78 79 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg);80 81 uint32_t bank = num_reg >> _param->_shift_spr;82 uint32_t reg = num_reg & _param->_mask_spr ;83 spr_stat_list [bank][reg].insert_read();84 }53 // if (PORT_READ(in_INSERT_READ_RA [i])) 54 // { 55 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); 56 57 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 58 59 // uint32_t bank = num_reg >> _param->_shift_gpr; 60 // uint32_t reg = num_reg & _param->_mask_gpr ; 61 // gpr_stat_list [bank][reg].insert_read(); 62 // } 63 64 // if (PORT_READ(in_INSERT_READ_RB [i])) 65 // { 66 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); 67 68 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); 69 70 // uint32_t bank = num_reg >> _param->_shift_gpr; 71 // uint32_t reg = num_reg & _param->_mask_gpr ; 72 // gpr_stat_list [bank][reg].insert_read(); 73 // } 74 75 // if (PORT_READ(in_INSERT_READ_RC [i])) 76 // { 77 // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); 78 79 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 80 81 // uint32_t bank = num_reg >> _param->_shift_spr; 82 // uint32_t reg = num_reg & _param->_mask_spr ; 83 // spr_stat_list [bank][reg].insert_read(); 84 // } 85 85 86 86 if (PORT_READ(in_INSERT_WRITE_RD [i])) … … 88 88 Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); 89 89 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg 90 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg new : %d",num_reg); 91 91 92 92 uint32_t bank = num_reg >> _param->_shift_gpr; … … 97 97 if (PORT_READ(in_INSERT_WRITE_RE [i])) 98 98 { 99 T general_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]);100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg 99 Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); 100 101 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg new : %d",num_reg); 102 102 103 103 uint32_t bank = num_reg >> _param->_shift_spr; … … 115 115 log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); 116 116 117 if (PORT_READ(in_RETIRE_READ_RA [i])) 118 { 119 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); 120 121 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 122 123 uint32_t bank = num_reg >> _param->_shift_gpr; 124 uint32_t reg = num_reg & _param->_mask_gpr ; 125 gpr_stat_list [bank][reg].retire_read(); 126 } 127 128 if (PORT_READ(in_RETIRE_READ_RB [i])) 129 { 130 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); 131 132 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RD - num_reg : %d",num_reg); 133 134 uint32_t bank = num_reg >> _param->_shift_gpr; 135 uint32_t reg = num_reg & _param->_mask_gpr ; 136 gpr_stat_list [bank][reg].retire_read(); 137 } 138 139 if (PORT_READ(in_RETIRE_READ_RC [i])) 140 { 141 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); 142 143 log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 144 145 uint32_t bank = num_reg >> _param->_shift_spr; 146 uint32_t reg = num_reg & _param->_mask_spr ; 147 spr_stat_list [bank][reg].retire_read(); 148 } 117 Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); 118 119 log_printf(TRACE,Stat_List_unit,FUNCTION," * restore : %d",restore); 120 121 // if (PORT_READ(in_RETIRE_READ_RA [i])) 122 // { 123 // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); 124 125 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); 126 127 // uint32_t bank = num_reg >> _param->_shift_gpr; 128 // uint32_t reg = num_reg & _param->_mask_gpr ; 129 // gpr_stat_list [bank][reg].retire_read(); 130 // } 131 132 // if (PORT_READ(in_RETIRE_READ_RB [i])) 133 // { 134 // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); 135 136 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); 137 138 // uint32_t bank = num_reg >> _param->_shift_gpr; 139 // uint32_t reg = num_reg & _param->_mask_gpr ; 140 // gpr_stat_list [bank][reg].retire_read(); 141 // } 142 143 // if (PORT_READ(in_RETIRE_READ_RC [i])) 144 // { 145 // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); 146 147 // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); 148 149 // uint32_t bank = num_reg >> _param->_shift_spr; 150 // uint32_t reg = num_reg & _param->_mask_spr ; 151 // spr_stat_list [bank][reg].retire_read(); 152 // } 149 153 150 154 if (PORT_READ(in_RETIRE_WRITE_RD [i])) … … 157 161 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); 158 162 159 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD -num_reg_old : %d",num_reg);163 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); 160 164 161 165 uint32_t bank = num_reg >> _param->_shift_gpr; 162 166 uint32_t reg = num_reg & _param->_mask_gpr ; 163 gpr_stat_list [bank][reg].retire_write_old(restore _old);167 gpr_stat_list [bank][reg].retire_write_old(restore, restore_old); 164 168 } 165 169 { 166 170 Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); 167 171 168 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD -num_reg_new : %d",num_reg);172 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); 169 173 170 174 uint32_t bank = num_reg >> _param->_shift_gpr; 171 175 uint32_t reg = num_reg & _param->_mask_gpr ; 172 gpr_stat_list [bank][reg].retire_write_new(restore _old);176 gpr_stat_list [bank][reg].retire_write_new(restore, restore_old); 173 177 } 174 178 } … … 181 185 182 186 { 183 T general_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]);184 185 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg_new: %d",num_reg);187 Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); 188 189 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); 186 190 187 191 uint32_t bank = num_reg >> _param->_shift_spr; 188 192 uint32_t reg = num_reg & _param->_mask_spr ; 189 spr_stat_list [bank][reg].retire_write_old(restore _old);193 spr_stat_list [bank][reg].retire_write_old(restore, restore_old); 190 194 } 191 195 { 192 T general_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);193 194 log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE -num_reg_new : %d",num_reg);196 Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); 197 198 log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); 195 199 196 200 uint32_t bank = num_reg >> _param->_shift_spr; 197 201 uint32_t reg = num_reg & _param->_mask_spr ; 198 spr_stat_list [bank][reg].retire_write_new(restore _old);202 spr_stat_list [bank][reg].retire_write_new(restore, restore_old); 199 203 } 200 204 } … … 207 211 // ===================================================== 208 212 if (internal_PUSH_GPR_VAL [i] and PORT_READ(in_PUSH_GPR_ACK [i])) 209 gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][ internal_GPR_PTR_FREE].free();213 gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][reg_GPR_PTR_FREE].free(); 210 214 211 215 // ===================================================== … … 213 217 // ===================================================== 214 218 if (internal_PUSH_SPR_VAL [i] and PORT_READ(in_PUSH_SPR_ACK [i])) 215 spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][ internal_SPR_PTR_FREE].free();219 spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][reg_SPR_PTR_FREE].free(); 216 220 } 217 221 218 222 // Update pointer 219 internal_GPR_PTR_FREE = ((internal_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:internal_GPR_PTR_FREE)-1;220 internal_SPR_PTR_FREE = ((internal_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:internal_SPR_PTR_FREE)-1;223 reg_GPR_PTR_FREE = ((reg_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:reg_GPR_PTR_FREE)-1; 224 reg_SPR_PTR_FREE = ((reg_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:reg_SPR_PTR_FREE)-1; 221 225 } 222 226 223 227 224 228 #if (DEBUG >= DEBUG_TRACE) 225 log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); 226 for (uint32_t i=0; i<_param->_nb_bank; i++) 227 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 228 log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", 229 i, 230 j, 231 (i<<_param->_shift_gpr)|j, 232 gpr_stat_list[i][j]._is_free, 233 gpr_stat_list[i][j]._is_link, 234 gpr_stat_list[i][j]._is_valid, 235 gpr_stat_list[i][j]._counter); 236 for (uint32_t i=0; i<_param->_nb_bank; i++) 237 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 238 log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", 239 i, 240 j, 241 (i<<_param->_shift_spr)|j, 242 spr_stat_list[i][j]._is_free, 243 spr_stat_list[i][j]._is_link, 244 spr_stat_list[i][j]._is_valid, 245 spr_stat_list[i][j]._counter); 229 { 230 log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); 231 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); 232 log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); 233 234 for (uint32_t i=0; i<_param->_nb_bank; i++) 235 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 236 log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", 237 i, 238 j, 239 (i<<_param->_shift_gpr)|j, 240 gpr_stat_list[i][j]._is_free, 241 gpr_stat_list[i][j]._is_link// , 242 // gpr_stat_list[i][j]._is_valid, 243 // gpr_stat_list[i][j]._counter 244 ); 245 for (uint32_t i=0; i<_param->_nb_bank; i++) 246 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 247 log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", 248 i, 249 j, 250 (i<<_param->_shift_spr)|j, 251 spr_stat_list[i][j]._is_free, 252 spr_stat_list[i][j]._is_link// , 253 // spr_stat_list[i][j]._is_valid, 254 // spr_stat_list[i][j]._counter 255 ); 256 } 246 257 #endif 258 259 #ifdef DEBUG_TEST 260 # if 0 261 { 262 uint32_t size_rob = 64; 263 uint32_t nb_context = 1; 264 265 { 266 uint32_t nb_is_link = 0; 267 uint32_t nb_reg = 32; 268 for (uint32_t i=0; i<_param->_nb_bank; i++) 269 for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) 270 if (gpr_stat_list[i][j]._is_link) 271 nb_is_link ++; 272 273 log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_GPR_IS_LINK : %d",nb_is_link); 274 275 if (nb_is_link > size_rob+nb_context*nb_reg) 276 throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked gpr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); 277 } 278 279 { 280 uint32_t nb_is_link = 0; 281 uint32_t nb_reg = 2; 282 for (uint32_t i=0; i<_param->_nb_bank; i++) 283 for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) 284 if (spr_stat_list[i][j]._is_link) 285 nb_is_link ++; 286 287 log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_SPR_IS_LINK : %d",nb_is_link); 288 289 if (nb_is_link > size_rob+nb_context*nb_reg) 290 throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked spr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); 291 } 292 } 293 # endif 294 #endif 295 247 296 248 297 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
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