Changeset 117 for trunk/IPs/systemC/Environment/src
- Timestamp:
- May 16, 2009, 4:42:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/Environment/src
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/Environment/src/Environment_simulation_end.cpp
r88 r117 5 5 bool Environment::simulation_end(void) 6 6 { 7 return (nb_context_stop >= param->nb_ entity);7 return (nb_context_stop >= param->nb_thread); 8 8 } 9 9 -
trunk/IPs/systemC/Environment/src/Environment_stop.cpp
r88 r117 5 5 void Environment::stop(uint32_t num_context) 6 6 { 7 8 cout("<stop> : num_context : %d\n",num_context); 9 cout("<stop> : context_stop : %d\n",context_stop [num_context]); 10 cout("<stop> : nb_context_stop : %d\n",nb_context_stop); 11 12 7 13 if (context_stop [num_context] == false) 8 14 { … … 10 16 nb_context_stop ++; 11 17 12 if (nb_context_stop >= param->nb_entity) 13 sc_stop(); 18 if (nb_context_stop >= param->nb_thread) 19 { 20 cout("<stop> : end simulation\n"); 21 sc_stop(); 22 } 14 23 } 15 24 } -
trunk/IPs/systemC/Environment/src/Environment_transition.cpp
r114 r117 52 52 uint32_t size = (param->iaccess_size_address [i]+2)/8; 53 53 54 _cout(ENVIRONMENT," * information\n");55 _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));56 _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));57 _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));58 _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));59 _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));54 _cout(ENVIRONMENT," * information\n"); 55 _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context)); 56 _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet )); 57 _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address)); 58 _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type )); 59 _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size )); 60 60 61 61 // search the entity … … 72 72 (entity.segment->getType() == data::TYPE_TARGET_MEMORY)) 73 73 { 74 _cout(ENVIRONMENT," * OK !\n");74 _cout(ENVIRONMENT," * OK !\n"); 75 75 bus_error = false; 76 76 uncached = entity.segment->getUncached(); … … 78 78 if (must_read == true) // Test if must read the ram 79 79 { 80 _cout(ENVIRONMENT," * must read\n");80 _cout(ENVIRONMENT," * must read\n"); 81 81 // Read all instruction 82 82 for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++) 83 83 { 84 84 uint32_t addr = address+k*(size); 85 _cout(ENVIRONMENT," * addr : %.8x\n",addr);85 _cout(ENVIRONMENT," * addr : %.8x\n",addr); 86 86 87 87 bus_error |= !component_data->read(addr,size,read_iram[k]); … … 93 93 } 94 94 95 _cout(ENVIRONMENT," * inst :");96 for (int32_t cpt=(param->iaccess_size_instruction[ context]/8)-1; cpt>=0; --cpt)97 _ cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));98 _ cout(ENVIRONMENT, "\n");95 _cout(ENVIRONMENT," * inst :"); 96 for (int32_t cpt=(param->iaccess_size_instruction[i]/8)-1; cpt>=0; --cpt) 97 __cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt])); 98 __cout(ENVIRONMENT, "\n"); 99 99 } 100 100 } … … 102 102 else 103 103 { 104 _cout(ENVIRONMENT, " * KO !\n");105 _cout(ENVIRONMENT, " * present : %d\n",entity.present);104 _cout(ENVIRONMENT, " * KO !\n"); 105 _cout(ENVIRONMENT, " * present : %d\n",entity.present); 106 106 if (entity.present) 107 _cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);107 _cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY); 108 108 109 109 // entity is not present, or is present but is not a memory : have a bus error … … 121 121 cache_type.direction); 122 122 123 _cout(ENVIRONMENT, " * latence : %d\n",latence);123 _cout(ENVIRONMENT, " * latence : %d\n",latence); 124 124 125 125 // If is a respons -> compute the latence and push in the write_buffer 126 126 if (must_ack or (must_ack_on_error and bus_error)) 127 127 { 128 _cout(ENVIRONMENT, " * must ack\n");128 _cout(ENVIRONMENT, " * must ack\n"); 129 129 130 130 if (bus_error == true) 131 131 { 132 _cout(ENVIRONMENT," * Icache : have a bus error\n");133 _cout(ENVIRONMENT," * entity : %d\n",i);134 _cout(ENVIRONMENT," * port : %d\n",j);135 _cout(ENVIRONMENT," * req_addr : %x\n",address);136 _cout(ENVIRONMENT," * req_trdid : %d\n",context);137 _cout(ENVIRONMENT," * req_pktid : %d\n",packet );132 _cout(ENVIRONMENT," * Icache : have a bus error\n"); 133 _cout(ENVIRONMENT," * entity : %d\n",i); 134 _cout(ENVIRONMENT," * port : %d\n",j); 135 _cout(ENVIRONMENT," * req_addr : %x\n",address); 136 _cout(ENVIRONMENT," * req_trdid : %d\n",context); 137 _cout(ENVIRONMENT," * req_pktid : %d\n",packet ); 138 138 139 139 // Write in instruction [0] the bad address (only 32bit ....) … … 142 142 143 143 // Simplification : the size of a line is a multiple of size_iword (no test) 144 _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);144 _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i); 145 145 146 146 irsp_t * rsp = new irsp_t(context, … … 153 153 } 154 154 155 _cout(ENVIRONMENT, " * End request\n");155 _cout(ENVIRONMENT, " * End request\n"); 156 156 } 157 157 … … 172 172 uint32_t size = param->daccess_size_data [i]/8; 173 173 174 _cout(ENVIRONMENT," * information\n");175 _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));176 _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));177 _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));178 _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));179 _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));174 _cout(ENVIRONMENT," * information\n"); 175 _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context)); 176 _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet )); 177 _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address)); 178 _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type )); 179 _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size )); 180 180 181 181 bool uncached = false; … … 230 230 uint32_t num_tty = (address - entity.segment->getBase())>>4; 231 231 uint32_t num_print = ((address>>2) & 0x3); 232 _cout( ENVIRONMENT,"* TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);232 _cout(true," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print); 233 233 234 234 switch (num_print) … … 243 243 case 1 : // STOP 244 244 { 245 printf("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" 245 _cout(true,"\n"); 246 _cout(true,"***********************************************************************************************\n"); 247 _cout(true,"***** [ STOP ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" 246 248 ,static_cast<uint32_t>(sc_simulation_time()) 247 249 ,static_cast<uint32_t>(address ) … … 251 253 ,static_cast<uint32_t>((wdata>> 0)&0xff) 252 254 ); 253 254 if (wdata == 0) 255 std::cout << STR_OK << std::endl; 256 else 257 std::cout << STR_KO << std::endl; 255 _cout(true,"***********************************************************************************************\n"); 256 _cout(true,"\n"); 257 _cout(true,"%s\n",(wdata == 0)?STR_OK:STR_KO); 258 _cout(true,"\n"); 258 259 259 260 stop (context); … … 263 264 case 2 : // PRINT 264 265 { 265 printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" 266 _cout(true,"\n"); 267 _cout(true,"-----------------------------------------------------------------------------------------------\n"); 268 _cout(true,"----- [ PRINT ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" 266 269 ,static_cast<uint32_t>(sc_simulation_time()) 267 270 ,static_cast<uint32_t>(address ) … … 271 274 ,static_cast<uint32_t>((wdata>> 0)&0xff) 272 275 ); 276 _cout(true,"-----------------------------------------------------------------------------------------------\n"); 277 _cout(true,"\n"); 273 278 274 279 break; … … 276 281 default : 277 282 { 278 printf("[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);283 _cout(true,"[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print); 279 284 bus_error = true; 280 285 } … … 288 293 case data::TYPE_TARGET_MEMORY : 289 294 { 290 _cout(ENVIRONMENT," MEMORY\n");291 _cout(ENVIRONMENT," access : %x\n",address);295 _cout(ENVIRONMENT," * TYPE_TARGET_MEMORY\n"); 296 _cout(ENVIRONMENT," * access : %x\n",address); 292 297 293 298 if (must_read == true) 294 299 { 295 300 // Read 296 _cout(ENVIRONMENT," * Read (%d bytes)\n",size);301 _cout(ENVIRONMENT," * Read (%d bytes)\n",size); 297 302 bus_error |= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word 298 303 299 _cout(ENVIRONMENT," * Rdata : ");300 for (uint32_t i=0; i<nb_bytes; i++)301 _cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));302 _cout(ENVIRONMENT,".\n");303 304 304 // Multiple copy 305 305 for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes) … … 314 314 { 315 315 // Write 316 _cout(ENVIRONMENT," * Write (%d bytes)\n",size);317 _cout(ENVIRONMENT," * Wdata : %x\n",wdata);316 _cout(ENVIRONMENT," * Write (%d bytes)\n",size); 317 _cout(ENVIRONMENT," * Wdata : %x\n",wdata); 318 318 itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes); 319 319 … … 329 329 case data::TYPE_TARGET_RAMLOCK : 330 330 { 331 _cout(ENVIRONMENT," * TYPE_TARGET_RAMLOCK\n"); 332 331 333 // Access is on a byte, else error 332 334 if (nb_bytes != 1) … … 338 340 uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access 339 341 uint32_t num_component_ramlock = entity.segment->getIndex(); 342 343 _cout(ENVIRONMENT," * num_ramlock : %d\n",num_ramlock ); 344 _cout(ENVIRONMENT," * num_component_ramlock : %d\n",num_component_ramlock); 340 345 341 346 // No test : because out of range … … 361 366 case data::TYPE_TARGET_SIM2OS : 362 367 { 368 _cout(ENVIRONMENT," * TYPE_TARGET_SIM2OS\n"); 369 363 370 // Mapping : 364 371 // [0] number of service - Wonly - A write in this register lunch the execution of service … … 368 375 369 376 uint32_t num_reg = (address - entity.segment->getBase())>>2; 377 378 _cout(ENVIRONMENT," * num_reg : %d\n",num_reg); 370 379 371 380 switch (num_reg) … … 380 389 else 381 390 { 382 _cout(ENVIRONMENT," <sim2os>service : %x\n",wdata);391 _cout(ENVIRONMENT," * service : %x\n",wdata); 383 392 component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata))); 384 393 } … … 396 405 // Decomposition en groupe octect 397 406 Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result)); 398 _cout(ENVIRONMENT," <sim2os>result : %x\n",result);407 _cout(ENVIRONMENT," * result : %x\n",result); 399 408 400 409 itoa<Tdcache_data_t>(result,read_dram[0],size); … … 413 422 // Decomposition en groupe octect 414 423 Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error; 415 _cout(ENVIRONMENT," <sim2os>error : %x\n",error);424 _cout(ENVIRONMENT," * error : %x\n",error); 416 425 417 426 itoa<Tdcache_data_t>(error,read_dram[0],size); … … 429 438 else 430 439 { 431 _cout(ENVIRONMENT," <sim2os>argument[%d] : %x\n",num_reg-1,wdata);440 _cout(ENVIRONMENT," * argument[%d] : %x\n",num_reg-1,wdata); 432 441 component_sim2os->parameter(num_reg-2,(void *)wdata); 433 442 } … … 480 489 if (bus_error == true) 481 490 { 482 _cout(ENVIRONMENT," * Dcache : have a bus error\n");483 _cout(ENVIRONMENT," * entity : %d\n",i);484 _cout(ENVIRONMENT," * port : %d\n",j);485 _cout(ENVIRONMENT," * req_addr : 0x%x\n",address);486 _cout(ENVIRONMENT," * req_trdid : %d\n",context);487 _cout(ENVIRONMENT," * req_pktid : %d\n",packet );491 _cout(ENVIRONMENT," * Dcache : have a bus error\n"); 492 _cout(ENVIRONMENT," * entity : %d\n",i); 493 _cout(ENVIRONMENT," * port : %d\n",j); 494 _cout(ENVIRONMENT," * req_addr : 0x%x\n",address); 495 _cout(ENVIRONMENT," * req_trdid : %d\n",context); 496 _cout(ENVIRONMENT," * req_pktid : %d\n",packet ); 488 497 489 498 // Write in data [0] the bad address (32bit or 64bits ) 490 499 itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8); 491 500 } 501 502 _cout(ENVIRONMENT," * Rdata : "); 503 for (uint32_t i=0; i<nb_bytes; i++) 504 __cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i])); 505 _cout(ENVIRONMENT,".\n"); 492 506 493 507 // Simplification : the size of a line is a multiple of size_iword (no test) … … 501 515 } 502 516 } 517 503 518 //============================================================================= 504 519 //===== [ OTHERS ]============================================================= … … 523 538 // { 524 539 // // Test if transaction 525 // // cout << "[" << i << "]"526 // // << "[" << j << "] "527 // // << "dreq_val : " << DCACHE [i][j].REQ_VAL.read() << " "528 // // << "dreq_ack : " << dreq_ack [i][j] << endl;529 540 530 541 // if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false) … … 600 611 // case 1 : // STOP 601 612 // { 602 // printf("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n"613 // cout("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" 603 614 // ,(unsigned int)sc_simulation_time() 604 615 // ,(unsigned int)addr … … 624 635 // case 2 : // PRINT 625 636 // { 626 // printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"637 // cout("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" 627 638 // ,(unsigned int)sc_simulation_time() 628 639 // ,(unsigned int)addr … … 637 648 // default : 638 649 // { 639 // printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);650 // cout("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print); 640 651 // exit(1); 641 652 // } … … 667 678 668 679 // /* 669 // printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());670 // printf(" * addr : %.8x\n" ,(uint32_t)addr);671 // printf(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());672 // printf(" * r/w : %d/%d\n",must_read,must_write);673 // printf(" * val : %d\n" ,(uint32_t)read_dram[0]);680 // cout("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time()); 681 // cout(" * addr : %.8x\n" ,(uint32_t)addr); 682 // cout(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read()); 683 // cout(" * r/w : %d/%d\n",must_read,must_write); 684 // cout(" * val : %d\n" ,(uint32_t)read_dram[0]); 674 685 // */ 675 686 // break; … … 696 707 // else 697 708 // { 698 // printf("<sim2os> service : %.8x\n",(uint32_t)wdata);709 // cout("<sim2os> service : %.8x\n",(uint32_t)wdata); 699 710 // component_sim2os->execute(int2service((uint32_t)wdata)); 700 711 // } … … 712 723 // // Decomposition en groupe octect 713 724 // uint32_t result = (uint32_t) component_sim2os->result; 714 // printf("<sim2os> result : %.8x (%d)\n",result,result);725 // cout("<sim2os> result : %.8x (%d)\n",result,result); 715 726 716 727 // read_dram = itoa(result,read_dram,SIZE_DDATA/8); … … 729 740 // // Decomposition en groupe octect 730 741 // uint32_t error = (uint32_t) component_sim2os->error; 731 // printf("<sim2os> error : %.8x\n",error);742 // cout("<sim2os> error : %.8x\n",error); 732 743 // read_dram = itoa(error ,read_dram,SIZE_DDATA/8); 733 744 // } … … 744 755 // { 745 756 // uint32_t data = (uint32_t)wdata; 746 // printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);757 // cout("<sim2os> argument[%d] : %.8x\n",num_reg-1,data); 747 758 // component_sim2os->parameter(num_reg-2,(void *)data); 748 759 // } … … 793 804 // { 794 805 // if (bus_error == true) 795 // cout << "Dcache : have a bus error" << endl;806 // cout("Dcache : have a bus error"); 796 807 // component_buffer_drsp [i]->push(latence, 797 808 // Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
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