Ignore:
Timestamp:
May 21, 2009, 12:01:32 AM (15 years ago)
Author:
rosiere
Message:

1) Stat List : scan all queue to find free register
2) Write_queue : test "genMealy" add bypass [0]
3) Functionnal_unit : add const parameters to add or not the pipeline_in
4) Load Store Unit : if load make an exception, free nb_check
5) Debug, change test to add model

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue
Files:
1 added
7 edited
1 moved

Legend:

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  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h

    r115 r118  
    2424
    2525
     26
    2627  class Parameters : public morpheo::behavioural::Parameters
    2728  {
    2829    //-----[ fields ]------------------------------------------------------------
    29   public : uint32_t              _size_queue                   ;
    30   public : uint32_t              _nb_context                   ;
    31   public : uint32_t              _nb_front_end                 ;
    32   public : uint32_t              _nb_ooo_engine                ;
    33   public : uint32_t              _nb_packet                    ;
    34 //public : uint32_t              _size_general_data            ;
    35   public : uint32_t              _nb_general_register          ;
    36 //public : uint32_t              _size_special_data            ;
    37   public : uint32_t              _nb_special_register          ;
    38   public : uint32_t              _nb_bypass_write              ;
    39   public : Twrite_queue_scheme_t _queue_scheme                 ;
    40 
    41   public : uint32_t              _nb_gpr_write                 ;
    42   public : uint32_t              _nb_spr_write                 ;
    43                                
    44 //public : uint32_t              _size_context_id              ;
    45 //public : uint32_t              _size_front_end_id            ;
    46 //public : uint32_t              _size_ooo_engine_id           ;
    47 //public : uint32_t              _size_packet_id               ;
    48 //public : uint32_t              _size_general_register        ;
    49 //public : uint32_t              _size_special_register        ;
    50   public : uint32_t              _size_internal_queue          ;
    51                                
    52 //public : bool                  _have_port_context_id         ;
    53 //public : bool                  _have_port_front_end_id      ;
    54 //public : bool                  _have_port_ooo_engine_id      ;
    55 //public : bool                  _have_port_packet_id          ;
     30  public : uint32_t               _size_queue             ;
     31  public : uint32_t               _nb_context             ;
     32  public : uint32_t               _nb_front_end           ;
     33  public : uint32_t               _nb_ooo_engine          ;
     34  public : uint32_t               _nb_packet              ;
     35//public : uint32_t               _size_general_data      ;
     36  public : uint32_t               _nb_general_register    ;
     37//public : uint32_t               _size_special_data      ;
     38  public : uint32_t               _nb_special_register    ;
     39  public : uint32_t               _nb_bypass_write        ;
     40  public : Twrite_queue_scheme_t  _queue_scheme           ;
     41  public : Tbypass_write_scheme_t _bypass_write_scheme    ;
     42  public : uint32_t               _nb_gpr_write           ;
     43  public : uint32_t               _nb_spr_write           ;
     44                                  
     45//public : uint32_t               _size_context_id        ;
     46//public : uint32_t               _size_front_end_id      ;
     47//public : uint32_t               _size_ooo_engine_id     ;
     48//public : uint32_t               _size_packet_id         ;
     49//public : uint32_t               _size_general_register  ;
     50//public : uint32_t               _size_special_register  ;
     51  public : uint32_t               _size_internal_queue    ;
     52                                  
     53//public : bool                   _have_port_context_id   ;
     54//public : bool                   _have_port_front_end_id ;
     55//public : bool                   _have_port_ooo_engine_id;
     56//public : bool                   _have_port_packet_id    ;
    5657
    5758    //-----[ methods ]-----------------------------------------------------------

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h

    r115 r118  
    2525      ,WRITE_QUEUE_SCHEME_MEALY // Write register and pop can be in same cycle
    2626    } Twrite_queue_scheme_t;
     27
     28  typedef enum
     29    {
     30      BYPASS_WRITE_FROM_ALU,
     31      BYPASS_WRITE_FROM_QUEUE
     32    } Tbypass_write_scheme_t;
    2733
    2834  class write_queue_entry_t
    … …  
    108114  };
    109115
     116  template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Tbypass_write_scheme_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Tbypass_write_scheme_t& x)
     117  {
     118    switch (x)
     119      {
     120      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::BYPASS_WRITE_FROM_ALU   : return "alu"  ; break;
     121      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::BYPASS_WRITE_FROM_QUEUE : return "queue"; break;
     122      default : return ""; break;
     123      }
     124  };
     125
     126  template<> inline morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Tbypass_write_scheme_t fromString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Tbypass_write_scheme_t>(const std::string& x)
     127  {
     128    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::BYPASS_WRITE_FROM_ALU))) == 0) or
     129         (x.compare("alu") == 0))
     130      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::BYPASS_WRITE_FROM_ALU;
     131    if ( (x.compare(toString(static_cast<uint32_t>(morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::BYPASS_WRITE_FROM_QUEUE))) == 0) or
     132         (x.compare("queue") == 0))
     133      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::BYPASS_WRITE_FROM_QUEUE;
     134   
     135    throw (ErrorMorpheo ("<fromString> : Unknow string : \""+x+"\""));
     136  };
     137
    110138}; // end namespace morpheo             
    111139

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h

    r115 r118  
    172172  public  : void     transition                (void);
    173173  public  : void     genMoore                  (void);
    174   public  : void     genMealy                  (void);
     174  public  : void     genMealy_write            (void);
     175  public  : void     genMealy_bypass           (void);
    175176#endif                                         
    176177#ifdef STATISTICS

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp

    r115 r118  
    4545    _nb_bypass_write         = nb_bypass_write    ;
    4646    _queue_scheme            = queue_scheme       ;
     47    _bypass_write_scheme     = BYPASS_WRITE_FROM_ALU;
     48//  _bypass_write_scheme     = BYPASS_WRITE_FROM_QUEUE;
    4749
    4850    _nb_gpr_write            = 1;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters_msg_error.cpp

    r113 r118  
    2828    Parameters_test test (_type);
    2929
    30     if (_nb_bypass_write > _size_queue)
     30    if ((_bypass_write_scheme == BYPASS_WRITE_FROM_ALU)   and (_nb_bypass_write > _size_queue))
    3131      test.error("The write_queue can't have more bypass_write than entry in the queue.\n");
     32    if ((_bypass_write_scheme == BYPASS_WRITE_FROM_QUEUE) and (_nb_bypass_write > _size_queue-1))
     33      test.error("The write_queue can't have more bypass_write than entry in the queue -1 (the write_queue[0] is unnecessary).\n");
    3234
    3335    log_printf(FUNC,Write_queue,FUNCTION,"End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp

    r115 r118  
    9292        if (_param->_queue_scheme == WRITE_QUEUE_SCHEME_MEALY)
    9393          {
    94         log_printf(INFO,Write_queue,FUNCTION,"Method - genMealy");
     94        log_printf(INFO,Write_queue,FUNCTION,"Method - genMealy_write");
    9595
    96         SC_METHOD (genMealy);
     96        SC_METHOD (genMealy_write);
    9797        dont_initialize ();
    9898        sensitive << (*(in_CLOCK)).neg(); // need internal register
    … …  
    106106# endif   
    107107          }
     108
     109        if ((_param->_bypass_write_scheme == BYPASS_WRITE_FROM_ALU) and
     110            (_param->_nb_bypass_write > 0))
     111          {
     112        log_printf(INFO,Write_queue,FUNCTION,"Method - genMealy_bypass");
     113
     114        SC_METHOD (genMealy_bypass);
     115        dont_initialize ();
     116//      sensitive << (*(in_CLOCK)).neg(); // don't need internal register
     117        sensitive << (*(in_WRITE_QUEUE_IN_VAL          ))
     118                  << (*(in_WRITE_QUEUE_IN_WRITE_RD     ))
     119                  << (*(in_WRITE_QUEUE_IN_NUM_REG_RD   ))
     120                  << (*(in_WRITE_QUEUE_IN_DATA_RD      ))
     121                  << (*(in_WRITE_QUEUE_IN_WRITE_RE     ))
     122                  << (*(in_WRITE_QUEUE_IN_NUM_REG_RE   ))
     123                  << (*(in_WRITE_QUEUE_IN_DATA_RE      ));
     124        if (_param->_have_port_ooo_engine_id)
     125        sensitive << (*(in_WRITE_QUEUE_IN_OOO_ENGINE_ID));
     126
     127
     128# ifdef SYSTEMCASS_SPECIFIC
     129        // List dependency information
     130# endif   
     131          }
    108132
    109133#endif

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMealy_write.cpp

    r116 r118  
    2020
    2121#undef  FUNCTION
    22 #define FUNCTION "Write_queue::genMealy"
    23   void Write_queue::genMealy (void)
     22#define FUNCTION "Write_queue::genMealy_write"
     23  void Write_queue::genMealy_write (void)
    2424  {
    2525    log_begin(Write_queue,FUNCTION);

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp

    r117 r118  
    2929    {
    3030      std::list<write_queue_entry_t *>::iterator it = _queue->begin();
    31       for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
     31
     32      // first bypass is the write_queue_in
     33      uint32_t first_index = ((_param->_bypass_write_scheme == BYPASS_WRITE_FROM_ALU)?1:0);
     34      for (uint32_t i=first_index; i<_param->_nb_bypass_write; i++)
    3235        {
    33           bool val     = i < _queue->size();
    34          
     36          // before because first slot is on {GPR|SPR}_WRITE. Also, take next
     37          if (it != _queue->end())
     38            it++;
     39
     40          uint32_t index = i;
     41//        bool val = (i+1) < _queue->size();
     42          bool val = (it != _queue->end());
     43
    3544          if (val)
    3645            {
    3746              if (_param->_have_port_ooo_engine_id)
    38               PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], (*it)->_ooo_engine_id);
    39               PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [i], (*it)->_num_reg_rd);
    40               PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [i], (*it)->_data_rd   );
    41               PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [i], (*it)->_num_reg_re);
    42               PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [i], (*it)->_data_re   );
     47              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], (*it)->_ooo_engine_id);
     48              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], (*it)->_num_reg_rd);
     49              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], (*it)->_data_rd   );
     50              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], (*it)->_num_reg_re);
     51              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], (*it)->_data_re   );
    4352            }
    4453#ifdef SYSTEMC_VHDL_COMPATIBILITY
    … …  
    4655            {
    4756              if (_param->_have_port_ooo_engine_id)
    48               PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [i], 0);
    49               PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [i], 0);
    50               PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [i], 0);
    51               PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [i], 0);
    52               PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [i], 0);
     57              PORT_WRITE(out_BYPASS_WRITE_OOO_ENGINE_ID [index], 0);
     58              PORT_WRITE(out_BYPASS_WRITE_GPR_NUM_REG   [index], 0);
     59              PORT_WRITE(out_BYPASS_WRITE_GPR_DATA      [index], 0);
     60              PORT_WRITE(out_BYPASS_WRITE_SPR_NUM_REG   [index], 0);
     61              PORT_WRITE(out_BYPASS_WRITE_SPR_DATA      [index], 0);
    5362            }
    5463#endif
    5564
    56           PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [i], val and (*it)->_write_rd  );
    57           PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [i], val and (*it)->_write_re  );
    58          
    59           if (it != _queue->end())
    60             it++;
     65          PORT_WRITE(out_BYPASS_WRITE_GPR_VAL       [index], val and (*it)->_write_rd  );
     66          PORT_WRITE(out_BYPASS_WRITE_SPR_VAL       [index], val and (*it)->_write_re  );
    6167        }
    6268    }
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