Changeset 122 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit
- Timestamp:
- Jun 3, 2009, 10:15:51 AM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r121 r122 143 143 public : SC_IN (Tcontrol_t ) *** in_RETIRE_EVENT_ACK ;//[nb_front_end][nb_context] 144 144 public : SC_OUT(Tevent_state_t ) *** out_RETIRE_EVENT_STATE ;//[nb_front_end][nb_context] 145 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_FLUSH ;//[nb_front_end][nb_context] 146 public : SC_OUT(Tcontrol_t ) *** out_RETIRE_EVENT_STOP ;//[nb_front_end][nb_context] 145 147 146 148 // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 233 235 private : uint32_t reg_NUM_BANK_HEAD ; 234 236 private : uint32_t reg_NUM_BANK_TAIL ; 237 private : uint32_t reg_NUM_PTR_TAIL ; 235 238 private : uint32_t * reg_BANK_PTR ;//[nb_bank] 236 239 … … 238 241 private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] 239 242 240 private : T event_state_t** reg_EVENT_STATE ;//[nb_front_end][nb_context]241 243 private : Tcommit_event_state_t ** reg_EVENT_STATE ;//[nb_front_end][nb_context] 244 //private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] 242 245 private : bool ** reg_EVENT_STOP ;//[nb_front_end][nb_context] 246 private : uint32_t ** reg_EVENT_NUM_BANK ;//[nb_front_end][nb_context] 247 private : uint32_t ** reg_EVENT_NUM_PTR ;//[nb_front_end][nb_context] 248 private : bool ** reg_EVENT_CAN_RESTART ;//[nb_front_end][nb_context] 249 private : uint32_t ** reg_EVENT_PACKET ;//[nb_front_end][nb_context] 250 private : bool ** reg_EVENT_LAST ;//[nb_front_end][nb_context] 251 private : uint32_t ** reg_EVENT_LAST_NUM_BANK ;//[nb_front_end][nb_context] 252 private : uint32_t ** reg_EVENT_LAST_NUM_PTR ;//[nb_front_end][nb_context] 243 253 244 254 //private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r121 r122 28 28 { 29 29 ROB_EMPTY , // 30 30 31 ROB_BRANCH_WAIT_END , // 31 32 ROB_BRANCH_COMPLETE , // 32 ROB_STORE_WAIT_HEAD_OK , // 33 // ROB_STORE_WAIT_HEAD_KO , // 34 ROB_STORE_HEAD_OK , // 35 ROB_STORE_HEAD_KO , // 33 34 ROB_STORE_WAIT_END_OK , // 35 ROB_STORE_WAIT_END_KO , // 36 ROB_STORE_OK , // 37 ROB_STORE_KO , // 38 ROB_STORE_OK_WAIT_END , // 39 ROB_STORE_KO_WAIT_END , // 40 ROB_STORE_EVENT , // 41 36 42 ROB_OTHER_WAIT_END , // 37 43 … … 50 56 ROB_END_EXCEPTION_WAIT_HEAD , // 51 57 ROB_END_EXCEPTION_UPDATE , // 52 ROB_END_EXCEPTION // 58 ROB_END_EXCEPTION , // 59 ROB_END 60 } rob_state_t; 53 61 54 } rob_state_t; 62 typedef enum 63 { 64 COMMIT_EVENT_STATE_NO_EVENT , 65 COMMIT_EVENT_STATE_EVENT , 66 COMMIT_EVENT_STATE_WAIT_DECOD, 67 COMMIT_EVENT_STATE_WAIT_END , 68 COMMIT_EVENT_STATE_END 69 } Tcommit_event_state_t; 70 71 #define commit_event_state_to_event_state(x) ((x==COMMIT_EVENT_STATE_EVENT)?EVENT_STATE_EVENT:((x==COMMIT_EVENT_STATE_WAIT_DECOD)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_WAIT_END)?EVENT_STATE_WAITEND:((x==COMMIT_EVENT_STATE_END)?EVENT_STATE_END:EVENT_STATE_NO_EVENT)))) 72 55 73 56 74 class entry_t 57 75 { 58 76 public : rob_state_t state ; 77 public : rob_state_t state_old ; 59 78 public : uint32_t ptr ; 60 79 public : Tcontext_t front_end_id ; … … 98 117 //public : Tgeneral_data_t data_commit ; // branch's destination 99 118 #ifdef DEBUG 119 public : Tgeneral_data_t load_data ; 100 120 public : Taddress_t address ; 101 121 #endif … … 121 141 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END : return "ROB_BRANCH_WAIT_END" ; break; 122 142 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE : return "ROB_BRANCH_COMPLETE" ; break; 123 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK : return "ROB_STORE_WAIT_HEAD_OK" ; break; 124 // case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO : return "ROB_STORE_WAIT_HEAD_KO" ; break; 125 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK : return "ROB_STORE_HEAD_OK" ; break; 126 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "ROB_STORE_HEAD_KO" ; break; 143 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_END_OK : return "ROB_STORE_WAIT_END_OK" ; break; 144 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_END_KO : return "ROB_STORE_WAIT_END_KO" ; break; 145 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK : return "ROB_STORE_OK" ; break; 146 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO : return "ROB_STORE_KO" ; break; 147 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_OK_WAIT_END : return "ROB_STORE_OK_WAIT_END" ; break; 148 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_KO_WAIT_END : return "ROB_STORE_KO_WAIT_END" ; break; 127 149 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "ROB_OTHER_WAIT_END" ; break; 128 150 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EVENT_WAIT_END : return "ROB_EVENT_WAIT_END" ; break; … … 140 162 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_UPDATE : return "ROB_END_EXCEPTION_UPDATE" ; break; 141 163 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "ROB_END_EXCEPTION" ; break; 164 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END : return "ROB_END" ; break; 142 165 143 166 default : return "" ; break; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r121 r122 141 141 _ALLOC2_VALACK_IN ( in_RETIRE_EVENT_ACK ,ACK,_param->_nb_front_end,_param->_nb_context[it1]); 142 142 _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE ,"state" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_front_end,_param->_nb_context[it1]); 143 _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_FLUSH ,"flush" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 144 _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STOP ,"stop" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); 143 145 144 146 ALLOC2_INTERFACE_END(_param->_nb_front_end,_param->_nb_context[it1]); … … 306 308 307 309 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 308 ALLOC2(_nb_cycle_idle ,double ,_param->_nb_front_end,_param->_nb_context [it1]);309 ALLOC1(_rob ,std::list<entry_t*> ,_param->_nb_bank);310 ALLOC2(_nb_cycle_idle ,double ,_param->_nb_front_end,_param->_nb_context [it1]); 311 ALLOC1(_rob ,std::list<entry_t*> ,_param->_nb_bank); 310 312 311 ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank);312 313 ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]);314 ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]);313 ALLOC1(reg_BANK_PTR ,uint32_t ,_param->_nb_bank); 314 315 ALLOC2(reg_NB_INST_COMMIT_ALL ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); 316 ALLOC2(reg_NB_INST_COMMIT_MEM ,Tcounter_t ,_param->_nb_front_end,_param->_nb_context [it1]); 315 317 316 ALLOC2(reg_EVENT_STATE ,Tevent_state_t,_param->_nb_front_end,_param->_nb_context [it1]); 317 ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 318 ALLOC2(reg_EVENT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 319 320 // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 321 ALLOC2(reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 322 ALLOC2(reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 323 ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 324 ALLOC2(reg_PC_NEXT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 318 ALLOC2(reg_EVENT_STATE ,Tcommit_event_state_t,_param->_nb_front_end,_param->_nb_context [it1]); 319 // ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 320 ALLOC2(reg_EVENT_STOP ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 321 ALLOC2(reg_EVENT_NUM_BANK ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 322 ALLOC2(reg_EVENT_NUM_PTR ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 323 ALLOC2(reg_EVENT_CAN_RESTART ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 324 ALLOC2(reg_EVENT_PACKET ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 325 ALLOC2(reg_EVENT_LAST ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 326 ALLOC2(reg_EVENT_LAST_NUM_BANK ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 327 ALLOC2(reg_EVENT_LAST_NUM_PTR ,uint32_t ,_param->_nb_front_end,_param->_nb_context [it1]); 328 329 // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 330 ALLOC2(reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 331 ALLOC2(reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 332 ALLOC2(reg_PC_CURRENT_IS_DS_TAKE,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 333 ALLOC2(reg_PC_NEXT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 325 334 } 326 335 … … 345 354 if (_param->_have_thread [i]) 346 355 { 356 347 357 std::string filename = morpheo::filename(MORPHEO_LOG, 348 358 "Instruction_flow-thread_"+toString(i), … … 351 361 false, 352 362 log_with_pid, 353 false); 363 true); 364 365 log_printf(TRACE,Commit_unit,FUNCTION,"KANE : %s",filename.c_str()); 354 366 355 instruction_log_file [i] 367 instruction_log_file [i].open(filename.c_str() ,std::ios::out | std::ios::trunc); 356 368 } 357 369 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r121 r122 94 94 DELETE2_SIGNAL( in_RETIRE_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1],1); 95 95 DELETE2_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_event_state); 96 DELETE2_SIGNAL(out_RETIRE_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context[it1],1); 97 DELETE2_SIGNAL(out_RETIRE_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context[it1],1); 96 98 97 99 DELETE1_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit,1 ); … … 202 204 DELETE2(reg_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context [it1]); 203 205 DELETE2(reg_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context [it1]); 206 204 207 DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 205 208 // DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); 206 209 DELETE2(reg_EVENT_STOP ,_param->_nb_front_end,_param->_nb_context [it1]); 210 DELETE2(reg_EVENT_NUM_BANK ,_param->_nb_front_end,_param->_nb_context [it1]); 211 DELETE2(reg_EVENT_NUM_PTR ,_param->_nb_front_end,_param->_nb_context [it1]); 212 DELETE2(reg_EVENT_CAN_RESTART ,_param->_nb_front_end,_param->_nb_context [it1]); 213 DELETE2(reg_EVENT_PACKET ,_param->_nb_front_end,_param->_nb_context [it1]); 214 DELETE2(reg_EVENT_LAST ,_param->_nb_front_end,_param->_nb_context [it1]); 215 DELETE2(reg_EVENT_LAST_NUM_BANK ,_param->_nb_front_end,_param->_nb_context [it1]); 216 DELETE2(reg_EVENT_LAST_NUM_PTR ,_param->_nb_front_end,_param->_nb_context [it1]); 217 207 218 // DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); 208 219 DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp
r117 r122 30 30 #endif 31 31 bool can_rename_select [_param->_nb_rename_unit]; 32 bool event_stop; 33 32 // bool event_stop; 33 34 // // Initialisation 35 // event_stop = false; // one signal for all context. 36 // for (uint32_t i=0; i<_param->_nb_front_end; ++i) 37 // for (uint32_t j=0; j<_param->_nb_context[i]; ++j) 38 // event_stop |= reg_EVENT_STOP [i][j]; 39 34 40 // Initialisation 35 event_stop = false; // one signal for all context.36 for (uint32_t i=0; i<_param->_nb_front_end; ++i)37 for (uint32_t j=0; j<_param->_nb_context[i]; ++j)38 event_stop |= reg_EVENT_STOP [i][j];39 41 for (uint32_t i=0; i<_param->_nb_bank; i++) 40 42 { … … 57 59 // log_printf(TRACE,Commit_unit,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); 58 60 59 if (not event_stop)61 // if (not event_stop) 60 62 { 61 63 std::list<generic::priority::select_t> * select_insert = _priority_insert ->select(); // same select for all insert -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r121 r122 56 56 57 57 } 58 58 59 // Scan Top of each bank 59 60 internal_BANK_RETIRE_HEAD = reg_NUM_BANK_HEAD; … … 62 63 uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; 63 64 65 // Test if have instruction 64 66 if (not _rob[num_bank].empty()) 65 67 { … … 68 70 uint32_t x = entry->rename_unit_id; 69 71 uint32_t y = num_inst_retire [x]; 70 72 bool bypass= false; 71 73 // test if : 72 74 // * can retire (all previous instruction is retired) … … 77 79 { 78 80 rob_state_t state = entry->state; 81 Tcontext_t front_end_id = entry->front_end_id; 82 Tcontext_t context_id = entry->context_id; 83 79 84 if ((state == ROB_END_OK ) or 80 85 (state == ROB_END_KO ) or … … 87 92 Tcontrol_t write_re = entry->write_re; 88 93 Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; 89 Tcontext_t front_end_id = entry->front_end_id;90 Tcontext_t context_id = entry->context_id;91 94 92 95 // if state is ok, when write flags in the SR regsiters … … 173 176 can_retire [x] = false; 174 177 } 178 179 bypass = ((state == ROB_END ) or 180 (state == ROB_STORE_OK ) or 181 (state == ROB_STORE_KO ) or 182 (state == ROB_STORE_OK_WAIT_END) or 183 (state == ROB_STORE_KO_WAIT_END)); 184 185 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); 186 187 // if future event, don't update after this event 188 if (reg_EVENT_STOP [front_end_id][context_id] and 189 (reg_EVENT_PACKET [entry->front_end_id][entry->context_id] == packet)) 190 bypass = false; 175 191 } 176 192 177 193 // Retire "in-order" 178 can_retire [x] &= retire_val [x][y];194 can_retire [x] &= (retire_val [x][y] or bypass); 179 195 } 180 196 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
r118 r122 28 28 // =================================================================== 29 29 { 30 log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]"); 31 32 // Store instruction comming Out Of Order in Load Store Unit. 33 // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB 34 35 Tcontrol_t val = false; 36 uint32_t num_bank = reg_NUM_BANK_HEAD; 37 38 if (not _rob[num_bank].empty()) 30 uint32_t nb_scan_bank = 0; // last scan bank 31 bool can_continue = true; 32 33 // for each reexecute_port 34 for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) 39 35 { 40 log_printf(TRACE,Commit_unit,FUNCTION," * ROB is not empty"); 41 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank); 42 43 entry_t * entry = _rob [num_bank].front(); 44 rob_state_t state = entry->state; 45 46 // Test state 47 val = ((state == ROB_STORE_HEAD_OK) or 48 (state == ROB_STORE_HEAD_KO)); 49 50 log_printf(TRACE,Commit_unit,FUNCTION," * val : %d",val); 51 if (val) 36 log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i); 37 38 // Store instruction comming Out Of Order in Load Store Unit. 39 // Must be executed in no speculative mode. Also, send a signal when an Store is in head of ROB 40 41 Tcontrol_t val = false; 42 43 for (uint32_t j=nb_scan_bank; j<_param->_nb_bank; j++) 52 44 { 53 Tpacket_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank); 54 55 log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",packet_id); 56 57 // Reexecute store 58 if (_param->_have_port_context_id) 59 PORT_WRITE(out_REEXECUTE_CONTEXT_ID [0], entry->context_id ); 60 if (_param->_have_port_front_end_id) 61 PORT_WRITE(out_REEXECUTE_FRONT_END_ID [0], entry->front_end_id ); 62 if (_param->_have_port_rob_ptr ) 63 PORT_WRITE(out_REEXECUTE_PACKET_ID [0], packet_id ); 64 PORT_WRITE(out_REEXECUTE_TYPE [0], entry->type ); 65 PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [0], entry->store_queue_ptr_write); 66 PORT_WRITE(out_REEXECUTE_OPERATION [0], (state == ROB_STORE_HEAD_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO); 67 } 45 nb_scan_bank ++; 46 47 // translate bank number 48 uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank; 49 50 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank); 51 52 // Test if the head of rob is not empty 53 if (not _rob[num_bank].empty()) 54 { 55 log_printf(TRACE,Commit_unit,FUNCTION," * ROB is not empty"); 56 57 // Read state 58 entry_t * entry = _rob [num_bank].front(); 59 rob_state_t state = entry->state; 60 61 // Test state 62 // * store is ko, send signal at store_queue 63 // * store_is ok, test if in head 64 // val = (((state == ROB_STORE_OK) and (num_bank == (reg_NUM_BANK_HEAD))) or 65 // (state == ROB_STORE_KO) or 66 // (state == ROB_STORE_EVENT) 67 // ); 68 val = (((state == ROB_STORE_OK) and can_continue) or 69 (state == ROB_STORE_KO) or 70 (state == ROB_STORE_EVENT) 71 ); 72 73 can_continue &= ((state == ROB_STORE_OK ) or 74 (state == ROB_STORE_OK_WAIT_END ) or 75 (state == ROB_END_OK_SPECULATIVE) or 76 (state == ROB_END_OK ) or 77 (state == ROB_END ) 78 ); 79 80 log_printf(TRACE,Commit_unit,FUNCTION," * val : %d",val); 81 82 if (val) 83 { 84 internal_REEXECUTE_NUM_BANK [i] = num_bank; 85 86 Tpacket_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank); 87 88 log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",packet_id); 89 90 // Reexecute store 91 if (_param->_have_port_context_id) 92 PORT_WRITE(out_REEXECUTE_CONTEXT_ID [i], entry->context_id ); 93 if (_param->_have_port_front_end_id) 94 PORT_WRITE(out_REEXECUTE_FRONT_END_ID [i], entry->front_end_id ); 95 if (_param->_have_port_rob_ptr ) 96 PORT_WRITE(out_REEXECUTE_PACKET_ID [i], packet_id ); 97 PORT_WRITE(out_REEXECUTE_TYPE [i], entry->type ); 98 PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i], entry->store_queue_ptr_write); 99 PORT_WRITE(out_REEXECUTE_OPERATION [i], (state == ROB_STORE_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO); 100 101 break; // Stop scan 102 } 103 } 104 } 105 106 internal_REEXECUTE_VAL [i] = val; 107 PORT_WRITE(out_REEXECUTE_VAL[i], internal_REEXECUTE_VAL [i]); 68 108 } 69 70 internal_REEXECUTE_VAL [0] = val;71 internal_REEXECUTE_NUM_BANK [0] = num_bank;72 73 PORT_WRITE(out_REEXECUTE_VAL[0], internal_REEXECUTE_VAL [0]);74 109 } 75 110 … … 79 114 { 80 115 // Branchement must be send at the prediction unit 81 uint32_t nb_scan_bank = 0; 116 117 uint32_t nb_scan_bank = 0; // last scan bank 82 118 83 119 // for each port, find a valid branchement. 84 120 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 85 121 { 122 log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); 123 86 124 Tcontrol_t val = false; 87 125 … … 92 130 // translate bank number 93 131 uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank; 132 133 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",num_bank); 94 134 135 // Test if in this bank, they have an instruction 95 136 if (not _rob [num_bank].empty()) 96 137 { 138 log_printf(TRACE,Commit_unit,FUNCTION," * not empty"); 139 140 // Read information 97 141 entry_t * entry = _rob [num_bank].front(); 98 142 rob_state_t state = entry->state; 99 100 if (state == ROB_BRANCH_COMPLETE) 143 Tcontext_t front_end_id = entry->front_end_id; 144 Tcontext_t context_id = entry->context_id ; 145 146 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 147 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 148 149 // don't complete a branch when rob manage an present event 150 if ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_NO_EVENT) and 151 (state == ROB_BRANCH_COMPLETE)) 101 152 { 102 val = true; 103 153 log_printf(TRACE,Commit_unit,FUNCTION," * find !!!"); 154 155 // test if have a future event (stop is set) 156 log_printf(TRACE,Commit_unit,FUNCTION," * reg_EVENT_STOP : %d",reg_EVENT_STOP [front_end_id][context_id]); 157 158 if (reg_EVENT_STOP [front_end_id][context_id]) 159 { 160 // Have future event, can complete the branch if the event is most speculative than this branchement 161 // Also, need compare packet_id (is order) 162 163 uint32_t _top = ((_rob[reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); 164 uint32_t _old = reg_EVENT_PACKET [front_end_id][context_id]; 165 uint32_t _new = ((entry->ptr << _param->_shift_num_slot) | num_bank); 166 167 // log_printf(TRACE,Commit_unit,FUNCTION," * _top : %d",_top); 168 // log_printf(TRACE,Commit_unit,FUNCTION," * _old (before) : %d",_old); 169 // log_printf(TRACE,Commit_unit,FUNCTION," * _new (before) : %d",_new); 170 171 if (_old < _top) _old = _old+_param->_size_queue; 172 if (_new < _top) _new = _new+_param->_size_queue; 173 if (_new < _old) val = true; 174 175 // log_printf(TRACE,Commit_unit,FUNCTION," * _old (after ) : %d",_old); 176 // log_printf(TRACE,Commit_unit,FUNCTION," * _new (after ) : %d",_new); 177 178 } 179 else 180 val = true; 181 182 log_printf(TRACE,Commit_unit,FUNCTION," * val : %d",val); 183 184 if (val) 185 { 186 // Have an valid branchement to complete 104 187 internal_BRANCH_COMPLETE_NUM_BANK [i] = num_bank; 105 188 189 if (_param->_have_port_front_end_id) 190 PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], front_end_id ); 106 191 if (_param->_have_port_context_id) 107 PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id ); 108 if (_param->_have_port_front_end_id) 109 PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id ); 192 PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], context_id ); 110 193 if (_param->_have_port_depth) 111 194 PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); … … 114 197 PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE [i], entry->no_sequence ); 115 198 116 break; 199 break; // Stop scan 200 } 117 201 } 118 202 } … … 131 215 internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD; 132 216 217 // Test if have an instruction 133 218 if (not _rob[internal_UPDATE_NUM_BANK].empty()) 134 219 { … … 138 223 entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); 139 224 225 // Test state 226 // Update if exception or load miss 140 227 switch (entry->state) 141 228 { … … 208 295 for (uint32_t i=0; i<_param->_nb_front_end; i++) 209 296 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 210 PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], reg_EVENT_STATE[i][j]); 297 { 298 // bool flush = reg_EVENT_FLUSH [i][j]; 299 bool flush = (((reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_EVENT) or 300 (reg_EVENT_STATE [i][j] == COMMIT_EVENT_STATE_WAIT_DECOD)) and 301 not reg_EVENT_CAN_RESTART[i][j]); 302 303 PORT_WRITE(out_RETIRE_EVENT_STATE [i][j], commit_event_state_to_event_state(reg_EVENT_STATE[i][j])); 304 PORT_WRITE(out_RETIRE_EVENT_FLUSH [i][j], flush); 305 PORT_WRITE(out_RETIRE_EVENT_STOP [i][j], reg_EVENT_STOP [i][j]); 306 } 211 307 212 308 log_end(Commit_unit,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r121 r122 16 16 namespace ooo_engine { 17 17 namespace commit_unit { 18 19 18 20 19 #undef FUNCTION … … 41 40 reg_NUM_BANK_HEAD = 0; 42 41 reg_NUM_BANK_TAIL = 0; 42 reg_NUM_PTR_TAIL = 0; 43 43 44 44 // Reset counter … … 51 51 reg_NB_INST_COMMIT_MEM [i][j] = 0; 52 52 53 reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT;54 53 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; 54 // reg_EVENT_FLUSH [i][j] = false; 55 55 reg_EVENT_STOP [i][j] = false; 56 reg_EVENT_LAST [i][j] = false; 56 57 57 58 // reg_PC_PREVIOUS [i][j] = (0x100-4)>>2; … … 80 81 for (uint32_t i=0; i<_param->_nb_front_end; i++) 81 82 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 82 switch (reg_EVENT_STATE [i][j]) 83 { 84 case EVENT_STATE_EVENT : 83 { 84 // Test if can_restart : (can_restart is to signal at the state than the decod_queue is empty) 85 // * no previous can_restart (trap for one) 86 // * and decod_queue is empty 87 // * and have an event or have a futur event 88 if (not reg_EVENT_CAN_RESTART [i][j] and 89 (PORT_READ(in_NB_INST_DECOD_ALL [i][j]) == 0) and 90 (reg_EVENT_STOP [i][j] or (reg_EVENT_STATE [i][j] != COMMIT_EVENT_STATE_NO_EVENT))) 91 reg_EVENT_CAN_RESTART [i][j] = true; 92 93 // Test event state 94 switch (reg_EVENT_STATE [i][j]) 85 95 { 86 if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) 87 reg_EVENT_STATE [i][j] = EVENT_STATE_WAITEND ; 88 break; 96 case COMMIT_EVENT_STATE_EVENT : 97 { 98 // Have an event, test if all composant have ack 99 if (internal_RETIRE_EVENT_VAL [i][j] and in_RETIRE_EVENT_ACK [i][j]) 100 { 101 // A minor optimisation : test if wait_decod is previously empty. 102 if (not reg_EVENT_CAN_RESTART [i][j]) 103 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_DECOD; 104 else 105 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; 106 } 107 108 break; 109 } 110 case COMMIT_EVENT_STATE_WAIT_DECOD : 111 { 112 // Wait flush of decod_queue. 113 // Test if can restart now 114 if (reg_EVENT_CAN_RESTART [i][j]) 115 { 116 //reg_EVENT_FLUSH [i][j] = false; 117 118 // A minor optimisation : test if the last element is already retire 119 if (not reg_EVENT_LAST [i][j]) 120 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_WAIT_END; 121 else 122 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END; 123 } 124 break; 125 } 126 case COMMIT_EVENT_STATE_WAIT_END : 127 { 128 // Wait the flush of Re Order Buffer. 129 // Test if the last element is retire 130 if (reg_EVENT_LAST [i][j]) 131 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_END ; 132 133 break; 134 } 135 case COMMIT_EVENT_STATE_END : 136 { 137 // Just one cycle 138 139 // flush of re order buffer is finish 140 reg_EVENT_STATE [i][j] = COMMIT_EVENT_STATE_NO_EVENT; 141 reg_EVENT_LAST [i][j] = false; 142 break; 143 } 144 //case COMMIT_EVENT_STATE_NO_EVENT : 145 default : break; 89 146 } 90 case EVENT_STATE_WAITEND : 147 } 148 149 // =================================================================== 150 // =====[ INSERT ]==================================================== 151 // =================================================================== 152 { 153 // variable to count instruction insert 154 uint32_t nb_insert = 0; 155 156 for (uint32_t i=0; i<_param->_nb_bank; i++) 157 { 158 // compute first bank number 159 uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; 160 161 if (internal_BANK_INSERT_VAL [num_bank]) 91 162 { 92 Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j]; 93 if (nb_inst_all == 0) 163 // get rename unit source and instruction. 164 uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank]; 165 uint32_t y = internal_BANK_INSERT_NUM_INST [num_bank]; 166 167 // Test if an instruction is valid 168 // (all in_order insert combinatory is in rename_unit ) 169 if (PORT_READ(in_INSERT_VAL [x][y])) 94 170 { 95 reg_EVENT_STATE [i][j] = EVENT_STATE_END; 96 reg_EVENT_FLUSH [i][j] = false; 97 //reg_EVENT_STOP [i][j] = false; 171 log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); 172 173 // get information 174 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; 175 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; 176 Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); 177 Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); 178 bool is_store = is_operation_memory_store(operation); 179 180 Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); 181 Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); 182 183 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 184 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); 185 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); 186 log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); 187 log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); 188 189 // Create new entry and write information 190 entry_t * entry = new entry_t; 191 uint32_t ptr = reg_BANK_PTR [num_bank]; 192 193 entry->ptr = ptr; 194 entry->front_end_id = front_end_id; 195 entry->context_id = context_id ; 196 entry->rename_unit_id = x; 197 entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; 198 entry->type = type; 199 entry->operation = operation; 200 entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); 201 // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 202 entry->exception = exception; 203 entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); 204 entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute); 205 entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute); 206 entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); 207 entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; 208 #ifdef DEBUG 209 entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); 210 entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); 211 entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); 212 entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); 213 entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); 214 entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); 215 entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); 216 entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); 217 entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); 218 #endif 219 entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); 220 entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); 221 entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); 222 entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); 223 entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); 224 entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); 225 entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); 226 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 227 entry->no_sequence = type == TYPE_BRANCH; 228 entry->speculative = true; 229 #ifdef DEBUG 230 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 231 #endif 232 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); 233 #ifdef DEBUG 234 entry->cycle_rob_in = simulation_cycle(); 235 entry->cycle_commit = simulation_cycle(); 236 #endif 237 238 // Test if exception : 239 // * yes : no execute instruction, wait ROB Head 240 // * no : test if no_execute (== instruction is flushed) 241 // else test type 242 // * BRANCH : l.j -> branch is ended 243 // other -> wait the execution end of branchment 244 // * MEMORY : store -> wait store is at head of ROB 245 // other -> wait end of instruction 246 // * OTHER 247 248 { 249 if (exception == EXCEPTION_NONE) 250 { 251 // no_execute : l.j, l.nop, l.rfe 252 253 log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); 254 255 switch (type) 256 { 257 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} 258 case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_END_OK:ROB_OTHER_WAIT_END); break;} 259 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 260 } 261 } 262 else 263 { 264 // Have an exception : wait head of ROB 265 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 266 267 entry->state = ROB_END_EXCEPTION_WAIT_HEAD; 268 } 269 } 270 271 #ifdef STATISTICS 272 if (usage_is_set(_usage,USE_STATISTICS)) 273 (*_stat_nb_inst_insert [x]) ++; 274 #endif 275 276 // Push entry in rob 277 _rob[num_bank].push_back(entry); 278 279 // Update counter and pointer 280 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; 281 if (type == TYPE_MEMORY) 282 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; 283 284 285 // flush = present event or future event. 286 // * present event = don't can restart 287 288 // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 289 290 // bool flush = (((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 291 // (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or 292 // (reg_EVENT_STOP [front_end_id][context_id])); 293 294 // New instruction from decod_queue. Flush if : 295 // * future event (instruction don't need execute because they are a previous event (miss load/branch or exception)) 296 // * or present_event 297 // * and not can_restart (previous empty decod queue), because between the event_stop (branch_complete) and the state event (miss in head), many cycle is occured. 298 bool flush = ((// present event 299 ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 300 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD)) or 301 // futur event 302 reg_EVENT_STOP [front_end_id][context_id]) 303 // can't restart 304 and not reg_EVENT_CAN_RESTART[front_end_id][context_id] 305 ); 306 307 if (flush) 308 { 309 // A new invalid instruction is push in rob -> new last instruction 310 reg_EVENT_LAST [front_end_id][context_id] = false; 311 reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = num_bank; 312 reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = ptr; 313 } 314 315 // Update pointer 316 reg_NUM_PTR_TAIL = ptr; 317 reg_BANK_PTR [num_bank] = (reg_BANK_PTR [num_bank]+1)%_param->_size_bank; 318 nb_insert ++; 98 319 } 99 break;100 320 } 101 case EVENT_STATE_END : 102 { 103 reg_EVENT_STATE [i][j] = EVENT_STATE_NO_EVENT; 104 break; 105 } 106 // case EVENT_STATE_NO_EVENT : 107 default : break; 108 } 109 110 // =================================================================== 111 // =====[ INSERT ]==================================================== 112 // =================================================================== 113 for (uint32_t i=0; i<_param->_nb_bank; i++) 114 if (internal_BANK_INSERT_VAL [i]) 115 { 116 // get rename unit source and instruction. 117 uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; 118 uint32_t y = internal_BANK_INSERT_NUM_INST [i]; 119 120 if (PORT_READ(in_INSERT_VAL [x][y])) 121 { 122 log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); 123 124 // get information 125 Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; 126 Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; 127 Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); 128 Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); 129 bool is_store = is_operation_memory_store(operation); 130 131 Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); 132 Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); 133 134 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 135 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); 136 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); 137 log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); 138 log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); 139 140 // Create new entry. 141 entry_t * entry = new entry_t; 142 143 entry->ptr = reg_BANK_PTR [i]; 144 entry->front_end_id = front_end_id; 145 entry->context_id = context_id ; 146 entry->rename_unit_id = x; 147 entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; 148 entry->type = type; 149 entry->operation = operation; 150 entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); 151 // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 152 entry->exception = exception; 153 entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); 154 entry->use_store_queue = (type == TYPE_MEMORY) and ( is_store) and (not no_execute); 155 entry->use_load_queue = (type == TYPE_MEMORY) and (not is_store) and (not no_execute); 156 entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); 157 entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; 158 #ifdef DEBUG 159 entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); 160 entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); 161 entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); 162 entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); 163 entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); 164 entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); 165 entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); 166 entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); 167 entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); 168 #endif 169 entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); 170 entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); 171 entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); 172 entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); 173 entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); 174 entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); 175 entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); 176 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 177 entry->no_sequence = type == TYPE_BRANCH; 178 entry->speculative = true; 179 #ifdef DEBUG 180 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 181 #endif 182 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); 183 #ifdef DEBUG 184 entry->cycle_rob_in = simulation_cycle(); 185 entry->cycle_commit = simulation_cycle(); 186 #endif 187 188 // Test if exception : 189 // * yes : no execute instruction, wait ROB Head 190 // * no : test type 191 // * BRANCH : l.j -> branch is ended 192 // other -> wait the execution end of branchment 193 // * MEMORY : store -> wait store is at head of ROB 194 // other -> wait end of instruction 195 // * OTHER 196 197 // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 198 199 // log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 200 201 // if (flush) 202 // { 203 // entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute 204 // } 205 // else 206 { 207 if (exception == EXCEPTION_NONE) 208 { 209 // no_execute : l.j, l.nop, l.rfe 210 211 log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); 212 213 switch (type) 214 { 215 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} 216 case TYPE_MEMORY : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:(entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END); break;} 217 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 218 } 219 } 220 else 221 { 222 // Have an exception : wait head of ROB 223 224 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 225 226 entry->state = ROB_END_EXCEPTION_WAIT_HEAD; 227 } 228 } 229 230 #ifdef STATISTICS 231 if (usage_is_set(_usage,USE_STATISTICS)) 232 (*_stat_nb_inst_insert [x]) ++; 233 #endif 234 235 // Push in rob 236 _rob[i].push_back(entry); 237 238 // Update counter and pointer 239 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; 240 if (type == TYPE_MEMORY) 241 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; 242 243 reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank; 244 reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank; 245 } 246 } 321 } 322 // Update pointer 323 reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+nb_insert)%_param->_nb_bank; 324 } 247 325 248 326 // =================================================================== … … 255 333 #endif 256 334 335 // For each commit instruction ... 257 336 for (uint32_t i=0; i<_param->_nb_bank; i++) 258 337 for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) 338 // ... test if an instruction have finish this execution 259 339 if (internal_BANK_COMMIT_VAL [i][j]) 260 340 { 261 // An instruction is executed. Change state of this instruction 262 341 // An instruction is executed -> Change state of this instruction 342 343 // Get information 263 344 uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; 264 345 346 // Test if instruction is valid and is enable 347 // (can be disable if this instruction is reexecute) 265 348 if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) 266 349 { … … 278 361 279 362 //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); 280 //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); 363 Ttype_t type = entry->type; 364 Tcontrol_t no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); 365 366 #if 0 367 if ((type == TYPE_MEMORY) and no_sequence) 368 continue; 369 #endif 370 281 371 Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); 282 372 … … 286 376 287 377 // change state : test exception_use 288 // * test if exception : exception and mask289 378 290 379 bool have_exception = false; 291 380 bool have_miss_speculation = false; 292 381 382 // Test if have an exception ... 293 383 if (exception != EXCEPTION_NONE) 294 384 { 295 // Test if the instruction is a load and is a miss speculation (load is commit, but they have an dependence with a previous store) 385 // Test if the instruction is a load and is a miss speculation 386 // (load is commit, but they have an dependence with a previous store -> need restart pipeline) 387 296 388 have_miss_speculation = (exception == EXCEPTION_MEMORY_MISS_SPECULATION); 297 389 390 // * Test if the exception generated can be trap by this exception 298 391 switch (entry->exception_use) 299 392 { … … 327 420 } 328 421 422 // Next state depends of previous state 329 423 switch (state) 330 424 { 331 // Branch ... 332 case ROB_BRANCH_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:ROB_BRANCH_COMPLETE; break;} 333 // Store KO 334 case ROB_EVENT_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 335 // Store OK, Load and other instruction 336 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} 425 // Branch : if no exception, the branchement can be completed 426 case ROB_BRANCH_WAIT_END : 427 { 428 if (not have_exception) 429 state = ROB_BRANCH_COMPLETE; 430 else 431 state = ROB_END_EXCEPTION_WAIT_HEAD; 432 break; 433 } 434 // Previous event -> set state as execute 435 case ROB_STORE_KO_WAIT_END : 436 case ROB_EVENT_WAIT_END : 437 { 438 state = ROB_END_KO_SPECULATIVE; 439 break; 440 } 441 // No previous event - Load and other instruction 442 case ROB_STORE_OK_WAIT_END : 443 case ROB_OTHER_WAIT_END : 444 { 445 if (not have_exception) 446 { 447 if (not have_miss_speculation) 448 state = ROB_END_OK_SPECULATIVE; 449 else 450 state = ROB_END_LOAD_MISS_SPECULATIVE; 451 } 452 else 453 state = ROB_END_EXCEPTION_WAIT_HEAD; 454 break; 455 } 456 case ROB_STORE_WAIT_END_OK : 457 { 458 if (not have_exception) 459 state = ROB_STORE_OK; 460 else 461 state = ROB_STORE_EVENT; 462 break; 463 } 464 case ROB_STORE_WAIT_END_KO : 465 { 466 // if (not have_exception) 467 state = ROB_STORE_KO; 468 // else 469 // state = ROB_END_EXCEPTION_WAIT_HEAD; 470 break; 471 } 472 473 337 474 default : 338 475 { … … 342 479 } 343 480 344 if ((have_exception or have_miss_speculation) and 345 (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) 346 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 347 348 // update Re Order Buffer 481 // Commit an instruction ... 482 // Test if have an event (miss_speculation or exception) and not manage a previous event 483 // if yes, this instruction would modify state machine. Also stop Re Order Buffer 484 485 // bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id]; 486 bool flush = ((reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_EVENT) or 487 (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or 488 (reg_EVENT_STATE [entry->front_end_id][entry->context_id] == COMMIT_EVENT_STATE_WAIT_END)); 489 490 if ((have_exception or have_miss_speculation) and (not flush)) 491 { 492 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | i); 493 494 // test have a previous event detected (event_stop = 1) 495 // if yes, test if the actual event if "before (in order)" that the previous event 496 if (reg_EVENT_STOP [entry->front_end_id][entry->context_id]) 497 { 498 // Compare packet_id (by construction instruction is insert in order by increase packet_id) 499 500 uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); 501 uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id]; 502 uint32_t _new = packet; 503 if (_old < _top) _old = _old+_param->_size_queue; 504 if (_new < _top) _new = _new+_param->_size_queue; 505 if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 506 } 507 else 508 reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 509 510 // have an error, stop issue instruction 511 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 512 // reg_EVENT_NUM_BANK [entry->front_end_id][entry->context_id] = i; 513 // reg_EVENT_NUM_PTR [entry->front_end_id][entry->context_id] = entry->ptr; 514 515 // reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; 516 reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 517 reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; 518 } 519 520 // Update Re Order Buffer 349 521 entry->state = state; 350 522 entry->exception = exception; 351 523 entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); 352 entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]);524 entry->no_sequence = no_sequence; 353 525 // jalr, jr : address_dest is in register 354 if (( entry->type == TYPE_BRANCH) and526 if (( type == TYPE_BRANCH) and 355 527 (entry->operation == OPERATION_BRANCH_L_JALR) and 356 528 (entry->read_rb)) … … 358 530 359 531 #ifdef DEBUG 360 entry->cycle_commit = simulation_cycle(); 532 entry->load_data = PORT_READ(in_COMMIT_ADDRESS [x]); 533 entry->cycle_commit = simulation_cycle(); 361 534 #endif 362 535 } … … 368 541 for (uint32_t i=0; i<_param->_nb_bank; i++) 369 542 { 543 // Compute bank number 370 544 uint32_t num_bank = (internal_BANK_RETIRE_HEAD+i)%_param->_nb_bank; 371 545 546 // Test if have an request 372 547 if (internal_BANK_RETIRE_VAL [num_bank]) 373 548 { 549 // Take num instruction 374 550 uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank]; 375 551 uint32_t y = internal_BANK_RETIRE_NUM_INST [num_bank]; … … 382 558 throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); 383 559 #endif 560 561 562 #ifdef STATISTICS 563 if (usage_is_set(_usage,USE_STATISTICS)) 564 (*_stat_nb_inst_retire [x]) ++; 384 565 385 entry_t * entry = _rob [num_bank].front(); 386 rob_state_t state = entry->state; 566 #endif 387 567 388 Tcontext_t front_end_id = entry->front_end_id; 389 Tcontext_t context_id = entry->context_id ; 390 uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; 391 Ttype_t type = entry->type ; 392 bool retire_ok = false; 393 394 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); 395 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 396 log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",((entry->ptr << _param->_shift_num_slot) | num_bank)); 397 log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); 398 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); 399 log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); 400 401 if ((state == ROB_END_OK ) or 402 // (state == ROB_END_KO ) or 403 (state == ROB_END_BRANCH_MISS) or 404 (state == ROB_END_LOAD_MISS )// or 405 // (state == ROB_END_MISS ) or 406 // (state == ROB_END_EXCEPTION ) 407 ) 408 { 409 log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); 410 411 retire_ok = true; 412 413 // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; 414 reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; 415 reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; 416 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 417 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 418 419 // if (entry->address_next != reg_PC_NEXT [front_end_id][context_id]) 420 // throw ERRORMORPHEO(FUNCTION,toString(_("Retire : Instruction's address_next (%.8x) is different of commit_unit's address_next (%.8x)"),entry->address_next,reg_PC_NEXT [front_end_id][context_id])); 421 } 422 423 if ((state == ROB_END_BRANCH_MISS) or 424 (state == ROB_END_LOAD_MISS)) 425 { 426 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 427 reg_EVENT_FLUSH [front_end_id][context_id] = true; 428 reg_EVENT_STOP [front_end_id][context_id] = false; 429 } 430 431 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) 432 // log file 433 instruction_log_file [num_thread] 434 << "[" << simulation_cycle() << "] " 435 << std::hex 436 << (entry->address<<2) << " (" << (entry->address) << ") " 437 << std::dec 438 << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] " 439 << "{" << ((retire_ok)?" OK ":"!KO!") << "} " 440 << std::endl; 441 #endif 442 443 // Update nb_inst 444 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; 445 if (type == TYPE_MEMORY) 446 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 447 448 reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; 449 450 delete entry; 451 _rob [num_bank].pop_front(); 452 453 // Transaction on retire interface : reset watch dog timer. 454 _nb_cycle_idle [front_end_id][context_id] = 0; 455 456 // Increase stop condition 457 if (retire_ok) 458 _simulation_nb_instruction_commited [num_thread] ++; 459 460 #ifdef STATISTICS 461 if (usage_is_set(_usage,USE_STATISTICS)) 462 { 463 (*_stat_nb_inst_retire [x]) ++; 464 465 if (retire_ok) 466 { 467 (*_stat_nb_inst_retire_ok [num_thread]) ++; 468 (*_stat_nb_inst_type [type] ) ++; 469 } 470 else 471 (*_stat_nb_inst_retire_ko [num_thread]) ++; 472 } 473 #endif 568 // Read information 569 entry_t * entry = _rob [num_bank].front(); 570 571 entry->state_old = entry->state; 572 entry->state = ROB_END; 474 573 } 475 574 } 476 575 576 for (uint32_t i=0; i<_param->_nb_bank; i++) 577 { 578 // Compute bank number 579 bool can_continue = false; 580 uint32_t num_bank = reg_NUM_BANK_HEAD; 581 582 if (not _rob [num_bank].empty ()) 583 { 584 entry_t * entry = _rob [num_bank].front(); 585 586 if (entry->state == ROB_END) 587 { 588 log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE_ROB [%d]",num_bank); 589 590 can_continue = true; 591 592 Tcontext_t front_end_id = entry->front_end_id; 593 Tcontext_t context_id = entry->context_id ; 594 uint32_t num_thread = _param->_translate_num_context_to_num_thread [front_end_id][context_id]; 595 rob_state_t state = entry->state_old; 596 Ttype_t type = entry->type ; 597 bool retire_ok = false; 598 uint32_t packet_id = ((entry->ptr << _param->_shift_num_slot) | num_bank); 599 600 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id ); 601 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 602 log_printf(TRACE,Commit_unit,FUNCTION," * rob_ptr : %d",packet_id ); 603 log_printf(TRACE,Commit_unit,FUNCTION," * num_thread : %d",num_thread ); 604 log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); 605 log_printf(TRACE,Commit_unit,FUNCTION," * state : %s",toString(state).c_str()); 606 607 // Test if the instruction is valid 608 // (BRANCH_MISS = instruction branch is valid, but have make an invalid prediction) 609 // (LOAD_MISS = instruction load is valid, but have make an invalid result) 610 if ((state == ROB_END_OK ) or 611 // (state == ROB_END_KO ) or 612 (state == ROB_END_BRANCH_MISS) or 613 (state == ROB_END_LOAD_MISS )// or 614 // (state == ROB_END_MISS ) or 615 // (state == ROB_END_EXCEPTION ) 616 ) 617 { 618 log_printf(TRACE,Commit_unit,FUNCTION," * retire_ok"); 619 620 retire_ok = true; 621 622 // Update PC information 623 // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; 624 reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; 625 reg_PC_CURRENT_IS_DS [front_end_id][context_id] = type == TYPE_BRANCH; 626 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 627 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 628 } 629 630 // Test if have an event 631 if ((state == ROB_END_BRANCH_MISS) or 632 (state == ROB_END_LOAD_MISS)) 633 { 634 reg_EVENT_STATE [front_end_id][context_id] = COMMIT_EVENT_STATE_EVENT; 635 // reg_EVENT_FLUSH [front_end_id][context_id] = true; 636 reg_EVENT_STOP [front_end_id][context_id] = false; // instruction flow can continue 637 // reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; 638 reg_EVENT_LAST [front_end_id][context_id] = false; 639 // it the head ! 640 reg_EVENT_PACKET [front_end_id][context_id] = packet_id; 641 642 // If event is an load_miss, many instruction can be inserted. 643 // -> new last instruction 644 if (state == ROB_END_LOAD_MISS) 645 { 646 reg_EVENT_CAN_RESTART [front_end_id][context_id] = false; 647 648 reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 649 reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] = reg_NUM_PTR_TAIL; 650 } 651 } 652 653 // Test if this instruction is the last instruction of an event 654 // * need event 655 // * packet id = last packet id 656 if ((reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and 657 (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank ) and 658 (reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] == entry->ptr )) 659 reg_EVENT_LAST [front_end_id][context_id] = true; 660 661 // Update nb_inst 662 reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; 663 if (type == TYPE_MEMORY) 664 reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; 665 666 // Update pointer 667 reg_NUM_BANK_HEAD = (num_bank+1)%_param->_nb_bank; 668 669 // Remove entry 670 delete entry; 671 _rob [num_bank].pop_front(); 672 673 // Reset watch dog timer because have transaction on retire interface 674 _nb_cycle_idle [front_end_id][context_id] = 0; 675 676 // Increase stop condition 677 if (retire_ok) 678 _simulation_nb_instruction_commited [num_thread] ++; 679 680 #ifdef STATISTICS 681 if (usage_is_set(_usage,USE_STATISTICS)) 682 { 683 if (retire_ok) 684 { 685 (*_stat_nb_inst_retire_ok [num_thread]) ++; 686 (*_stat_nb_inst_type [type] ) ++; 687 } 688 else 689 (*_stat_nb_inst_retire_ko [num_thread]) ++; 690 } 691 #endif 692 693 #if defined(DEBUG) and defined(DEBUG_Commit_unit) and (DEBUG_Commit_unit == true) 694 { 695 // log file 696 instruction_log_file [num_thread] 697 << "[" << simulation_cycle() << "] " 698 << std::hex 699 << (entry->address<<2) << " (" << (entry->address) << ") " 700 << std::dec 701 << "[" << entry->cycle_rob_in << ", " << entry->cycle_commit << "] " 702 << "{" << ((retire_ok)?"OK":"KO") << "} "; 703 704 if ((type == TYPE_MEMORY) and is_operation_memory_load(entry->operation)) 705 instruction_log_file [num_thread] << std::hex << entry->load_data << std::dec; 706 707 instruction_log_file [num_thread] << std::endl; 708 } 709 #endif 710 } 711 } 712 713 if (not can_continue) 714 break; // stop scan 715 } 716 477 717 // =================================================================== 478 718 // =====[ REEXECUTE ]================================================= 479 719 // =================================================================== 480 if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) 481 { 482 log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [0]"); 483 484 uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; 485 486 entry_t * entry = _rob [num_bank].front(); 487 rob_state_t state = entry->state; 488 489 switch (state) 490 { 491 case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } 492 case ROB_STORE_HEAD_KO : {state = ROB_EVENT_WAIT_END; break; } 493 default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} 494 } 495 496 entry->state = state; 497 } 498 720 // Test if have an reexecute instruction (an store in head of rob) 721 for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) 722 if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) 723 { 724 log_printf(TRACE,Commit_unit,FUNCTION," * REEXECUTE [%d]",i); 725 726 uint32_t num_bank = internal_REEXECUTE_NUM_BANK [i]; 727 728 entry_t * entry = _rob [num_bank].front(); 729 rob_state_t state = entry->state; 730 731 // Change state 732 switch (state) 733 { 734 case ROB_STORE_OK : {state = ROB_STORE_OK_WAIT_END; break; } 735 case ROB_STORE_KO : {state = ROB_STORE_KO_WAIT_END; break; } 736 case ROB_STORE_EVENT : {state = ROB_EVENT_WAIT_END; break; } 737 default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} 738 } 739 740 entry->state = state; 741 } 742 499 743 // =================================================================== 500 744 // =====[ BRANCH_COMPLETE ]=========================================== 501 745 // =================================================================== 502 746 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 747 // Test if the prediction_unit have accept the branch complete transaction 503 748 if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) 504 749 { 505 750 log_printf(TRACE,Commit_unit,FUNCTION," * BRANCH_COMPLETE [%d]",i); 506 log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])); 507 751 752 // Read information 508 753 uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; 509 754 … … 516 761 #endif 517 762 Tcontrol_t miss = PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]); 763 764 log_printf(TRACE,Commit_unit,FUNCTION," * miss_prediction : %d",miss); 518 765 519 766 entry->state = (miss)?ROB_END_BRANCH_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE; 520 521 if (miss and (reg_EVENT_FLUSH [entry->front_end_id][entry->context_id] == 0)) 522 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 523 524 525 // entry->state = ROB_END_OK_SPECULATIVE; 767 768 // bool flush = reg_EVENT_FLUSH [entry->front_end_id][entry->context_id]; 769 770 // Branch_complete can be execute if 771 // * no present event 772 // * futur event and most not speculative that the event 773 774 // Also, test if in this cycle, they have not an most recently event !!! 775 if (miss) 776 { 777 uint32_t packet = ((entry->ptr << _param->_shift_num_slot) | num_bank); 778 779 // test if this packet is before previous event 780 if (reg_EVENT_STOP [entry->front_end_id][entry->context_id]) 781 { 782 uint32_t _top = ((_rob[ reg_NUM_BANK_HEAD].front()->ptr << _param->_shift_num_slot) | reg_NUM_BANK_HEAD); 783 uint32_t _old = reg_EVENT_PACKET [entry->front_end_id][entry->context_id]; 784 uint32_t _new = packet; 785 if (_old < _top) _old = _old+_param->_size_queue; 786 if (_new < _top) _new = _new+_param->_size_queue; 787 if (_new < _old) reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 788 } 789 else 790 reg_EVENT_PACKET [entry->front_end_id][entry->context_id] = packet; 791 792 // In all case, stop instruction flow 793 reg_EVENT_STOP [entry->front_end_id][entry->context_id] = true; 794 // reg_EVENT_NUM_BANK [entry->front_end_id][entry->context_id] = num_bank; 795 // reg_EVENT_NUM_PTR [entry->front_end_id][entry->context_id] = entry->ptr; 796 797 reg_EVENT_CAN_RESTART [entry->front_end_id][entry->context_id] = false; 798 799 reg_EVENT_LAST_NUM_BANK [entry->front_end_id][entry->context_id] = ((reg_NUM_BANK_TAIL==0)?_param->_nb_bank:reg_NUM_BANK_TAIL)-1; 800 reg_EVENT_LAST_NUM_PTR [entry->front_end_id][entry->context_id] = reg_NUM_PTR_TAIL; 801 } 526 802 } 527 803 … … 529 805 // =====[ UPDATE ]==================================================== 530 806 // =================================================================== 807 // Update when exception or load_miss 531 808 if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) 532 809 { 533 810 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); 534 811 812 // Change state 535 813 entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); 536 814 … … 556 834 } 557 835 } 558 559 836 } 560 837 … … 578 855 // =====[ DEPTH - HEAD ]============================================== 579 856 // =================================================================== 580 for (uint32_t i=0; i<_param->_nb_bank; i++) 581 if (not _rob[i].empty()) 582 { 583 // Scan all instruction in windows and test if instruction is speculative 584 entry_t * entry = _rob [i].front(); 585 586 Tcontext_t front_end_id = entry->front_end_id; 587 Tcontext_t context_id = entry->context_id ; 588 rob_state_t state = entry->state; 589 Tdepth_t depth = entry->depth; 590 591 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; 592 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; 593 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); 857 858 { 859 bool EVENT_LAST [_param->_nb_front_end][_param->_max_nb_context]; 860 for (uint32_t i=0; i<_param->_nb_front_end; i++) 861 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 862 EVENT_LAST [i][j] = reg_EVENT_LAST [i][j]; 863 864 // Read all instruction of all top bank 865 for (uint32_t i=0; i<_param->_nb_bank; i++) 866 { 867 uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; 594 868 595 // is a valid instruction ? 596 // If DEPTH_CURRENT : 597 // equal at DEPTH_MIN -> not speculative 598 // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss 599 // include ]DEPTH_MIN:DEPTH_MAX] -> speculative 600 601 // All case 602 // ....... min ...X... max ....... OK 603 // ....... min ....... max ...X... KO 604 // ...X... min ....... max ....... KO 605 // ....... max ....... min ...X... OK 606 // ...X... max ....... min ....... OK 607 // ....... max ...X... min ....... KO 608 609 bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 610 bool speculative = entry->speculative and not (depth == depth_min); 611 Tcontrol_t is_valid = ((not speculative or 612 (speculative and (depth_full or // all is valid 613 ((depth_min <= depth_max)? // test if depth is overflow 614 ((depth >= depth_min) and (depth <=depth_max)): 615 ((depth >= depth_min) or (depth <=depth_max)))))) 616 and not flush); 617 618 // Tcontrol_t is_valid = ((depth == depth_min) and not flush); 619 620 log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); 621 log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); 622 log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); 623 log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); 624 log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); 625 log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); 626 log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 627 628 //------------------------------------------------------ 629 // test if instruction is miss speculative 630 //------------------------------------------------------ 631 if (not is_valid) 632 { 633 switch (state) 634 { 635 case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} 636 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 637 case ROB_END_BRANCH_MISS : 638 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 639 case ROB_END_LOAD_MISS_UPDATE : 640 case ROB_END_LOAD_MISS : 641 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 642 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO ; break;} 643 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 644 case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} 645 case ROB_END_OK : 646 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 647 case ROB_END_KO : 648 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 649 case ROB_END_EXCEPTION_UPDATE : 650 case ROB_END_EXCEPTION : 651 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 652 653 // don't change 654 case ROB_STORE_HEAD_KO : {break;} 655 case ROB_EVENT_WAIT_END : {break;} 656 case ROB_END_MISS : {break;} 657 658 // can't have miss speculation 659 case ROB_STORE_HEAD_OK : 660 default : 661 { 662 throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); 663 break; 664 } 665 } 666 } 667 668 //------------------------------------------------------ 669 // test if instruction is not speculative 670 //------------------------------------------------------ 671 entry->speculative = speculative; 672 // if (entry->depth == depth_min) 673 if (not speculative) 674 { 675 switch (state) 676 { 677 case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} 678 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 679 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 680 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} 681 default : {break;} // else, no change 682 } 683 } 684 685 //------------------------------------------------------ 686 // test if instruction is store and head 687 //------------------------------------------------------ 688 if (i == reg_NUM_BANK_HEAD) 689 { 690 switch (state) 691 { 692 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 693 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 694 default : {break;} // else, no change 695 } 696 } 697 698 entry->state = state; 699 } 700 } 701 702 // =================================================================== 703 // =====[ OTHER ]===================================================== 704 // =================================================================== 869 // Test if have an instruction 870 if (not _rob[num_bank].empty()) 871 { 872 // Scan all instruction in windows and test if instruction is speculative 873 entry_t * entry = _rob [num_bank].front(); 874 875 Tcontext_t front_end_id = entry->front_end_id; 876 Tcontext_t context_id = entry->context_id ; 877 878 // scan while last event instruction is not retire 879 if (EVENT_LAST [front_end_id][context_id] == false) 880 { 881 // Read information 882 rob_state_t state = entry->state; 883 Tdepth_t depth = entry->depth; 884 885 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; 886 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; 887 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); 888 889 // is a valid instruction ? 890 // If DEPTH_CURRENT : 891 // equal at DEPTH_MIN -> not speculative 892 // not include ]DEPTH_MIN:DEPTH_MAX] -> previous branch miss 893 // include ]DEPTH_MIN:DEPTH_MAX] -> speculative 894 895 // All case 896 // ....... min ...X... max ....... OK 897 // ....... min ....... max ...X... KO 898 // ...X... min ....... max ....... KO 899 // ....... max ....... min ...X... OK 900 // ...X... max ....... min ....... OK 901 // ....... max ...X... min ....... KO 902 903 bool flush = ((reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_EVENT) or 904 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_DECOD) or 905 (reg_EVENT_STATE [front_end_id][context_id] == COMMIT_EVENT_STATE_WAIT_END)); 906 bool speculative = entry->speculative and not (depth == depth_min); 907 Tcontrol_t is_valid = ((not speculative or 908 (speculative and (depth_full or // all is valid 909 ((depth_min <= depth_max)? // test if depth is overflow 910 ((depth >= depth_min) and (depth <=depth_max)): 911 ((depth >= depth_min) or (depth <=depth_max)))))) 912 and not flush); // no event 913 914 //Tcontrol_t is_valid = ((depth == depth_min) and not flush); 915 916 log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d] - %d",num_bank,((entry->ptr << _param->_shift_num_slot) | num_bank)); 917 918 log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); 919 log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); 920 log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); 921 log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); 922 log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); 923 log_printf(TRACE,Commit_unit,FUNCTION," * speculative : %d",speculative); 924 log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 925 926 //------------------------------------------------------ 927 // test if instruction is miss speculative 928 //------------------------------------------------------ 929 if (not is_valid) 930 { 931 // Change state 932 switch (state) 933 { 934 case ROB_BRANCH_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} 935 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 936 case ROB_END_BRANCH_MISS : 937 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 938 case ROB_END_LOAD_MISS_UPDATE : 939 case ROB_END_LOAD_MISS : 940 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 941 case ROB_STORE_OK : {state = ROB_STORE_KO ; break;} 942 case ROB_STORE_WAIT_END_OK : {state = ROB_STORE_WAIT_END_KO; break;} 943 case ROB_STORE_OK_WAIT_END : {state = ROB_STORE_KO_WAIT_END; break;} 944 case ROB_OTHER_WAIT_END : {state = ROB_EVENT_WAIT_END; break;} 945 case ROB_END_OK : 946 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 947 case ROB_END_KO : 948 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 949 case ROB_END_EXCEPTION_UPDATE : 950 case ROB_END_EXCEPTION : 951 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 952 953 // don't change state -> wait 954 case ROB_STORE_WAIT_END_KO : {break;} 955 case ROB_STORE_KO : {break;} 956 case ROB_STORE_KO_WAIT_END : {break;} 957 case ROB_STORE_EVENT : {break;} 958 case ROB_EVENT_WAIT_END : {break;} 959 case ROB_END_MISS : {break;} 960 case ROB_END : {break;} 961 962 // can't have miss speculation -> invalid state 963 default : 964 { 965 throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); 966 break; 967 } 968 } 969 } 970 971 //------------------------------------------------------ 972 // test if instruction is not speculative 973 //------------------------------------------------------ 974 entry->speculative = speculative; 975 // if (entry->depth == depth_min) 976 // test if instruction is speculative (depth != depth_min) 977 if (not speculative) 978 { 979 switch (state) 980 { 981 case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} 982 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 983 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 984 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} 985 default : {break;} // else, no change 986 } 987 } 988 989 //------------------------------------------------------ 990 // test if instruction wait head and is the top of rob 991 //------------------------------------------------------ 992 // TODO : retire OOO 993 if (i == 0) 994 { 995 switch (state) 996 { 997 // case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 998 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 999 default : {break;} // else, no change 1000 } 1001 } 1002 1003 // Write new state 1004 entry->state = state; 1005 1006 // Test if this instruction is the last of event 1007 if ((reg_EVENT_STATE [front_end_id][context_id] != COMMIT_EVENT_STATE_NO_EVENT) and 1008 (reg_EVENT_LAST_NUM_BANK [front_end_id][context_id] == num_bank ) and 1009 (reg_EVENT_LAST_NUM_PTR [front_end_id][context_id] == entry->ptr )) 1010 { 1011 log_printf(TRACE,Commit_unit,FUNCTION," * Stop Scan !!!"); 1012 1013 EVENT_LAST [front_end_id][context_id] = true; 1014 } 1015 } 1016 } 1017 } 1018 } 1019 1020 705 1021 706 1022 #ifdef STATISTICS … … 709 1025 *(_stat_bank_nb_inst [i]) += _rob[i].size(); 710 1026 #endif 1027 } 1028 1029 // =================================================================== 1030 // =====[ OTHER ]===================================================== 1031 // =================================================================== 711 1032 712 1033 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) … … 715 1036 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); 716 1037 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); 1038 log_printf(TRACE,Commit_unit,FUNCTION," * num_ptr_tail : %d",reg_NUM_PTR_TAIL ); 717 1039 718 1040 for (uint32_t i=0; i<_param->_nb_front_end; i++) … … 720 1042 { 721 1043 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] - %d",i,j,_param->_translate_num_context_to_num_thread [i][j]); 722 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); 723 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); 724 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); 725 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); 726 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); 727 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 728 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 1044 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s - %s",toString(reg_EVENT_STATE [i][j]).c_str(),toString(commit_event_state_to_event_state(reg_EVENT_STATE [i][j])).c_str()); 1045 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); 1046 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STOP : %d",reg_EVENT_STOP [i][j]); 1047 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT : %d (bank %d, ptr %d)",((reg_EVENT_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_NUM_BANK [i][j]), reg_EVENT_NUM_BANK [i][j],reg_EVENT_NUM_PTR [i][j]); 1048 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_CAN_RESTART : %d",reg_EVENT_CAN_RESTART [i][j]); 1049 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_PACKET : %d",reg_EVENT_PACKET[i][j]); 1050 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d",reg_EVENT_LAST [i][j]); 1051 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_LAST : %d (bank %d, ptr %d)",((reg_EVENT_LAST_NUM_PTR [i][j] << _param->_shift_num_slot) | reg_EVENT_LAST_NUM_BANK [i][j]), reg_EVENT_LAST_NUM_BANK [i][j],reg_EVENT_LAST_NUM_PTR [i][j]); 1052 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); 1053 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); 1054 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 1055 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 729 1056 } 730 1057 1058 std::list<entry_t*>::iterator iter [_param->_nb_bank]; 731 1059 for (uint32_t i=0; i<_param->_nb_bank; i++) 732 1060 { 733 1061 uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; 734 735 log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); 1062 // log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); 1063 1064 iter [num_bank] = _rob[num_bank].begin(); 1065 } 1066 1067 bool all_empty = false; 1068 while (not all_empty) 1069 { 1070 all_empty = true; 736 1071 737 for (std::list<entry_t*>::iterator it=_rob[num_bank].begin(); 738 it!=_rob[num_bank].end(); 739 it++) 1072 for (uint32_t i=0; i<_param->_nb_bank; i++) 740 1073 { 741 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", 742 num_bank , 743 (*it)->ptr , 744 (((*it)->ptr << _param->_shift_num_slot) | num_bank), 745 (*it)->front_end_id , 746 (*it)->context_id , 747 (*it)->rename_unit_id , 748 (*it)->depth , 749 (*it)->type , 750 (*it)->operation , 751 (*it)->is_delay_slot , 752 (*it)->use_store_queue , 753 (*it)->store_queue_ptr_write , 754 (*it)->use_load_queue , 755 (*it)->load_queue_ptr_write , 756 toString((*it)->state).c_str() ); 757 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 758 (*it)->read_ra , 759 (*it)->num_reg_ra_log , 760 (*it)->num_reg_ra_phy , 761 (*it)->read_rb , 762 (*it)->num_reg_rb_log , 763 (*it)->num_reg_rb_phy , 764 (*it)->read_rc , 765 (*it)->num_reg_rc_log , 766 (*it)->num_reg_rc_phy , 767 (*it)->write_rd , 768 (*it)->num_reg_rd_log , 769 (*it)->num_reg_rd_phy_old , 770 (*it)->num_reg_rd_phy_new , 771 (*it)->write_re , 772 (*it)->num_reg_re_log , 773 (*it)->num_reg_re_phy_old , 774 (*it)->num_reg_re_phy_new ); 775 776 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", 777 (*it)->exception_use , 778 (*it)->exception , 779 (*it)->flags , 780 (*it)->no_sequence , 781 (*it)->speculative , 782 (*it)->address , 783 (*it)->address<<2 , 784 (*it)->address_next , 785 (*it)->address_next<<2 786 ); 1074 uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; 1075 1076 std::list<entry_t*>::iterator it = iter[num_bank]; 1077 if (it != _rob[num_bank].end()) 1078 { 1079 all_empty = false; 1080 1081 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d][%.4d] (%.4d) %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s", 1082 num_bank , 1083 (*it)->ptr , 1084 (((*it)->ptr << _param->_shift_num_slot) | num_bank), 1085 (*it)->front_end_id , 1086 (*it)->context_id , 1087 (*it)->rename_unit_id , 1088 (*it)->depth , 1089 (*it)->type , 1090 (*it)->operation , 1091 (*it)->is_delay_slot , 1092 (*it)->use_store_queue , 1093 (*it)->store_queue_ptr_write , 1094 (*it)->use_load_queue , 1095 (*it)->load_queue_ptr_write , 1096 toString((*it)->state).c_str() ); 1097 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 1098 (*it)->read_ra , 1099 (*it)->num_reg_ra_log , 1100 (*it)->num_reg_ra_phy , 1101 (*it)->read_rb , 1102 (*it)->num_reg_rb_log , 1103 (*it)->num_reg_rb_phy , 1104 (*it)->read_rc , 1105 (*it)->num_reg_rc_log , 1106 (*it)->num_reg_rc_phy , 1107 (*it)->write_rd , 1108 (*it)->num_reg_rd_log , 1109 (*it)->num_reg_rd_phy_old , 1110 (*it)->num_reg_rd_phy_new , 1111 (*it)->write_re , 1112 (*it)->num_reg_re_log , 1113 (*it)->num_reg_re_phy_old , 1114 (*it)->num_reg_re_phy_new ); 1115 1116 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", 1117 (*it)->exception_use , 1118 (*it)->exception , 1119 (*it)->flags , 1120 (*it)->no_sequence , 1121 (*it)->speculative , 1122 (*it)->address , 1123 (*it)->address<<2 , 1124 (*it)->address_next , 1125 (*it)->address_next<<2 1126 ); 1127 1128 iter [num_bank] ++; 1129 } 787 1130 } 788 1131 } … … 822 1165 ) 823 1166 if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) 824 throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address ( %x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"),1167 throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (0x%x) is different of reg_PC_CURRENT[%d][%d] (0x%x).\n"), 825 1168 entry->address, 826 1169 entry->front_end_id, -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp
r110 r122 40 40 test.error(_("nb_bank must be a multiple of size_queue.\n")); 41 41 42 if (_nb_inst_reexecute != 1)43 test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"));42 // if (_nb_inst_reexecute != 1) 43 // test.error(_("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n")); 44 44 45 45 for (uint32_t i=0; i<_nb_front_end; ++i)
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