- Timestamp:
- Jun 26, 2009, 10:43:23 AM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end
- Files:
-
- 28 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r124 r128 50 50 reg_STATE [i] = CONTEXT_STATE_OK; 51 51 reg_INTERRUPT_ENABLE [i] = 0; 52 reg_EVENT_DEPTH [i] = 0; // unacessary 52 53 reg_EVENT_ADDRESS [i] = 0; // not necessary 54 reg_EVENT_ADDRESS_EPCR [i] = 0; // not necessary 55 reg_EVENT_ADDRESS_EPCR_VAL [i] = 0; // not necessary 56 reg_EVENT_ADDRESS_EEAR [i] = 0; // not necessary 57 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; // not necessary 58 reg_EVENT_IS_DELAY_SLOT [i] = 0; // not necessary 59 reg_EVENT_IS_DS_TAKE [i] = 0; // not necessary 60 reg_EVENT_DEPTH [i] = 0; // not necessary 61 reg_EVENT_FLUSH_ONLY [i] = 0; // not necessary 53 62 } 54 63 } … … 236 245 reg_STATE [i] = state; 237 246 } 247 248 // ------------------------------------------------------------------- 249 // -----[ BRANCH_EVENT ]---------------------------------------------- 250 // ------------------------------------------------------------------- 251 for (uint32_t i=0; i<_param->_nb_context; ++i) 252 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) 253 { 254 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); 255 256 context_state_t state = reg_STATE [i]; 257 258 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; 259 Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; 260 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; 261 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i]; 262 263 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 264 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 265 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 266 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 267 268 // priority : miss_load > miss_branch > excep > spr/sync 269 uint8_t priority0 = get_priority(state); 270 uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss 271 272 // is_valid = can modify local information 273 // if context_state_ok : yes 274 // if context_state_ko : test the depth, and the priority of event 275 bool is_valid = ((state == CONTEXT_STATE_OK) or 276 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or 277 // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or 278 (depth1< depth0) or 279 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth 280 281 bool is_invalid = priority0 == PRIORITY_MISS_LOAD; 282 283 #ifdef DEBUG_TEST 284 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and 285 (depth0 != depth1)) 286 throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str())); 287 #endif 288 289 log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str()); 290 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 291 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 292 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 293 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 294 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 295 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 296 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 297 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 298 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 299 log_printf(TRACE,Context_State,FUNCTION," * is_invalid : %d",is_invalid); 300 301 if (is_valid and not is_invalid) 302 { 303 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 304 305 if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) 306 { 307 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) 308 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR; 309 // #else 310 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND; 311 // #endif 312 } 313 else 314 { 315 Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]); 316 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 317 318 log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val ); 319 log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue); 320 321 if (can_continue) 322 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 323 else 324 { 325 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT) 326 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 327 // #else 328 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; 329 // #endif 330 } 331 332 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 333 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next 334 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; 335 //reg_EVENT_ADDRESS_EEAR [i] = 0; 336 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; 337 reg_EVENT_IS_DELAY_SLOT [i] = 1; 338 reg_EVENT_IS_DS_TAKE [i] = dest_val; 339 reg_EVENT_DEPTH [i] = depth; 340 reg_EVENT_FLUSH_ONLY [i] = can_continue; 341 } 342 } 343 } 344 345 // ------------------------------------------------------------------- 346 // -----[ DECOD_EVENT ]----------------------------------------------- 347 // ------------------------------------------------------------------- 348 349 for (uint32_t i=0; i<_param->_nb_decod_unit; i++) 350 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) 351 { 352 log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); 353 354 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; 355 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; 356 Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; 357 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; 358 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context]; 359 360 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 361 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 362 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 363 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); 364 365 context_state_t state = reg_STATE [context]; 366 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); 367 368 // miss_load > miss_branch > excep > spr/sync 369 uint8_t priority0 = get_priority(state); 370 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE; 371 372 // is_valid = can modify local information 373 // if context_state_ok : yes 374 // if context_state_ko : test the depth, and the priority of envent 375 376 bool is_valid = ((state == CONTEXT_STATE_OK) or 377 (depth1< depth0) or 378 ((depth1==depth0) and (priority1>=priority0))); 379 380 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth ); 381 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur ); 382 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min ); 383 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max ); 384 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 ); 385 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 ); 386 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 ); 387 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 ); 388 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid ); 389 390 if (is_valid) 391 { 392 log_printf(TRACE,Context_State,FUNCTION," * is_valid"); 393 394 // decod : 395 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) 396 context_state_t state_next = state; 397 Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); 398 Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); 399 400 switch (type) 401 { 402 case EVENT_TYPE_EXCEPTION : 403 { 404 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION"); 405 406 state_next = CONTEXT_STATE_KO_EXCEP; 407 408 break; 409 } 410 case EVENT_TYPE_SPR_ACCESS : 411 { 412 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS"); 413 414 // state_next = CONTEXT_STATE_KO_SPR ; 415 state_next = CONTEXT_STATE_KO_SPR_EXEC; 416 address++; // take next address 417 // if (is_delay_slot) 418 // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); 419 break; 420 } 421 case EVENT_TYPE_MSYNC : 422 { 423 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC"); 424 425 // state_next = CONTEXT_STATE_KO_MSYNC; 426 state_next = CONTEXT_STATE_KO_MSYNC_EXEC; 427 address++; // take next address 428 // if (is_delay_slot) 429 // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n"); 430 break; 431 } 432 case EVENT_TYPE_PSYNC : 433 { 434 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC"); 435 436 // state_next = CONTEXT_STATE_KO_PSYNC; 437 state_next = CONTEXT_STATE_KO_PSYNC_FLUSH; 438 address++; // take next address 439 if (is_delay_slot) 440 throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n"); 441 break; 442 } 443 case EVENT_TYPE_CSYNC : 444 { 445 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC"); 446 447 // state_next = CONTEXT_STATE_KO_CSYNC; 448 state_next = CONTEXT_STATE_KO_CSYNC_FLUSH; 449 address++; // take next address 450 if (is_delay_slot) 451 throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n"); 452 break; 453 } 454 case EVENT_TYPE_NONE : 455 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 456 case EVENT_TYPE_LOAD_MISS_SPECULATION : 457 // case EVENT_TYPE_BRANCH_NO_ACCURATE : 458 default : 459 { 460 throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); 461 } 462 } 463 464 reg_STATE [context] = state_next; 465 reg_EVENT_ADDRESS [context] = address; 466 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); 467 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; 468 //reg_EVENT_ADDRESS_EEAR [context] 469 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; 470 reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; 471 //reg_EVENT_IS_DS_TAKE [context] = 0; 472 reg_EVENT_DEPTH [context] = depth; 473 reg_EVENT_FLUSH_ONLY [context] = false; 474 } 475 } 238 476 239 477 // ------------------------------------------------------------------- … … 283 521 284 522 // ------------------------------------------------------------------- 285 // -----[ BRANCH_EVENT ]----------------------------------------------286 // -------------------------------------------------------------------287 for (uint32_t i=0; i<_param->_nb_context; ++i)288 if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])289 {290 log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);291 292 context_state_t state = reg_STATE [i];293 294 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;295 Tdepth_t depth_cur = reg_EVENT_DEPTH [i];296 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;297 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i];298 299 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));300 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));301 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));302 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));303 304 // priority : miss_load > miss_branch > excep > spr/sync305 uint8_t priority0 = get_priority(state);306 uint8_t priority1 = PRIORITY_MISS_BRANCH; // miss307 308 // is_valid = can modify local information309 // if context_state_ok : yes310 // if context_state_ko : test the depth, and the priority of event311 bool is_valid = ((state == CONTEXT_STATE_OK) or312 (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or313 // (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or314 (depth1< depth0) or315 ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth316 317 bool is_invalid = priority0 == PRIORITY_MISS_LOAD;318 319 #ifdef DEBUG_TEST320 if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and321 (depth0 != depth1))322 throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str()));323 #endif324 325 log_printf(TRACE,Context_State,FUNCTION," * state : %s",toString(state).c_str());326 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );327 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );328 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );329 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );330 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );331 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );332 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );333 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );334 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );335 336 if (is_valid and not is_invalid)337 {338 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;339 340 if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)341 {342 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)343 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;344 // #else345 reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;346 // #endif347 }348 else349 {350 Tcontrol_t can_continue = PORT_READ(in_BRANCH_EVENT_CAN_CONTINUE [i]);351 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);352 353 log_printf(TRACE,Context_State,FUNCTION," * dest_val : %d",dest_val );354 log_printf(TRACE,Context_State,FUNCTION," * can_continue: %d",can_continue);355 356 if (can_continue)357 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;358 else359 {360 // #if (MANAGE_EVENT == MANAGE_EVENT_NO_WAIT)361 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;362 // #else363 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND;364 // #endif365 }366 367 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot368 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next369 reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;370 //reg_EVENT_ADDRESS_EEAR [i] = 0;371 reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;372 reg_EVENT_IS_DELAY_SLOT [i] = 1;373 reg_EVENT_IS_DS_TAKE [i] = dest_val;374 reg_EVENT_DEPTH [i] = depth;375 reg_EVENT_FLUSH_ONLY [i] = can_continue;376 }377 }378 }379 380 // -------------------------------------------------------------------381 523 // -----[ BRANCH_COMPLETE ]---------------------------------------------- 382 524 // ------------------------------------------------------------------- … … 429 571 reg_EVENT_DEPTH [context_id] = depth; 430 572 reg_EVENT_FLUSH_ONLY [context_id] = false; 431 }432 }433 434 // -------------------------------------------------------------------435 // -----[ DECOD_EVENT ]-----------------------------------------------436 // -------------------------------------------------------------------437 438 for (uint32_t i=0; i<_param->_nb_decod_unit; i++)439 if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])440 {441 log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);442 443 Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;444 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;445 Tdepth_t depth_cur = reg_EVENT_DEPTH [context];446 Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;447 Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];448 449 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));450 Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));451 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));452 // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));453 454 context_state_t state = reg_STATE [context];455 Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);456 457 // miss_load > miss_branch > excep > spr/sync458 uint8_t priority0 = get_priority(state);459 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?PRIORITY_EXCEPTION:PRIORITY_NONE;460 461 // is_valid = can modify local information462 // if context_state_ok : yes463 // if context_state_ko : test the depth, and the priority of envent464 465 bool is_valid = ((state == CONTEXT_STATE_OK) or466 (depth1< depth0) or467 ((depth1==depth0) and (priority1>=priority0)));468 469 log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );470 log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );471 log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );472 log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );473 log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );474 log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );475 log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );476 log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );477 log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );478 479 if (is_valid)480 {481 log_printf(TRACE,Context_State,FUNCTION," * is_valid");482 483 // decod :484 // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)485 context_state_t state_next = state;486 Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);487 Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);488 489 switch (type)490 {491 case EVENT_TYPE_EXCEPTION :492 {493 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");494 495 state_next = CONTEXT_STATE_KO_EXCEP;496 497 break;498 }499 case EVENT_TYPE_SPR_ACCESS :500 {501 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");502 503 // state_next = CONTEXT_STATE_KO_SPR ;504 state_next = CONTEXT_STATE_KO_SPR_EXEC;505 address++; // take next address506 // if (is_delay_slot)507 // throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");508 break;509 }510 case EVENT_TYPE_MSYNC :511 {512 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");513 514 // state_next = CONTEXT_STATE_KO_MSYNC;515 state_next = CONTEXT_STATE_KO_MSYNC_EXEC;516 address++; // take next address517 // if (is_delay_slot)518 // throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");519 break;520 }521 case EVENT_TYPE_PSYNC :522 {523 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");524 525 // state_next = CONTEXT_STATE_KO_PSYNC;526 state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;527 address++; // take next address528 if (is_delay_slot)529 throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");530 break;531 }532 case EVENT_TYPE_CSYNC :533 {534 log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");535 536 // state_next = CONTEXT_STATE_KO_CSYNC;537 state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;538 address++; // take next address539 if (is_delay_slot)540 throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");541 break;542 }543 case EVENT_TYPE_NONE :544 case EVENT_TYPE_BRANCH_MISS_SPECULATION :545 case EVENT_TYPE_LOAD_MISS_SPECULATION :546 // case EVENT_TYPE_BRANCH_NO_ACCURATE :547 default :548 {549 throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));550 }551 }552 553 reg_STATE [context] = state_next;554 reg_EVENT_ADDRESS [context] = address;555 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);556 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;557 //reg_EVENT_ADDRESS_EEAR [context]558 reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;559 reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;560 //reg_EVENT_IS_DS_TAKE [context] = 0;561 reg_EVENT_DEPTH [context] = depth;562 reg_EVENT_FLUSH_ONLY [context] = false;563 573 } 564 574 } … … 706 716 } 707 717 718 // ------------------------------------------------------------------- 719 // -----[ INTERRUPT ]------------------------------------------------- 720 // ------------------------------------------------------------------- 708 721 for (uint32_t i=0; i<_param->_nb_context; ++i) 709 722 { -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
r123 r128 90 90 DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE ,_param->_nb_context,1); 91 91 DELETE1_SIGNAL(in_CONTEXT_EVENT ,_param->_nb_context,1); 92 DELETE1_SIGNAL(in_CONTEXT_DEPTH_VAL ,_param->_nb_context,1); 92 93 DELETE1_SIGNAL(in_CONTEXT_DEPTH ,_param->_nb_context,_param->_size_depth); 93 94 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp
r112 r128 35 35 DELETE0_SIGNAL(out_ADDRESS_BRANCH_STATE ,_param->_size_branch_state ); 36 36 DELETE0_SIGNAL(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); 37 DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,1,_param->_nb_instruction);37 DELETE1_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction,1); 38 38 39 39 DELETE0_SIGNAL(out_PREDICT_VAL ,1); … … 48 48 DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); 49 49 DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); 50 DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE ,1,_param->_nb_instruction);50 DELETE1_SIGNAL(in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction,1); 51 51 52 52 DELETE0_SIGNAL( in_EVENT_VAL ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
r123 r128 28 28 { 29 29 // nothing is valid 30 reg_PC_ACCESS_VAL = 0; 31 32 reg_PC_CURRENT_VAL = 0; 33 34 reg_PC_NEXT_VAL = 1; 35 reg_PC_NEXT = 0x100>>2; 36 reg_PC_NEXT_IS_DS_TAKE = 0; 30 reg_PC_ACCESS_VAL = 0; 31 reg_PC_ACCESS = 0;// not necessary 32 reg_PC_ACCESS_IS_DS_TAKE = 0;// not necessary 33 for (uint32_t i=0; i<_param->_nb_instruction; i++) 34 reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = 0;// not necessary 35 reg_PC_ACCESS_INST_IFETCH_PTR = 0;// not necessary 36 reg_PC_ACCESS_BRANCH_STATE = 0;// not necessary 37 reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = 0;// not necessary 38 39 reg_PC_CURRENT_VAL = 0; 40 reg_PC_CURRENT = 0;// not necessary 41 reg_PC_CURRENT_IS_DS_TAKE = 0;// not necessary 42 for (uint32_t i=0; i<_param->_nb_instruction; i++) 43 reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = 0;// not necessary 44 reg_PC_CURRENT_INST_IFETCH_PTR = 0;// not necessary 45 reg_PC_CURRENT_BRANCH_STATE = 0;// not necessary 46 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = 0;// not necessary 47 48 reg_PC_NEXT_VAL = 1; 49 reg_PC_NEXT = 0x100>>2; 50 reg_PC_NEXT_IS_DS_TAKE = 0; 37 51 uint32_t index = reg_PC_NEXT % _param->_nb_instruction; 38 52 for (uint32_t i=0; i<_param->_nb_instruction; i++) 39 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 40 reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; 41 reg_PC_NEXT_INST_IFETCH_PTR = 0; 42 reg_PC_NEXT_BRANCH_STATE = 0; 43 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; 44 45 46 reg_PC_NEXT_NEXT_VAL = 0; 53 reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; 54 reg_PC_NEXT_INSTRUCTION_ENABLE [index] = 1; 55 reg_PC_NEXT_INST_IFETCH_PTR = 0; 56 reg_PC_NEXT_BRANCH_STATE = 0; 57 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; 58 59 reg_PC_NEXT_NEXT_VAL = 0; 60 reg_PC_NEXT_NEXT = 0;// not necessary 61 reg_PC_NEXT_NEXT_IS_DS_TAKE = 0;// not necessary 47 62 } 48 63 else -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h
r101 r128 47 47 public : ~ifetch_queue_entry_t (void) 48 48 { 49 delete _instruction ;50 delete _instruction_enable;49 delete [] _instruction ; 50 delete [] _instruction_enable; 51 51 } 52 53 // public : friend std::ostream& operator<< (std::ostream& output,54 // ifetch_queue_entry_t & x)55 // {56 // output << ;57 // return output;58 // }59 60 52 }; 61 53 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp
r119 r128 31 31 32 32 for (uint32_t i=0; i<_param->_size_queue; i++) 33 _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; 33 { 34 _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; 35 _queue [i]->_address = 0; // not necessary 36 _queue [i]->_inst_ifetch_ptr = 0; // not necessary 37 _queue [i]->_branch_state = 0; // not necessary 38 _queue [i]->_branch_update_prediction_id = 0; // not necessary 39 _queue [i]->_exception = 0; // not necessary 40 41 for (uint32_t j=0; j<_param->_nb_instruction; j++) 42 { 43 _queue [i]->_instruction [j] = 0; // not necessary 44 _queue [i]->_instruction_enable [j] = 0; // not necessary 45 } 46 } 34 47 } 35 48 else -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp
r123 r128 60 60 DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); 61 61 DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch); 62 DELETE1_SIGNAL(out_DECOD_VAL , 1,_param->_nb_instruction);63 DELETE1_SIGNAL( in_DECOD_ACK , 1,_param->_nb_instruction);62 DELETE1_SIGNAL(out_DECOD_VAL ,_param->_nb_instruction,1); 63 DELETE1_SIGNAL( in_DECOD_ACK ,_param->_nb_instruction,1); 64 64 DELETE1_SIGNAL(out_DECOD_INSTRUCTION ,_param->_nb_instruction,_param->_size_instruction); 65 65 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Branch_Target_Buffer_Glue.h
r82 r128 82 82 public : SC_IN (Tcontrol_t ) *** in_PREDICT_REGISTER_IS_ACCURATE ; //[nb_inst_predict][associativity] 83 83 84 public : SC_IN (T ptr_t) ** in_PREDICT_SORT_VAL ; //[nb_inst_predict]84 public : SC_IN (Tcontrol_t ) ** in_PREDICT_SORT_VAL ; //[nb_inst_predict] 85 85 public : SC_IN (Tptr_t ) ** in_PREDICT_SORT_INDEX ; //[nb_inst_predict] 86 86 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp
r112 r128 74 74 if (_param->_have_port_victim) 75 75 { 76 ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_VAL ,"sort_val" ,Tptr_t,1);77 ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_INDEX ,"sort_index",Tptr_t,_param->_size_victim);76 ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_VAL , "sort_val" ,Tcontrol_t ,1); 77 ALLOC1_SIGNAL_IN ( in_PREDICT_SORT_INDEX , "sort_index" ,Tptr_t ,_param->_size_victim); 78 78 79 79 ALLOC1_SIGNAL_OUT(out_PREDICT_VICTIM_VAL , "victim_val" ,Tcontrol_t , 1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp
r123 r128 38 38 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); 39 39 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); 40 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * port_victim : %d",_param->_have_port_victim); 40 41 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val ); 41 42 log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); … … 51 52 52 53 // Multiplexor 54 53 55 PORT_WRITE(out_PREDICT_HIT [i],hit); 54 56 PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],address_src); … … 64 66 victim_ack 65 67 )); 68 66 69 PORT_WRITE(out_PREDICT_REGISTER_VAL [i], ( 67 70 val and … … 84 87 PORT_WRITE(out_PREDICT_VICTIM_INDEX [i], index); 85 88 } 89 86 90 } 87 91 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp
r107 r128 29 29 for (uint32_t i=0; i<_param->_size_bank; i++) 30 30 for (uint32_t j=0; j<_param->_associativity; j++) 31 reg_BTB [i][j]._val = false; 31 { 32 reg_BTB [i][j]._val = false; 33 reg_BTB [i][j]._context = 0; // not necessary 34 reg_BTB [i][j]._address_dest_val = 0; // not necessary 35 reg_BTB [i][j]._address_src = 0; // not necessary 36 reg_BTB [i][j]._address_dest = 0; // not necessary 37 reg_BTB [i][j]._condition = 0; // not necessary 38 reg_BTB [i][j]._last_take = 0; // not necessary 39 reg_BTB [i][j]._accurate = 0; // not necessary 40 } 32 41 } 33 42 else -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp
r115 r128 64 64 { 65 65 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 66 delete_component_sort [i];66 delete _component_sort [i]; 67 67 delete [] _component_sort; 68 delete _component_victim;68 delete _component_victim; 69 69 } 70 70 delete _component_branch_target_buffer_glue; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp
r88 r128 35 35 } 36 36 37 //_stat->add_stat(_component_branch_target_buffer_glue ->_stat);37 _stat->add_stat(_component_branch_target_buffer_glue ->_stat); 38 38 _stat->add_stat(_component_branch_target_buffer_register->_stat); 39 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue/src/Parameters.cpp
r111 r128 80 80 { 81 81 log_begin(Meta_Predictor_Glue,FUNCTION); 82 83 DELETE1(_predictor_history_mask ,_nb_predictor); 84 DELETE1(_predictor_history_shift_msb,_nb_predictor); 85 DELETE1(_predictor_history_shift ,_nb_predictor); 86 82 87 log_end(Meta_Predictor_Glue,FUNCTION); 83 88 }; … … 88 93 { 89 94 log_begin(Meta_Predictor_Glue,FUNCTION); 90 91 DELETE1(_predictor_history_mask ,_nb_predictor);92 DELETE1(_predictor_history_shift,_nb_predictor);93 94 95 log_end(Meta_Predictor_Glue,FUNCTION); 95 96 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_deallocation.cpp
r112 r128 45 45 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 46 46 47 DELETE0(_component_glue); 48 DELETE1(_component_two_level_branch_predictor,_param->_nb_predictor); 47 delete _component_glue; 48 for (uint32_t i=0; i<_param->_nb_predictor; ++i) 49 delete _component_two_level_branch_predictor [i]; 50 delete [] _component_two_level_branch_predictor; 49 51 50 52 delete _component; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Meta_Predictor_statistics_allocation.cpp
r110 r128 28 28 "Meta_Predictor", 29 29 param_statistics); 30 31 for (uint32_t i=0; i<_param->_nb_predictor; ++i) 32 _stat->add_stat(_component_two_level_branch_predictor [i]->_stat); 33 _stat->add_stat(_component_glue ->_stat); 30 34 31 35 log_end(Meta_Predictor,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/src/Parameters.cpp
r112 r128 122 122 log_begin(Meta_Predictor,FUNCTION); 123 123 124 DELETE1(_param_two_level_branch_predictor, _nb_predictor); 124 delete _param_glue; 125 for (uint32_t i=0; i<_nb_predictor; ++i) 126 delete _param_two_level_branch_predictor [i]; 127 delete [] _param_two_level_branch_predictor; 125 128 126 129 DELETE1(_predictor_size_history , _nb_predictor); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_statistics_allocation.cpp
r81 r128 28 28 param_statistics); 29 29 30 _stat->add_stat(_component_glue->_stat); 30 if (_param->_have_component_meta_predictor) 31 _stat->add_stat(_component_meta_predictor->_stat); 32 _stat->add_stat(_component_glue ->_stat); 31 33 32 34 log_printf(FUNC,Direction,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
r111 r128 37 37 // reg_PREDICT_BOTTOM [i] = 0; 38 38 reg_PREDICT_NB_ELT [i] = 0; 39 40 for (uint32_t j=0; j<_param->_size_queue [i]; ++j) 41 reg_stack [i][j]._address = 0; // not necessary 39 42 } 40 43 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp
r122 r128 63 63 for (uint32_t i=0; i<_nb_thread; i++) 64 64 _have_thread[i] = false; 65 for (uint32_t i=0; i<_nb_ context; i++)65 for (uint32_t i=0; i<_nb_thread; i++) 66 66 _have_thread[_translate_num_context_to_num_thread [i]] = true; 67 67 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r122 r128 172 172 173 173 #if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true) 174 for (uint32_t i=0; i<_param->_nb_thread; ++i) 175 if (_param->_have_thread [i]) 176 { 177 branchement_log_file [i].close(); 178 } 174 { 175 for (uint32_t i=0; i<_param->_nb_thread; ++i) 176 if (_param->_have_thread [i]) 177 { 178 branchement_log_file [i].close(); 179 } 180 delete [] branchement_log_file; 181 } 179 182 #endif 180 183 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp
r97 r128 29 29 delete _stat; 30 30 31 DELETE2(_stat_nb_branch_hit ,_param->_nb_context,MAX_BRANCH_CONDITION); 32 DELETE2(_stat_nb_branch_miss ,_param->_nb_context,MAX_BRANCH_CONDITION); 33 DELETE1(_stat_nb_branch_unused ,_param->_nb_context); 34 DELETE1(_stat_ufpt_queue_nb_elt ,_param->_nb_context); 35 DELETE1(_stat_upt_queue_nb_elt ,_param->_nb_context); 31 DELETE2(_stat_nb_branch_hit ,_param->_nb_context,MAX_BRANCH_CONDITION); 32 DELETE2(_stat_nb_branch_miss ,_param->_nb_context,MAX_BRANCH_CONDITION); 33 DELETE1(_stat_nb_branch_unused ,_param->_nb_context); 34 35 DELETE1(_stat_nb_branch_ifetch_prediction,_param->_nb_context); 36 DELETE1(_stat_nb_branch_accurate ,_param->_nb_context); 37 38 DELETE1(_stat_ufpt_queue_nb_elt ,_param->_nb_context); 39 DELETE1(_stat_upt_queue_nb_elt ,_param->_nb_context); 36 40 37 41 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r124 r128 34 34 { 35 35 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 36 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 36 { 37 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 38 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition = 0; // not necessary 39 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary 40 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary 41 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary 42 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary 43 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history = 0; // not necessary 44 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary 45 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary 46 } 37 47 reg_UFPT_BOTTOM [i] = 0; 38 48 reg_UFPT_TOP [i] = 0; … … 42 52 43 53 for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) 44 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; 54 { 55 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; 56 reg_UPDATE_PREDICTION_TABLE [i][j]._condition = 0; // not necessary 57 reg_UPDATE_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary 58 reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary 59 reg_UPDATE_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary 60 reg_UPDATE_PREDICTION_TABLE [i][j]._good_take = 0; // not necessary 61 reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary 62 reg_UPDATE_PREDICTION_TABLE [i][j]._history = 0; // not necessary 63 reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary 64 reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary 65 reg_UPDATE_PREDICTION_TABLE [i][j]._ifetch_prediction= 0; // not necessary 66 reg_UPDATE_PREDICTION_TABLE [i][j]._miss_commit = 0; // not necessary 67 reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = 0; // not necessary 68 reg_UPDATE_PREDICTION_TABLE [i][j]._miss_prediction = 0; // not necessary 69 } 45 70 reg_UPT_BOTTOM [i] = 0; 46 71 reg_UPT_TOP [i] = 0; … … 54 79 reg_UPT_EVENT_STATE [i] = UPT_EVENT_STATE_OK; 55 80 56 // reg_EVENT_VAL [i] = false; 57 // reg_EVENT_STATE [i] = EVENT_STATE_OK; 58 // reg_EVENT_IS_BRANCH [i] = true; 81 reg_EVENT_UPT_PTR [i] = 0; // not necessary 82 reg_EVENT_UPT_FULL [i] = 0; // not necessary 83 84 // reg_EVENT_STATE [i] = EVENT_STATE_OK; // not necessary 85 // reg_EVENT_IS_BRANCH [i] = true ; // not necessary 86 87 reg_EVENT_DEPTH [i] = 0; // not necessary 88 reg_EVENT_ADDRESS_SRC [i] = 0; // not necessary 89 reg_EVENT_ADDRESS_DEST_VAL [i] = 0; // not necessary 90 reg_EVENT_ADDRESS_DEST [i] = 0; // not necessary 91 reg_EVENT_CAN_CONTINUE [i] = 0; // not necessary 92 59 93 } 60 94 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
r119 r128 66 66 DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); 67 67 // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); 68 //DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth);68 DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); 69 69 // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); 70 70 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp
r111 r128 223 223 224 224 test (name,param); 225 226 delete param; 225 227 } 226 228 catch (morpheo::ErrorMorpheo & error) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
r108 r128 47 47 sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); 48 48 sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); 49 50 sc_signal<Tcontrol_t > ** out_ICACHE_REQ_VAL ; 51 sc_signal<Tcontrol_t > ** in_ICACHE_REQ_ACK ; 52 //sc_signal<Tcontext_t > ** out_ICACHE_REQ_THREAD_ID ; 53 sc_signal<Tpacket_t > ** out_ICACHE_REQ_PACKET_ID ; 54 sc_signal<Ticache_instruction_t> ** out_ICACHE_REQ_ADDRESS ; 55 sc_signal<Ticache_type_t > ** out_ICACHE_REQ_TYPE ; 56 sc_signal<Tcontrol_t > ** in_ICACHE_RSP_VAL ; 57 sc_signal<Tcontrol_t > ** out_ICACHE_RSP_ACK ; 58 //sc_signal<Tcontext_t > ** in_ICACHE_RSP_THREAD_ID ; 59 sc_signal<Tpacket_t > ** in_ICACHE_RSP_PACKET_ID ; 60 sc_signal<Ticache_instruction_t> *** in_ICACHE_RSP_INSTRUCTION ; 61 sc_signal<Ticache_error_t > ** in_ICACHE_RSP_ERROR ; 62 sc_signal<Tcontrol_t > ** out_DECOD_VAL ; 63 sc_signal<Tcontrol_t > ** in_DECOD_ACK ; 64 sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ; 65 sc_signal<Tdepth_t > ** out_DECOD_DEPTH ; 66 sc_signal<Ttype_t > ** out_DECOD_TYPE ; 67 sc_signal<Toperation_t > ** out_DECOD_OPERATION ; 68 sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ; 69 sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ; 70 sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ; 71 sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ; 72 sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ; 73 sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ; 74 sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ; 75 sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ; 76 sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ; 77 sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ; 78 sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ; 79 sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ; 80 sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ; 81 sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ; 82 sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ; 83 sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ; 84 sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ; 85 sc_signal<Texception_t > ** out_DECOD_EXCEPTION ; 86 sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_VAL ; 87 sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_ACK ; 88 sc_signal<Tcontext_t > ** in_BRANCH_COMPLETE_CONTEXT_ID ; 89 sc_signal<Tdepth_t > ** in_BRANCH_COMPLETE_DEPTH ; 90 sc_signal<Taddress_t > ** in_BRANCH_COMPLETE_ADDRESS ; 91 sc_signal<Tcontrol_t > ** in_BRANCH_COMPLETE_NO_SEQUENCE ; 92 sc_signal<Tcontrol_t > ** out_BRANCH_COMPLETE_MISS_PREDICTION; 93 sc_signal<Tcontrol_t > * in_COMMIT_EVENT_VAL ; 94 sc_signal<Tcontrol_t > * out_COMMIT_EVENT_ACK ; 95 sc_signal<Tcontext_t > * in_COMMIT_EVENT_CONTEXT_ID ; 96 sc_signal<Tdepth_t > * in_COMMIT_EVENT_DEPTH ; 97 sc_signal<Tevent_type_t > * in_COMMIT_EVENT_TYPE ; 98 sc_signal<Tcontrol_t > * in_COMMIT_EVENT_IS_DELAY_SLOT ; 99 sc_signal<Taddress_t > * in_COMMIT_EVENT_ADDRESS ; 100 sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 101 sc_signal<Taddress_t > * in_COMMIT_EVENT_ADDRESS_EPCR ; 102 sc_signal<Tcontrol_t > * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; 103 sc_signal<Tgeneral_data_t > * in_COMMIT_EVENT_ADDRESS_EEAR ; 104 sc_signal<Tcontrol_t > ** out_EVENT_VAL ; 105 sc_signal<Tcontrol_t > ** in_EVENT_ACK ; 106 sc_signal<Taddress_t > ** out_EVENT_ADDRESS ; 107 sc_signal<Taddress_t > ** out_EVENT_ADDRESS_NEXT ; 108 sc_signal<Tcontrol_t > ** out_EVENT_ADDRESS_NEXT_VAL ; 109 sc_signal<Tcontrol_t > ** out_EVENT_IS_DS_TAKE ; 110 sc_signal<Tcontrol_t > ** out_SPR_EVENT_VAL ; 111 sc_signal<Tcontrol_t > ** in_SPR_EVENT_ACK ; 112 sc_signal<Tspr_t > ** out_SPR_EVENT_EPCR ; 113 sc_signal<Tcontrol_t > ** out_SPR_EVENT_EEAR_WEN ; 114 sc_signal<Tspr_t > ** out_SPR_EVENT_EEAR ; 115 sc_signal<Tcontrol_t > ** out_SPR_EVENT_SR_DSX ; 116 sc_signal<Tcontrol_t > ** out_SPR_EVENT_SR_TO_ESR ; 117 sc_signal<Tcounter_t > ** in_NB_INST_COMMIT_ALL ; 118 sc_signal<Tcounter_t > ** in_NB_INST_COMMIT_MEM ; 119 sc_signal<Tcounter_t > ** out_NB_INST_DECOD_ALL ; 120 sc_signal<Tdepth_t > ** out_DEPTH_MIN ; 121 sc_signal<Tdepth_t > ** out_DEPTH_MAX ; 122 sc_signal<Tcontrol_t > ** out_DEPTH_FULL ; 123 sc_signal<Tcontrol_t > ** in_SPR_SR_IEE ; 124 sc_signal<Tcontrol_t > ** in_SPR_SR_EPH ; 125 sc_signal<Tcontrol_t > ** in_INTERRUPT_ENABLE ; 49 126 50 127 ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_context); … … 68 145 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod); 69 146 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod); 70 #ifdef DEBUG71 147 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod); 72 #endif73 148 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod); 74 149 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod); … … 325 400 DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); 326 401 DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); 327 #ifdef DEBUG328 402 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod); 329 #endif330 403 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); 331 404 DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
r123 r128 109 109 DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); 110 110 111 DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth 112 DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth +1);113 DELETE1_SIGNAL(out_DEPTH_FULL ,_param->_nb_context, _param->_size_depth+1);111 DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); 112 DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth); 113 DELETE1_SIGNAL(out_DEPTH_FULL ,_param->_nb_context,1); 114 114 115 115 DELETE1_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp
r122 r128 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h" 9 #include "Behavioural/include/Allocation.h" 9 10 #include "Common/include/Max.h" 10 11 … … 110 111 uint32_t size_instruction_address = size_general_data - 2; 111 112 112 _array_size_depth = new uint32_t [_nb_context];113 ALLOC1(_array_size_depth ,uint32_t,_nb_context); 113 114 for (uint32_t i=0; i<_nb_context; i++) 114 115 _array_size_depth [i] = log2(_upt_size_queue[i]); 115 116 116 _array_size_nb_inst_decod = new uint32_t [_nb_decod_unit];117 ALLOC1(_array_size_nb_inst_decod ,uint32_t,_nb_decod_unit); 117 118 for (uint32_t i=0; i<_nb_decod_unit; i++) 118 119 _array_size_nb_inst_decod [i] = log2(_size_decod_queue[i]+1); … … 159 160 ); 160 161 161 _translate_context_id_from_decod_unit= new std::vector<uint32_t> [_nb_decod_unit];162 ALLOC1(_translate_context_id_from_decod_unit,std::vector<uint32_t>,_nb_decod_unit); 162 163 163 164 for (uint32_t i=0; i<_nb_context; ++i) 164 165 _translate_context_id_from_decod_unit [_link_context_to_decod_unit[i]].push_back(i); 165 166 166 _decod_unit_nb_context = new uint32_t [_nb_decod_unit];167 _decod_unit_nb_inst_fetch = new uint32_t * [_nb_decod_unit];168 _decod_unit_nb_branch_speculated = new uint32_t * [_nb_decod_unit];169 // _decod_unit_depth = new uint32_t * [_nb_decod_unit];170 _decod_unit_instruction_implemeted = new bool ** [_nb_decod_unit];171 // _have_port_decod_unit_context_id = new bool [_nb_decod_unit];167 ALLOC1(_decod_unit_nb_context ,uint32_t,_nb_decod_unit); 168 ALLOC2(_decod_unit_nb_inst_fetch ,uint32_t,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size()); 169 ALLOC2(_decod_unit_nb_branch_speculated ,uint32_t,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size()); 170 // ALLOC2(_decod_unit_depth ,uint32_t,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size()); 171 ALLOC3(_decod_unit_instruction_implemeted,bool ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size(),NB_INSTRUCTION); 172 // ALLOC2(_have_port_decod_unit_context_id ,bool ,_nb_decod_unit); 172 173 _sum_inst_decod = 0; 173 174 … … 179 180 180 181 _decod_unit_nb_context [i] = size; 181 _decod_unit_nb_inst_fetch [i] = new uint32_t [size]; 182 // _decod_unit_depth [i] = new uint32_t [size]; 183 _decod_unit_nb_branch_speculated [i] = new uint32_t [size]; 184 _decod_unit_instruction_implemeted [i] = new bool * [size]; 185 // _have_port_decod_unit_context_id [i] = size > 0; 182 // _have_port_decod_unit_context_id [i] = size > 0; 186 183 187 184 for (uint32_t j=0; j<size; ++j) … … 191 188 _decod_unit_nb_inst_fetch [i][j] = _nb_inst_fetch [x]; 192 189 _decod_unit_nb_branch_speculated [i][j] = _upt_size_queue [x]; 193 // _decod_unit_depth [i][j] = log2(_upt_size_queue[x]); 194 _decod_unit_instruction_implemeted [i][j] = new bool [NB_INSTRUCTION]; 190 // _decod_unit_depth [i][j] = log2(_upt_size_queue[x]); 195 191 196 192 for (uint32_t k=0; k<NB_INSTRUCTION; ++k) … … 302 298 delete [] _param_ifetch_unit ; 303 299 304 // delete [] _size_ifetch_queue_ptr; 305 // delete [] _size_nb_inst_decod; 306 delete [] _array_size_depth; 307 for (uint32_t i=0; i<_nb_context; ++i) 308 { 309 for (uint32_t j=0; j<_translate_context_id_from_decod_unit [i].size(); ++j) 310 delete [] _decod_unit_instruction_implemeted [i][j]; 311 312 delete [] _decod_unit_nb_inst_fetch [i]; 313 // delete [] _decod_unit_depth [i]; 314 delete [] _decod_unit_nb_branch_speculated [i]; 315 delete [] _decod_unit_instruction_implemeted [i]; 316 } 317 delete [] _decod_unit_nb_inst_fetch ; 318 // delete [] _decod_unit_depth ; 319 delete [] _decod_unit_nb_branch_speculated ; 320 delete [] _decod_unit_instruction_implemeted; 321 322 // delete [] _have_port_decod_unit_context_id; 323 delete [] _decod_unit_nb_context ; 324 delete [] _translate_context_id_from_decod_unit; 300 // DELETE2(_have_port_decod_unit_context_id ,_nb_decod_unit); 301 DELETE3(_decod_unit_instruction_implemeted ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size(),NB_INSTRUCTION); 302 // DELETE2(_decod_unit_depth ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size()); 303 DELETE2(_decod_unit_nb_branch_speculated ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size()); 304 DELETE2(_decod_unit_nb_inst_fetch ,_nb_decod_unit,_translate_context_id_from_decod_unit [it1].size()); 305 DELETE1(_decod_unit_nb_context ,_nb_decod_unit); 306 307 DELETE1(_translate_context_id_from_decod_unit,_nb_decod_unit); 308 DELETE1(_array_size_nb_inst_decod ,_nb_decod_unit); 309 DELETE1(_array_size_depth ,_nb_context); 325 310 326 311 log_end(Front_end,FUNCTION);
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